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Format `-pwires`
author
Eddie Hung
<eddie@fpgeh.com>
Fri, 30 Aug 2019 17:27:07 +0000
(10:27 -0700)
committer
GitHub
<noreply@github.com>
Fri, 30 Aug 2019 17:27:07 +0000
(10:27 -0700)
README.md
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diff --git
a/README.md
b/README.md
index 38ca77862adf9bcc24f85791fa194da7d443f4e1..0195248a0c27cea0b7900a2aa6d8d813bb51e3c0 100644
(file)
--- a/
README.md
+++ b/
README.md
@@
-330,7
+330,7
@@
Verilog Attributes and non-standard features
- The ``parameter`` and ``localparam`` attributes are used to mark wires
that represent module parameters or localparams (when the HDL front-end
- is run in
-pwires
mode).
+ is run in
``-pwires``
mode).
- The ``clkbuf_driver`` attribute can be set on an output port of a blackbox
module to mark it as a clock buffer output, and thus prevent ``clkbufmap``