+// Helper:
+//
+// Given an extended register number, translate it into an index into the
+// register array. This is necessary as the upper 8 extended registers are
+// actually synonyms for the d0-d3/a0-a3 registers.
+//
+//
+
+:function:::int:translate_rreg:int rreg
+{
+
+ /* The higher register numbers actually correspond to the
+ basic machine's address and data registers. */
+ if (rreg > 7 && rreg < 12)
+ return REG_A0 + rreg - 8;
+ else if (rreg > 11 && rreg < 16)
+ return REG_D0 + rreg - 12;
+ else
+ return REG_E0 + rreg;
+}
+
// 1111 0000 0010 00An; mov USP,An
8.0xf0+4.0x2,00,2.AN0:D0m:::mov
"mov"
"mov"
*am33
{
+ int destreg = translate_rreg (SD_, RN0);
+
PC = cia;
- /* The higher register numbers actually correspond to the
- basic machine's address and data registers. */
- if (RN0 > 7 && RN0 < 12)
- State.regs[REG_A0 + RN0 - 8] = State.regs[REG_A0 + AM1];
- else if (RN0 > 11 && RN0 < 16)
- State.regs[REG_D0 + RN0 - 12] = State.regs[REG_A0 + AM1];
- else
- State.regs[REG_E0 + RN0] = State.regs[REG_A0 + AM1] ;
+ State.regs[destreg] = State.regs[REG_A0 + AM1];
}
// 1111 0101 01Dm Rn; mov Dm,Rn
"mov"
*am33
{
+ int destreg = translate_rreg (SD_, RN0);
+
PC = cia;
- /* The higher register numbers actually correspond to the
- basic machine's address and data registers. */
- if (RN0 > 7 && RN0 < 12)
- State.regs[REG_A0 + RN0 - 8] = State.regs[REG_D0 + DM1];
- else if (RN0 > 11 && RN0 < 16)
- State.regs[REG_D0 + RN0 - 12] = State.regs[REG_D0 + DM1];
- else
- State.regs[REG_E0 + RN0] = State.regs[REG_D0 + DM1] ;
+ State.regs[destreg] = State.regs[REG_D0 + DM1];
}
// 1111 0101 10Rm An; mov Rm,An
"mov"
*am33
{
+ int destreg = translate_rreg (SD_, RM1);
+
PC = cia;
- /* The higher register numbers actually correspond to the
- basic machine's address and data registers. */
- if (RM1 > 7 && RM1 < 12)
- State.regs[REG_A0 + AN0] = State.regs[REG_A0 + RM1 - 8];
- else if (RM1 > 11 && RM1 < 16)
- State.regs[REG_A0 + AN0] = State.regs[REG_D0 + RM1 - 12];
- else
- State.regs[REG_A0 + AN0] = State.regs[REG_E0 + RM1];
+ State.regs[REG_A0 + AN0] = State.regs[destreg];
}
// 1111 0101 11Rm Dn; mov Rm,Dn
"mov"
*am33
{
+ int destreg = translate_rreg (SD_, RM1);
+
PC = cia;
- /* The higher register numbers actually correspond to the
- basic machine's address and data registers. */
- if (RM1 > 7 && RM1 < 12)
- State.regs[REG_D0 + DN0] = State.regs[REG_A0 + RM1 - 8];
- else if (RM1 > 11 && RM1 < 16)
- State.regs[REG_D0 + DN0] = State.regs[REG_D0 + RM1 - 12];
- else
- State.regs[REG_D0 + DN0] = State.regs[REG_E0 + RM1];
+ State.regs[REG_D0 + DN0] = State.regs[destreg];
}
PC = cia;
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = State.regs[srcreg];
}
"mov"
*am33
{
- int srcreg, dstreg;
+ int srcreg;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg = REG_D0 + RN0 - 12;
- else
- srcreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RN0);
if (State.regs[srcreg] & 0x80000000)
State.regs[REG_MDR] = -1;
else
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = State.regs[srcreg] & 0xff;
}
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = State.regs[srcreg] & 0xffff;
}
"clr"
*am33
{
- int srcreg, dstreg;
+ int dstreg;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = 0;
-
PSW |= PSW_Z;
PSW &= ~(PSW_V | PSW_C | PSW_N);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
genericAdd (State.regs[srcreg], dstreg);
}
unsigned long reg1, reg2, sum;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
reg1 = State.regs[srcreg];
reg2 = State.regs[dstreg];
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
genericSub (State.regs[srcreg], dstreg);
}
unsigned long reg1, reg2, difference;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
reg1 = State.regs[srcreg];
reg2 = State.regs[dstreg];
int dstreg;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ dstreg = translate_rreg (SD_, RN0);
genericAdd (1, dstreg);
}
int dstreg;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] += 4;
}
int srcreg1, srcreg2;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg1 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg1 = REG_D0 + RN0 - 12;
- else
- srcreg1 = REG_E0 + RN0;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg2 = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg2 = REG_D0 + RM2 - 12;
- else
- srcreg2 = REG_E0 + RM2;
+ srcreg1 = translate_rreg (SD_, RN0);
+ srcreg2 = translate_rreg (SD_, RM2);
genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
}
"mov"
*am33
{
- int srcreg, dstreg;
+ int dstreg;
PC = cia;
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
if (XRM2 == 0)
{
int srcreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
+ srcreg = translate_rreg (SD_, RM2);
if (XRN0 == 0)
{
PC = cia;
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] &= State.regs[srcreg];
z = (State.regs[dstreg] == 0);
int z, n;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] |= State.regs[srcreg];
z = (State.regs[dstreg] == 0);
int z, n;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] ^= State.regs[srcreg];
z = (State.regs[dstreg] == 0);
int z, n;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = ~State.regs[dstreg];
z = (State.regs[dstreg] == 0);
int c, z, n;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
temp = State.regs[dstreg];
c = temp & 1;
PC = cia;
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
c = State.regs[dstreg] & 1;
State.regs[dstreg] >>= State.regs[srcreg];
int z, n;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] <<= State.regs[srcreg];
z = (State.regs[dstreg] == 0);
int n, z;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] <<= 2;
z = (State.regs[dstreg] == 0);
unsigned long value;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
value = State.regs[dstreg];
c = (value & 0x1);
unsigned long value;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
value = State.regs[dstreg];
c = (value & 0x80000000) ? 1 : 0;
int n, z;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
temp = ((signed64)(signed32)State.regs[dstreg]
* (signed64)(signed32)State.regs[srcreg]);
int n, z;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
temp = ((unsigned64)State.regs[dstreg]
* (unsigned64)State.regs[srcreg]);
int n, z;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
temp = State.regs[REG_MDR];
temp <<= 32;
int n, z;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
temp = State.regs[REG_MDR];
temp <<= 32;
int srcreg, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_word (State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
store_word (State.regs[dstreg], State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_byte (State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
store_byte (State.regs[dstreg], State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_half (State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
store_half (State.regs[dstreg], State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_word (State.regs[srcreg]);
State.regs[srcreg] += 4;
}
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
store_word (State.regs[dstreg], State.regs[srcreg]);
State.regs[dstreg] += 4;
}
"mov"
*am33
{
- int srcreg, dstreg;
+ int dstreg;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_word (State.regs[REG_SP]);
}
"mov"
*am33
{
- int srcreg, dstreg;
+ int srcreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- dstreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- dstreg = REG_D0 + RM2 - 12;
- else
- dstreg = REG_E0 + RM2;
-
- store_word (State.regs[REG_SP], State.regs[dstreg]);
+ srcreg = translate_rreg (SD_, RM2);
+ store_word (State.regs[REG_SP], State.regs[srcreg]);
}
// 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
"movbu"
*am33
{
- int srcreg, dstreg;
+ int dstreg;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_byte (State.regs[REG_SP]);
}
"movbu"
*am33
{
- int srcreg, dstreg;
+ int srcreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- dstreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- dstreg = REG_D0 + RM2 - 12;
- else
- dstreg = REG_E0 + RM2;
-
- store_byte (State.regs[REG_SP], State.regs[dstreg]);
+ srcreg = translate_rreg (SD_, RM2);
+ store_byte (State.regs[REG_SP], State.regs[srcreg]);
}
// 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
"movhu"
*am33
{
- int srcreg, dstreg;
+ int dstreg;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_half (State.regs[REG_SP]);
}
"movhu"
*am33
{
- int srcreg, dstreg;
+ int srcreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- dstreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- dstreg = REG_D0 + RM2 - 12;
- else
- dstreg = REG_E0 + RM2;
-
- store_half (State.regs[REG_SP], State.regs[dstreg]);
+ srcreg = translate_rreg (SD_, RM2);
+ store_half (State.regs[REG_SP], State.regs[srcreg]);
}
// 1111 1001 1110 1010 Rm Rn; movhu (Rm+),Rn
int srcreg, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_half (State.regs[srcreg]);
State.regs[srcreg] += 2;
}
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
store_half (State.regs[dstreg], State.regs[srcreg]);
State.regs[dstreg] += 2;
}
int c, v;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg1 = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg1 = REG_D0 + RM2 - 12;
- else
- srcreg1 = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg2 = REG_D0 + RN0 - 12;
- else
- srcreg2 = REG_E0 + RN0;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
temp = ((signed64)State.regs[srcreg2]
* (signed64)State.regs[srcreg1]);
int c, v;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg1 = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg1 = REG_D0 + RM2 - 12;
- else
- srcreg1 = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg2 = REG_D0 + RN0 - 12;
- else
- srcreg2 = REG_E0 + RN0;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
temp = ((unsigned64)State.regs[srcreg2]
* (unsigned64)State.regs[srcreg1]);
int v;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg1 = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg1 = REG_D0 + RM2 - 12;
- else
- srcreg1 = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg2 = REG_D0 + RN0 - 12;
- else
- srcreg2 = REG_E0 + RN0;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
temp = ((signed32)(State.regs[srcreg2] & 0xff)
* (signed32)(State.regs[srcreg1] & 0xff));
int v;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg1 = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg1 = REG_D0 + RM2 - 12;
- else
- srcreg1 = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg2 = REG_D0 + RN0 - 12;
- else
- srcreg2 = REG_E0 + RN0;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
temp = ((unsigned32)(State.regs[srcreg2] & 0xff)
* (unsigned32)(State.regs[srcreg1] & 0xff));
int c, v;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg1 = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg1 = REG_D0 + RM2 - 12;
- else
- srcreg1 = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg2 = REG_D0 + RN0 - 12;
- else
- srcreg2 = REG_E0 + RN0;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
* (unsigned64)(State.regs[srcreg1] & 0xffff));
int c, v;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg1 = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg1 = REG_D0 + RM2 - 12;
- else
- srcreg1 = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg2 = REG_D0 + RN0 - 12;
- else
- srcreg2 = REG_E0 + RN0;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
temp = ((unsigned64)(State.regs[srcreg2] & 0xffff)
* (unsigned64)(State.regs[srcreg1] & 0xffff));
int v;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg1 = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg1 = REG_D0 + RM2 - 12;
- else
- srcreg1 = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg2 = REG_D0 + RN0 - 12;
- else
- srcreg2 = REG_E0 + RN0;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
temp = ((signed32)(State.regs[srcreg2] & 0xffff)
* (signed32)(State.regs[srcreg1] & 0xffff));
int v;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg1 = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg1 = REG_D0 + RM2 - 12;
- else
- srcreg1 = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg2 = REG_D0 + RN0 - 12;
- else
- srcreg2 = REG_E0 + RN0;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
temp = ((unsigned32)(State.regs[srcreg2] & 0xffff)
* (unsigned32)(State.regs[srcreg1] & 0xffff));
long temp;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
temp = ((signed32)(State.regs[dstreg] & 0xffff)
* (signed32)(State.regs[srcreg] & 0xffff));
unsigned long temp;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
temp = ((unsigned32)(State.regs[dstreg] & 0xffff)
* (unsigned32)(State.regs[srcreg] & 0xffff));
int value;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
value = State.regs[srcreg];
{
int srcreg, dstreg;
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 24)
| (((State.regs[srcreg] >> 8) & 0xff) << 16)
{
int srcreg, dstreg;
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = (((State.regs[srcreg] & 0xff) << 8)
| ((State.regs[srcreg] >> 8) & 0xff)
{
int srcreg, dstreg;
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = (((State.regs[srcreg] & 0xffff) << 16)
| ((State.regs[srcreg] >> 16) & 0xffff));
int start;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
temp = State.regs[srcreg];
start = (State.regs[dstreg] & 0x1f) - 1;
int dstreg;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = EXTEND8 (IMM8);
}
int dstreg;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = IMM8 & 0xff;
}
int dstreg;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ dstreg = translate_rreg (SD_, RN0);
genericAdd (EXTEND8 (IMM8), dstreg);
}
unsigned long reg1, reg2, sum;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
imm = EXTEND8 (IMM8);
reg2 = State.regs[dstreg];
int dstreg;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
genericSub (EXTEND8 (IMM8), dstreg);
}
unsigned long reg1, reg2, difference;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
imm = EXTEND8 (IMM8);
reg2 = State.regs[dstreg];
int srcreg;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg = REG_D0 + RN0 - 12;
- else
- srcreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RN0);
genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
}
int z, n;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] &= (IMM8 & 0xff);
z = (State.regs[dstreg] == 0);
int z, n;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] |= (IMM8 & 0xff);
z = (State.regs[dstreg] == 0);
int z, n;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] ^= (IMM8 & 0xff);
z = (State.regs[dstreg] == 0);
int c, z, n;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
temp = State.regs[dstreg];
c = temp & 1;
int z, n, c;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
c = State.regs[dstreg] & 1;
State.regs[dstreg] >>= (IMM8 & 0xff);
int z, n;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] <<= (IMM8 & 0xff);
z = (State.regs[dstreg] == 0);
int z, n;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
temp = ((signed64)(signed32)State.regs[dstreg]
* (signed64)(signed32)EXTEND8 (IMM8));
int z, n;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
temp = ((unsigned64)State.regs[dstreg]
* (unsigned64)(IMM8 & 0xff));
int srcreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
+ srcreg = translate_rreg (SD_, RM0);
genericBtst(IMM8, State.regs[srcreg]);
-
}
int srcreg, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
}
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
}
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
}
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
State.regs[srcreg] += 4;
}
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
State.regs[dstreg] += 4;
}
int dstreg;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
}
int srcreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
+ srcreg = translate_rreg (SD_, RM2);
store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
}
int dstreg;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
}
int srcreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
+ srcreg = translate_rreg (SD_, RM2);
store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
}
int dstreg;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
}
int srcreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
+ srcreg = translate_rreg (SD_, RM2);
store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
State.regs[srcreg] += 2;
}
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
State.regs[dstreg] += 2;
}
8.0xfb+8.0x0b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mac
"mac"
{
- int srcreg1, srcreg2;
+ int srcreg;
long long temp, sum;
int c, v;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- srcreg1 = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- srcreg1 = REG_D0 + RN2 - 12;
- else
- srcreg1 = REG_E0 + RN2;
+ srcreg = translate_rreg (SD_, RN2);
temp = ((signed64)EXTEND8 (IMM8)
- * (signed64)State.regs[srcreg1]);
+ * (signed64)State.regs[srcreg]);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
8.0xfb+8.0x1b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macu
"macu"
{
- int srcreg1, srcreg2;
+ int srcreg;
long long temp, sum;
int c, v;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- srcreg1 = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- srcreg1 = REG_D0 + RN2 - 12;
- else
- srcreg1 = REG_E0 + RN2;
+ srcreg = translate_rreg (SD_, RN2);
temp = ((unsigned64) (IMM8)
- * (unsigned64)State.regs[srcreg1]);
+ * (unsigned64)State.regs[srcreg]);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
8.0xfb+8.0x2b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macb
"macb"
{
- int srcreg1, srcreg2;
+ int srcreg;
long long temp, sum;
int c, v;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- srcreg1 = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- srcreg1 = REG_D0 + RN2 - 12;
- else
- srcreg1 = REG_E0 + RN2;
+ srcreg = translate_rreg (SD_, RN2);
temp = ((signed64)EXTEND8 (IMM8)
- * (signed64)State.regs[srcreg1] & 0xff);
+ * (signed64)State.regs[srcreg] & 0xff);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
8.0xfb+8.0x3b+4.RN2,4.RN0=RN2+8.IMM8:D2:::macbu
"macbu"
{
- int srcreg1, srcreg2;
+ int srcreg;
long long temp, sum;
int c, v;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- srcreg1 = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- srcreg1 = REG_D0 + RN2 - 12;
- else
- srcreg1 = REG_E0 + RN2;
+ srcreg = translate_rreg (SD_, RN2);
temp = ((unsigned64) (IMM8)
- * (unsigned64)State.regs[srcreg1] & 0xff);
+ * (unsigned64)State.regs[srcreg] & 0xff);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
8.0xfb+8.0x4b+4.RN2,4.RN0=RN2+8.IMM8:D2:::mach
"mach"
{
- int srcreg1, srcreg2;
+ int srcreg;
long long temp, sum;
int c, v;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- srcreg1 = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- srcreg1 = REG_D0 + RN2 - 12;
- else
- srcreg1 = REG_E0 + RN2;
+ srcreg = translate_rreg (SD_, RN2);
temp = ((signed64)EXTEND8 (IMM8)
- * (signed64)State.regs[srcreg1] & 0xffff);
+ * (signed64)State.regs[srcreg] & 0xffff);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
8.0xfb+8.0x5b+4.RN2,4.RN0=RN2+8.IMM8:D2:::machu
"machu"
{
- int srcreg1, srcreg2;
+ int srcreg;
long long temp, sum;
int c, v;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- srcreg1 = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- srcreg1 = REG_D0 + RN2 - 12;
- else
- srcreg1 = REG_E0 + RN2;
+ srcreg = translate_rreg (SD_, RN2);
temp = ((unsigned64) (IMM8)
- * (unsigned64)State.regs[srcreg1] & 0xffff);
+ * (unsigned64)State.regs[srcreg] & 0xffff);
sum = State.regs[REG_MCRL] + (temp & 0xffffffff);
c = (sum < State.regs[REG_MCRL]) || (sum < (temp & 0xffffffff));
State.regs[REG_MCRL] = sum;
int srcreg1, srcreg2, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg1 = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg1 = REG_D0 + RM2 - 12;
- else
- srcreg1 = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg2 = REG_D0 + RN0 - 12;
- else
- srcreg2 = REG_E0 + RN0;
-
- if (RD0 > 7 && RD0 < 12)
- dstreg = REG_A0 + RD0 - 8;
- else if (RD0 > 11 && RD0 < 16)
- dstreg = REG_D0 + RD0 - 12;
- else
- dstreg = REG_E0 + RD0;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
source1 = State.regs[srcreg1];
source2 = State.regs[srcreg2];
int srcreg1, srcreg2, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg1 = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg1 = REG_D0 + RM2 - 12;
- else
- srcreg1 = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg2 = REG_D0 + RN0 - 12;
- else
- srcreg2 = REG_E0 + RN0;
-
- if (RD0 > 7 && RD0 < 12)
- dstreg = REG_A0 + RD0 - 8;
- else if (RD0 > 11 && RD0 < 16)
- dstreg = REG_D0 + RD0 - 12;
- else
- dstreg = REG_E0 + RD0;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
source1 = State.regs[srcreg1];
source2 = State.regs[srcreg2];
int srcreg1, srcreg2, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg1 = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg1 = REG_D0 + RM2 - 12;
- else
- srcreg1 = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg2 = REG_D0 + RN0 - 12;
- else
- srcreg2 = REG_E0 + RN0;
-
- if (RD0 > 7 && RD0 < 12)
- dstreg = REG_A0 + RD0 - 8;
- else if (RD0 > 11 && RD0 < 16)
- dstreg = REG_D0 + RD0 - 12;
- else
- dstreg = REG_E0 + RD0;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
source1 = State.regs[srcreg1];
source2 = State.regs[srcreg2];
int srcreg1, srcreg2, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg1 = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg1 = REG_D0 + RM2 - 12;
- else
- srcreg1 = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg2 = REG_D0 + RN0 - 12;
- else
- srcreg2 = REG_E0 + RN0;
-
- if (RD0 > 7 && RD0 < 12)
- dstreg = REG_A0 + RD0 - 8;
- else if (RD0 > 11 && RD0 < 16)
- dstreg = REG_D0 + RD0 - 12;
- else
- dstreg = REG_E0 + RD0;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
source1 = State.regs[srcreg1];
source2 = State.regs[srcreg2];
int srcreg1, srcreg2, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg1 = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg1 = REG_D0 + RM2 - 12;
- else
- srcreg1 = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg2 = REG_D0 + RN0 - 12;
- else
- srcreg2 = REG_E0 + RN0;
-
- if (RD0 > 7 && RD0 < 12)
- dstreg = REG_A0 + RD0 - 8;
- else if (RD0 > 11 && RD0 < 16)
- dstreg = REG_D0 + RD0 - 12;
- else
- dstreg = REG_E0 + RD0;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
int srcreg1, srcreg2, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg1 = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg1 = REG_D0 + RM2 - 12;
- else
- srcreg1 = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg2 = REG_D0 + RN0 - 12;
- else
- srcreg2 = REG_E0 + RN0;
-
- if (RD0 > 7 && RD0 < 12)
- dstreg = REG_A0 + RD0 - 8;
- else if (RD0 > 11 && RD0 < 16)
- dstreg = REG_D0 + RD0 - 12;
- else
- dstreg = REG_E0 + RD0;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
int srcreg1, srcreg2, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg1 = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg1 = REG_D0 + RM2 - 12;
- else
- srcreg1 = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg2 = REG_D0 + RN0 - 12;
- else
- srcreg2 = REG_E0 + RN0;
-
- if (RD0 > 7 && RD0 < 12)
- dstreg = REG_A0 + RD0 - 8;
- else if (RD0 > 11 && RD0 < 16)
- dstreg = REG_D0 + RD0 - 12;
- else
- dstreg = REG_E0 + RD0;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
int srcreg1, srcreg2, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg1 = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg1 = REG_D0 + RM2 - 12;
- else
- srcreg1 = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg2 = REG_D0 + RN0 - 12;
- else
- srcreg2 = REG_E0 + RN0;
-
- if (RD0 > 7 && RD0 < 12)
- dstreg = REG_A0 + RD0 - 8;
- else if (RD0 > 11 && RD0 < 16)
- dstreg = REG_D0 + RD0 - 12;
- else
- dstreg = REG_E0 + RD0;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
temp = State.regs[srcreg2];
c = temp & 1;
int srcreg1, srcreg2, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg1 = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg1 = REG_D0 + RM2 - 12;
- else
- srcreg1 = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg2 = REG_D0 + RN0 - 12;
- else
- srcreg2 = REG_E0 + RN0;
-
- if (RD0 > 7 && RD0 < 12)
- dstreg = REG_A0 + RD0 - 8;
- else if (RD0 > 11 && RD0 < 16)
- dstreg = REG_D0 + RD0 - 12;
- else
- dstreg = REG_E0 + RD0;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
c = State.regs[srcreg2] & 1;
State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
int srcreg1, srcreg2, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg1 = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg1 = REG_D0 + RM2 - 12;
- else
- srcreg1 = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg2 = REG_D0 + RN0 - 12;
- else
- srcreg2 = REG_E0 + RN0;
-
- if (RD0 > 7 && RD0 < 12)
- dstreg = REG_A0 + RD0 - 8;
- else if (RD0 > 11 && RD0 < 16)
- dstreg = REG_D0 + RD0 - 12;
- else
- dstreg = REG_E0 + RD0;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg = translate_rreg (SD_, RD0);
State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];;
signed long long temp;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg1 = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg1 = REG_D0 + RM2 - 12;
- else
- srcreg1 = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg2 = REG_D0 + RN0 - 12;
- else
- srcreg2 = REG_E0 + RN0;
-
- if (RD0 > 7 && RD0 < 12)
- dstreg1 = REG_A0 + RD0 - 8;
- else if (RD0 > 11 && RD0 < 16)
- dstreg1 = REG_D0 + RD0 - 12;
- else
- dstreg1 = REG_E0 + RD0;
-
- if (RD2 > 7 && RD2 < 12)
- dstreg2 = REG_A0 + RD2 - 8;
- else if (RD2 > 11 && RD2 < 16)
- dstreg2 = REG_D0 + RD2 - 12;
- else
- dstreg2 = REG_E0 + RD2;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg1 = translate_rreg (SD_, RD0);
+ dstreg2 = translate_rreg (SD_, RD2);
temp = ((signed64)(signed32)State.regs[srcreg1]
* (signed64)(signed32)State.regs[srcreg2]);
signed long long temp;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg1 = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg1 = REG_D0 + RM2 - 12;
- else
- srcreg1 = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg2 = REG_D0 + RN0 - 12;
- else
- srcreg2 = REG_E0 + RN0;
-
- if (RD0 > 7 && RD0 < 12)
- dstreg1 = REG_A0 + RD0 - 8;
- else if (RD0 > 11 && RD0 < 16)
- dstreg1 = REG_D0 + RD0 - 12;
- else
- dstreg1 = REG_E0 + RD0;
-
- if (RD2 > 7 && RD2 < 12)
- dstreg2 = REG_A0 + RD2 - 8;
- else if (RD2 > 11 && RD2 < 16)
- dstreg2 = REG_D0 + RD2 - 12;
- else
- dstreg2 = REG_E0 + RD2;
+ srcreg1 = translate_rreg (SD_, RM2);
+ srcreg2 = translate_rreg (SD_, RN0);
+ dstreg1 = translate_rreg (SD_, RD0);
+ dstreg2 = translate_rreg (SD_, RD2);
temp = ((unsigned64)(unsigned32)State.regs[srcreg1]
* (unsigned64)(unsigned32)State.regs[srcreg2]);
int dstreg;
PC = cia;
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_word (IMM8);
}
{
int srcreg;
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
+ PC = cia;
+ srcreg = translate_rreg (SD_, RM2);
store_word (IMM8, State.regs[srcreg]);
}
int dstreg;
PC = cia;
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_byte (IMM8);
}
int srcreg;
PC = cia;
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
+ srcreg = translate_rreg (SD_, RM2);
store_byte (IMM8, State.regs[srcreg]);
}
int dstreg;
PC = cia;
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_half (IMM8);
}
int srcreg;
PC = cia;
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
+ srcreg = translate_rreg (SD_, RM2);
store_half (IMM8, State.regs[srcreg]);
}
int srcreg1, srcreg2, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg1 = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg1 = REG_D0 + RM0 - 12;
- else
- srcreg1 = REG_E0 + RM0;
-
- if (RI0 > 7 && RI0 < 12)
- srcreg2 = REG_A0 + RI0 - 8;
- else if (RI0 > 11 && RI0 < 16)
- srcreg2 = REG_D0 + RI0 - 12;
- else
- srcreg2 = REG_E0 + RI0;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg1 = translate_rreg (SD_, RM0);
+ srcreg1 = translate_rreg (SD_, RI0);
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = load_word (State.regs[srcreg1] + State.regs[srcreg2]);
}
int srcreg, dstreg1, dstreg2;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RI0 > 7 && RI0 < 12)
- dstreg1 = REG_A0 + RI0 - 8;
- else if (RI0 > 11 && RI0 < 16)
- dstreg1 = REG_D0 + RI0 - 12;
- else
- dstreg1 = REG_E0 + RI0;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg2 = REG_D0 + RN0 - 12;
- else
- dstreg2 = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg1 = translate_rreg (SD_, RI0);
+ dstreg2 = translate_rreg (SD_, RN0);
store_word (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
}
int srcreg1, srcreg2, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg1 = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg1 = REG_D0 + RM0 - 12;
- else
- srcreg1 = REG_E0 + RM0;
-
- if (RI0 > 7 && RI0 < 12)
- srcreg2 = REG_A0 + RI0 - 8;
- else if (RI0 > 11 && RI0 < 16)
- srcreg2 = REG_D0 + RI0 - 12;
- else
- srcreg2 = REG_E0 + RI0;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg1 = translate_rreg (SD_, RM0);
+ srcreg1 = translate_rreg (SD_, RI0);
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = load_byte (State.regs[srcreg1] + State.regs[srcreg2]);
}
int srcreg, dstreg1, dstreg2;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RI0 > 7 && RI0 < 12)
- dstreg1 = REG_A0 + RI0 - 8;
- else if (RI0 > 11 && RI0 < 16)
- dstreg1 = REG_D0 + RI0 - 12;
- else
- dstreg1 = REG_E0 + RI0;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg2 = REG_D0 + RN0 - 12;
- else
- dstreg2 = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg1 = translate_rreg (SD_, RI0);
+ dstreg2 = translate_rreg (SD_, RN0);
store_byte (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
}
{
int srcreg1, srcreg2, dstreg;
- PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg1 = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg1 = REG_D0 + RM0 - 12;
- else
- srcreg1 = REG_E0 + RM0;
-
- if (RI0 > 7 && RI0 < 12)
- srcreg2 = REG_A0 + RI0 - 8;
- else if (RI0 > 11 && RI0 < 16)
- srcreg2 = REG_D0 + RI0 - 12;
- else
- srcreg2 = REG_E0 + RI0;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ PC = cia;
+ srcreg1 = translate_rreg (SD_, RM0);
+ srcreg1 = translate_rreg (SD_, RI0);
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = load_half (State.regs[srcreg1] + State.regs[srcreg2]);
}
int srcreg, dstreg1, dstreg2;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RI0 > 7 && RI0 < 12)
- dstreg1 = REG_A0 + RI0 - 8;
- else if (RI0 > 11 && RI0 < 16)
- dstreg1 = REG_D0 + RI0 - 12;
- else
- dstreg1 = REG_E0 + RI0;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg2 = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg2 = REG_D0 + RN0 - 12;
- else
- dstreg2 = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg1 = translate_rreg (SD_, RI0);
+ dstreg2 = translate_rreg (SD_, RN0);
store_half (State.regs[dstreg1] + State.regs[dstreg2], State.regs[srcreg]);
}
int value;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
value = State.regs[srcreg];
int dstreg;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
}
int dstreg;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
}
int dstreg;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ dstreg = translate_rreg (SD_, RN0);
genericAdd (FETCH24 (IMM24A, IMM24B, IMM24C), dstreg);
}
unsigned long sum, imm, reg2;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
reg2 = State.regs[dstreg];
int dstreg;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ dstreg = translate_rreg (SD_, RN0);
genericSub (FETCH24 (IMM24A, IMM24B, IMM24C), dstreg);
}
unsigned long difference, imm, reg2;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
reg2 = State.regs[dstreg];
int srcreg;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg = REG_D0 + RN0 - 12;
- else
- srcreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RN0);
genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
}
"mov"
*am33
{
- int dstreg;
-
PC = cia;
if (XRN0 == 0)
int z,n;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
z = (State.regs[dstreg] == 0);
int z,n;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
z = (State.regs[dstreg] == 0);
int z,n;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
z = (State.regs[dstreg] == 0);
int c, z, n;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
temp = State.regs[dstreg];
c = temp & 1;
int z, n, c;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
c = State.regs[dstreg] & 1;
State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
int z, n;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
z = (State.regs[dstreg] == 0);
int srcreg;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg = REG_D0 + RN0 - 12;
- else
- srcreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RN0);
genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_word (State.regs[srcreg]
+ FETCH24 (IMM24A, IMM24B, IMM24C));
}
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
store_word (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_byte (State.regs[srcreg]
+ FETCH24 (IMM24A, IMM24B, IMM24C));
}
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
store_byte (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_half (State.regs[srcreg]
+ FETCH24 (IMM24A, IMM24B, IMM24C));
}
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
store_half (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_word (State.regs[srcreg]
+ FETCH24 (IMM24A, IMM24B, IMM24C));
State.regs[srcreg] += 4;
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
store_word (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
State.regs[srcreg]);
State.regs[dstreg] += 4;
int dstreg;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_word (State.regs[REG_SP]
+ FETCH24 (IMM24A, IMM24B, IMM24C));
}
int srcreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
+ srcreg = translate_rreg (SD_, RM2);
store_word (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
State.regs[srcreg]);
}
int dstreg;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_byte (State.regs[REG_SP]
+ FETCH24 (IMM24A, IMM24B, IMM24C));
}
int srcreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
+ srcreg = translate_rreg (SD_, RM2);
store_byte (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
State.regs[srcreg]);
}
int dstreg;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_half (State.regs[REG_SP]
+ FETCH24 (IMM24A, IMM24B, IMM24C));
}
int srcreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
+ srcreg = translate_rreg (SD_, RM2);
store_half (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_half (State.regs[srcreg]
+ FETCH24 (IMM24A, IMM24B, IMM24C));
State.regs[dstreg] += 2;
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
store_half (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
State.regs[srcreg]);
State.regs[srcreg] += 2;
int dstreg;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
}
int srcreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
+ srcreg = translate_rreg (SD_, RM2);
store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
}
int dstreg;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
}
int srcreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
+ srcreg = translate_rreg (SD_, RM2);
store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
}
int dstreg;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
}
int srcreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
+ srcreg = translate_rreg (SD_, RM2);
store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
}
int dstreg;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
}
int dstreg;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
}
int dstreg;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ dstreg = translate_rreg (SD_, RN0);
genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
}
int z, n, c, v;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
reg2 = State.regs[dstreg];
int dstreg;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ dstreg = translate_rreg (SD_, RN0);
genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
}
int z, n, c, v;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
reg2 = State.regs[dstreg];
int srcreg;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg = REG_D0 + RN0 - 12;
- else
- srcreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RN0);
genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
}
"mov"
*am33
{
- int dstreg;
-
PC = cia;
if (XRN0 == 0)
int z,n;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
z = (State.regs[dstreg] == 0);
int z,n;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
z = (State.regs[dstreg] == 0);
int z,n;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
z = (State.regs[dstreg] == 0);
int c, z, n;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
temp = State.regs[dstreg];
c = temp & 1;
int z, n, c;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
c = State.regs[dstreg] & 1;
State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
int z, n;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
+ dstreg = translate_rreg (SD_, RN0);
State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
z = (State.regs[dstreg] == 0);
int srcreg;
PC = cia;
-
- if (RN0 > 7 && RN0 < 12)
- srcreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- srcreg = REG_D0 + RN0 - 12;
- else
- srcreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RN0);
genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_word (State.regs[srcreg]
+ FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
}
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_byte (State.regs[srcreg]
+ FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
}
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_half (State.regs[srcreg]
+ FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
}
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_word (State.regs[srcreg]
+ FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
State.regs[srcreg] += 4;
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
State.regs[srcreg]);
State.regs[dstreg] += 4;
int dstreg;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_word (State.regs[REG_SP]
+ FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
}
int srcreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
+ srcreg = translate_rreg (SD_, RM2);
store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
State.regs[srcreg]);
}
int dstreg;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_byte (State.regs[REG_SP]
+ FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
}
int srcreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
+ srcreg = translate_rreg (SD_, RM2);
store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
State.regs[srcreg]);
}
int dstreg;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_half (State.regs[REG_SP]
+ FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
}
int srcreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
+ srcreg = translate_rreg (SD_, RM2);
store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
State.regs[srcreg]);
}
int srcreg, dstreg;
PC = cia;
-
- if (RM0 > 7 && RM0 < 12)
- srcreg = REG_A0 + RM0 - 8;
- else if (RM0 > 11 && RM0 < 16)
- srcreg = REG_D0 + RM0 - 12;
- else
- srcreg = REG_E0 + RM0;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ srcreg = translate_rreg (SD_, RM0);
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_half (State.regs[srcreg]
+ FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
State.regs[srcreg] += 2;
int srcreg, dstreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
- if (RN0 > 7 && RN0 < 12)
- dstreg = REG_A0 + RN0 - 8;
- else if (RN0 > 11 && RN0 < 16)
- dstreg = REG_D0 + RN0 - 12;
- else
- dstreg = REG_E0 + RN0;
-
+ srcreg = translate_rreg (SD_, RM2);
+ dstreg = translate_rreg (SD_, RN0);
store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
State.regs[srcreg]);
State.regs[dstreg] += 2;
int dstreg;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
}
int srcreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
+ srcreg = translate_rreg (SD_, RM2);
store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
}
int dstreg;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
}
int srcreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
+ srcreg = translate_rreg (SD_, RM2);
store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
}
int dstreg;
PC = cia;
-
- if (RN2 > 7 && RN2 < 12)
- dstreg = REG_A0 + RN2 - 8;
- else if (RN2 > 11 && RN2 < 16)
- dstreg = REG_D0 + RN2 - 12;
- else
- dstreg = REG_E0 + RN2;
-
+ dstreg = translate_rreg (SD_, RN2);
State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
}
int srcreg;
PC = cia;
-
- if (RM2 > 7 && RM2 < 12)
- srcreg = REG_A0 + RM2 - 8;
- else if (RM2 > 11 && RM2 < 16)
- srcreg = REG_D0 + RM2 - 12;
- else
- srcreg = REG_E0 + RM2;
-
+ srcreg = translate_rreg (SD_, RM2);
store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
}
-// DSP
+// ??? DSP
projects / binutils-gdb.git / commitdiff