i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE

Emulate MMX ssse3_pmulhrswv4hi3 with SSE.  Only SSE register source
operand is allowed.

	PR target/89021
	* config/i386/sse.md (ssse3_pmulhrswv4hi3): Require TARGET_MMX
	or TARGET_MMX_WITH_SSE.
	(*ssse3_pmulhrswv4hi3): Add SSE emulation.

From-SVN: r271244

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9cad0f4c8b2aae10ba0634eb14c3e645e0da8d87..3347edaa25dfa3274ae02365d681c496dd794377 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2019-05-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR target/89021
+       * config/i386/sse.md (ssse3_pmulhrswv4hi3): Require TARGET_MMX
+       or TARGET_MMX_WITH_SSE.
+       (*ssse3_pmulhrswv4hi3): Add SSE emulation.
+
 2019-05-15  H.J. Lu  <hongjiu.lu@intel.com>
 
        PR target/89021

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index bd3bbbe94a4f1c5e549e521067ef681716f5c304..3e188cea36805a751c3dc441a749fee4776eeb26 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -16117,38 +16117,44 @@
              (lshiftrt:V4SI
                (mult:V4SI
                  (sign_extend:V4SI
-                   (match_operand:V4HI 1 "nonimmediate_operand"))
+                   (match_operand:V4HI 1 "register_mmxmem_operand"))
                  (sign_extend:V4SI
-                   (match_operand:V4HI 2 "nonimmediate_operand")))
+                   (match_operand:V4HI 2 "register_mmxmem_operand")))
                (const_int 14))
              (match_dup 3))
            (const_int 1))))]
-  "TARGET_SSSE3"
+  "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
 {
   operands[3] = CONST1_RTX(V4HImode);
   ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);
 })
 
 (define_insn "*ssse3_pmulhrswv4hi3"
-  [(set (match_operand:V4HI 0 "register_operand" "=y")
+  [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv")
        (truncate:V4HI
          (lshiftrt:V4SI
            (plus:V4SI
              (lshiftrt:V4SI
                (mult:V4SI
                  (sign_extend:V4SI
-                   (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
+                   (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yv"))
                  (sign_extend:V4SI
-                   (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
+                   (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv")))
                (const_int 14))
              (match_operand:V4HI 3 "const1_operand"))
            (const_int 1))))]
-  "TARGET_SSSE3 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
-  "pmulhrsw\t{%2, %0|%0, %2}"
-  [(set_attr "type" "sseimul")
+  "(TARGET_MMX || TARGET_MMX_WITH_SSE)
+   && TARGET_SSSE3
+   && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
+  "@
+   pmulhrsw\t{%2, %0|%0, %2}
+   pmulhrsw\t{%2, %0|%0, %2}
+   vpmulhrsw\t{%2, %1, %0|%0, %1, %2}"
+  [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+   (set_attr "type" "sseimul")
    (set_attr "prefix_extra" "1")
    (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
-   (set_attr "mode" "DI")])
+   (set_attr "mode" "DI,TI,TI")])
 
 (define_insn "<ssse3_avx2>_pshufb<mode>3<mask_name>"
   [(set (match_operand:VI1_AVX512 0 "register_operand" "=x,x,v")