arch-riscv: respect IALIGN, influenced by toggling 'c' extension.

According to the privileged ISA spec, SEPC[0]/MEPC[0] reads always 0
and SEPC[1]/MEPC[1] reads 0 if the compressed extension is disabled.

Additionally, the compressed extension can only be disabled if the next
instruction is 4-byte aligned.

Change-Id: I590c05e4000b59a5ba283f47933f7a92959d8e38
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25658
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index a2fbd804373151d2db16d1847baa4967d7c5b3a6..b6137fe9f5bf45d4eb7ce0009f7e19c82e10b1d3 100644 (file)
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -283,6 +283,18 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
                     tc->getCpuPtr()->getInterruptController(tc->threadId()));
             return ic->readIE();
         }
+      case MISCREG_SEPC:
+      case MISCREG_MEPC:
+        {
+            auto misa = readMiscRegNoEffect(MISCREG_ISA);
+            auto val = readMiscRegNoEffect(misc_reg);
+            // if compressed instructions are disabled, epc[1] is set to 0
+            if ((misa & ISA_EXT_C_MASK) == 0)
+                return mbits(val, 63, 2);
+            // epc[0] is always 0
+            else
+                return mbits(val, 63, 1);
+        }
       default:
         // Try reading HPM counters
         // As a placeholder, all HPM counters are just cycle counters
@@ -347,6 +359,17 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
                 setMiscRegNoEffect(misc_reg, new_val);
             }
             break;
+          case MISCREG_ISA:
+            {
+                auto cur_val = readMiscRegNoEffect(misc_reg);
+                // only allow to disable compressed instructions
+                // if the following instruction is 4-byte aligned
+                if ((val & ISA_EXT_C_MASK) == 0 &&
+                    bits(tc->pcState().npc(), 2, 0) != 0)
+                    val |= cur_val & ISA_EXT_C_MASK;
+                setMiscRegNoEffect(misc_reg, val);
+            }
+            break;
           case MISCREG_STATUS:
             {
                 // SXL and UXL are hard-wired to 64 bit

diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index d5c05a2e4697b5fa71f1abc60224b8879ed80db7..9b899e343793f56f7878bc9fc616372be588bc6e 100644 (file)
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -2,6 +2,7 @@
  * Copyright (c) 2013 ARM Limited
  * Copyright (c) 2014-2015 Sven Karlsson
  * Copyright (c) 2019 Yifei Liu
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -646,6 +647,7 @@ const off_t FRM_OFFSET = 5;
 
 const RegVal ISA_MXL_MASK = 3ULL << MXL_OFFSET;
 const RegVal ISA_EXT_MASK = mask(26);
+const RegVal ISA_EXT_C_MASK = 1UL << ('c' - 'a');
 const RegVal MISA_MASK = ISA_MXL_MASK | ISA_EXT_MASK;
 
 const RegVal STATUS_SD_MASK = 1ULL << ((sizeof(uint64_t) * 8) - 1);