(no commit message)

diff --git a/simple_v_extension/vector_ops.mdwn b/simple_v_extension/vector_ops.mdwn
index 11235f24e5fca2d54ba7e2d4678603969226b9ab..edcd88ce74d1d3d18f19402c682ed9f202af8ccf 100644 (file)
--- a/simple_v_extension/vector_ops.mdwn
+++ b/simple_v_extension/vector_ops.mdwn
@@ -99,3 +99,7 @@ Pseudocode:
 
         return (s0 * v0) + (s1 * v1);
     }
+
+# Expensive 3-operand OP32 operations
+
+3-operand operations are extremely expensive in terms of OP32 encoding space.  A potential idea is to embed 3 RVC register formats across two out of three 5-bit fields rs1/rs2/rd