* testsuite/gas/tic4x/tic4x.exp: Create
* testsuite/gas/tic4x/zeros.d: Create
* testsuite/gas/tic4x/zeros.s: Create
-
+ * config/tc-tic4x.c: Fixed proper commandline
+ parameters. Added support for new opcode-list format. General
+ error message fixups.
+ (c4x_inst_add): Reject insn not for our CPU
+ (md_begin): Added matrix for setting the proper opcode-level &
+ device-flags according to cpu type and revision. Rewrite the
+ opcode hasher.
+ (c4x_operand_parse): Fix opcode bug
+ (c4x_operands_match): New function argument. Added dry-run
+ mechanism, that is optional error generation. Added constraint 'i'
+ and 'j'.
+ (c4x_insn_check): Added new function for post-verification of the
+ generated insn.
+ (md_assemble): Check all opcodes before croaking because of an
+ argument mismatch. Need this to be able to fully support
+ ortogonally arguments.
+ (md_parse_options): Revised commandprompt swicthes and added new
+ ones.
+ (md_show_usage): Complete rewrite of printout.
+ * testsuite/gas/tic4x/addressing.s: Fix bug in one insn
+ * testsuite/gas/tic4x/addressing_c3x.d: Update thereafter
+ * testsuite/gas/tic4x/addressing_c4x.d: Update thereafter
+ * testsuite/gas/tic4x/allopcodes.S: Add support for new
+ opclass.h changes
+ * testsuite/gas/tic4x/opclasses.h: Added testsuites for
+ the new enhanced opcodes.
+ * testsuite/gas/tic4x/opcodes.s: Regenerate
+ * testsuite/gas/tic4x/opcodes_c3x.d: Update from above
+ * testsuite/gas/tic4x/opcodes_c4x.d: Update from above
+ * testsuite/gas/tic4x/opcodes_new.d: Added new testsuite for
+ the enhanced and special insns.
+ * testsuite/gas/tic4x/tic4x.exp: Added the opcodes_new testsuite
+
2002-11-16 Svein E. Seldal <Svein.Seldal@solidas.com>
* config/tc-tic4x.c: Remove c4x_pseudo_ignore function.
o Evaluation of constant floating point expressions (expr.c needs
work!)
- o Warnings issued if parallel load of same register. Applies to LL
- class. Can be applied to destination of the LS class as well, but
- the test will be more complex.
-
- o Support 'abc' constants?
-
- o Support new opcodes and implement a silicon version switch (maybe
- -mpg)
-
- o Disallow non-float registers in float instructions.
-
- o Make sure the source and destination register is NOT equal when
- the C4X LDA insn is used (arg mode Q,Y)
-
- o Merge the C3x op-table and the c4x op-table, and adhere to the
- last argument when parsing the hash.
+ o Support 'abc' constants (that is 0x616263)
*/
#include <stdio.h>
static struct hash_control *c4x_asg_hash = NULL;
static unsigned int c4x_cpu = 0; /* Default to TMS320C40. */
+static unsigned int c4x_revision = 0; /* CPU revision */
+static unsigned int c4x_idle2 = 0; /* Idle2 support */
+static unsigned int c4x_lowpower = 0; /* Lowpower support */
+static unsigned int c4x_enhanced = 0; /* Enhanced opcode support */
static unsigned int c4x_big_model = 0; /* Default to small memory model. */
static unsigned int c4x_reg_args = 0; /* Default to args passed on stack. */
+static unsigned long c4x_oplevel = 0; /* Opcode level */
+
+#define OPTION_CPU 'm'
+#define OPTION_BIG (OPTION_MD_BASE + 1)
+#define OPTION_SMALL (OPTION_MD_BASE + 2)
+#define OPTION_MEMPARM (OPTION_MD_BASE + 3)
+#define OPTION_REGPARM (OPTION_MD_BASE + 4)
+#define OPTION_IDLE2 (OPTION_MD_BASE + 5)
+#define OPTION_LOWPOWER (OPTION_MD_BASE + 6)
+#define OPTION_ENHANCED (OPTION_MD_BASE + 7)
+#define OPTION_REV (OPTION_MD_BASE + 8)
+
+CONST char *md_shortopts = "bm:prs";
+struct option md_longopts[] =
+{
+ { "mcpu", required_argument, NULL, OPTION_CPU },
+ { "mdsp", required_argument, NULL, OPTION_CPU },
+ { "mbig", no_argument, NULL, OPTION_BIG },
+ { "msmall", no_argument, NULL, OPTION_SMALL },
+ { "mmemparm", no_argument, NULL, OPTION_MEMPARM },
+ { "mregparm", no_argument, NULL, OPTION_REGPARM },
+ { "midle2", no_argument, NULL, OPTION_IDLE2 },
+ { "mlowpower", no_argument, NULL, OPTION_LOWPOWER },
+ { "menhanced", no_argument, NULL, OPTION_ENHANCED },
+ { "mrev", required_argument, NULL, OPTION_REV },
+ { NULL, no_argument, NULL, 0 }
+};
+
+size_t md_longopts_size = sizeof (md_longopts);
+
typedef enum
{
static char *c4x_operand_parse
PARAMS ((char *, c4x_operand_t *));
static int c4x_operands_match
- PARAMS ((c4x_inst_t *, c4x_insn_t *));
+ PARAMS ((c4x_inst_t *, c4x_insn_t *, int));
+static void c4x_insn_check
+ PARAMS ((c4x_insn_t *));
static void c4x_insn_output
PARAMS ((c4x_insn_t *));
static int c4x_operands_parse
input_line_pointer =
c4x_expression_abs (input_line_pointer, &temp);
if (!IS_CPU_C3X (temp) && !IS_CPU_C4X (temp))
- as_bad ("This assembler does not support processor generation %d\n",
+ as_bad ("This assembler does not support processor generation %d",
temp);
if (c4x_cpu && temp != c4x_cpu)
- as_warn ("Changing processor generation on fly not supported...\n");
+ as_warn ("Changing processor generation on fly not supported...");
c4x_cpu = temp;
demand_empty_rest_of_line ();
}
d = name;
+ /* We do not care about INSNs that is not a part of our
+ oplevel setting */
+ if (!insts->oplevel & c4x_oplevel)
+ return ok;
+
while (1)
{
switch (*s)
int ok = 1;
unsigned int i;
+ /* Setup the proper opcode level according to the
+ commandline parameters */
+ c4x_oplevel = OP_C3X;
+
+ if ( IS_CPU_C4X(c4x_cpu) )
+ c4x_oplevel |= OP_C4X;
+
+ if ( ( c4x_cpu == 31 && c4x_revision >= 6)
+ || (c4x_cpu == 32 && c4x_revision >= 2)
+ || (c4x_cpu == 33)
+ || c4x_enhanced )
+ c4x_oplevel |= OP_ENH;
+
+ if ( ( c4x_cpu == 30 && c4x_revision >= 7)
+ || (c4x_cpu == 31 && c4x_revision >= 5)
+ || (c4x_cpu == 32)
+ || c4x_lowpower )
+ c4x_oplevel |= OP_LPWR;
+
+ if ( ( c4x_cpu == 30 && c4x_revision >= 7)
+ || (c4x_cpu == 31 && c4x_revision >= 5)
+ || (c4x_cpu == 32)
+ || (c4x_cpu == 33)
+ || (c4x_cpu == 40 && c4x_revision >= 5)
+ || (c4x_cpu == 44)
+ || c4x_idle2 )
+ c4x_oplevel |= OP_IDLE2;
+
/* Create hash table for mnemonics. */
c4x_op_hash = hash_new ();
c4x_asg_hash = hash_new ();
/* Add mnemonics to hash table, expanding conditional mnemonics on fly. */
- for (i = 0; i < c3x_num_insts; i++)
- ok &= c4x_inst_add ((void *) &c3x_insts[i]);
-
- if (IS_CPU_C4X (c4x_cpu))
- {
- for (i = 0; i < c4x_num_insts; i++)
- ok &= c4x_inst_add ((void *) &c4x_insts[i]);
- }
+ for (i = 0; i < c4x_num_insts; i++)
+ ok &= c4x_inst_add ((void *) &c4x_insts[i]);
/* Create dummy inst to avoid errors accessing end of table. */
c4x_inst_make ("", 0, "");
case '*':
ret = -1;
- for (i = 0; i < num_indirects; i++)
+ for (i = 0; i < c4x_num_indirects; i++)
if ((ret = c4x_indirect_parse (operand, &c4x_indirects[i])))
break;
if (ret < 0)
break;
- if (i < num_indirects)
+ if (i < c4x_num_indirects)
{
operand->mode = M_INDIRECT;
/* Indirect addressing mode number. */
}
static int
-c4x_operands_match (inst, insn)
+c4x_operands_match (inst, insn, check)
c4x_inst_t *inst;
c4x_insn_t *insn;
+ int check;
{
const char *args = inst->args;
unsigned long opcode = inst->opcode;
}
else
{
- as_bad ("LDF's immediate value of %ld is too large",
- (long) exp->X_add_number);
+ if (!check)
+ as_bad ("Immediate value of %ld is too large for ldf",
+ (long) exp->X_add_number);
ret = -1;
continue;
}
}
else
{
- as_bad ("Direct value of %ld is too large",
- (long) exp->X_add_number);
+ if (!check)
+ as_bad ("Direct value of %ld is too large",
+ (long) exp->X_add_number);
ret = -1;
continue;
}
INSERTU (opcode, reg - REG_AR0, 24, 22);
else
{
- as_bad ("Destination register must be ARn");
+ if (!check)
+ as_bad ("Destination register must be ARn");
ret = -1;
}
continue;
}
else
{
- as_bad ("Immediate value of %ld is too large",
- (long) exp->X_add_number);
+ if (!check)
+ as_bad ("Immediate value of %ld is too large",
+ (long) exp->X_add_number);
ret = -1;
continue;
}
if (operand->expr.X_add_number != 0
&& operand->expr.X_add_number != 0x18)
{
- as_bad ("Invalid indirect addressing mode");
- ret = -1;
+ if (!check)
+ as_bad ("Invalid indirect addressing mode");
+ ret = -1;
continue;
}
INSERTU (opcode, operand->aregno - REG_AR0, 2, 0);
INSERTU (opcode, reg, 7, 0);
else
{
- as_bad ("Register must be Rn");
+ if (!check)
+ as_bad ("Register must be Rn");
ret = -1;
}
continue;
INSERTU (opcode, reg, 15, 8);
else
{
- as_bad ("Register must be Rn");
+ if (!check)
+ as_bad ("Register must be Rn");
ret = -1;
}
continue;
INSERTU (opcode, reg - REG_R0, 18, 16);
else
{
- as_bad ("Register must be R0--R7");
+ if (!check)
+ as_bad ("Register must be R0--R7");
ret = -1;
}
continue;
+ case 'i':
+ if ( operand->mode == M_REGISTER
+ && c4x_oplevel & OP_ENH )
+ {
+ reg = exp->X_add_number;
+ INSERTU (opcode, reg, 4, 0);
+ INSERTU (opcode, 7, 7, 5);
+ continue;
+ }
+ /* Fallthrough */
+
case 'I':
if (operand->mode != M_INDIRECT)
break;
{
if (IS_CPU_C4X (c4x_cpu))
break;
- as_bad ("Invalid indirect addressing mode displacement %d",
- operand->disp);
+ if (!check)
+ as_bad ("Invalid indirect addressing mode displacement %d",
+ operand->disp);
ret = -1;
continue;
}
INSERTU (opcode, operand->expr.X_add_number, 7, 3);
continue;
+ case 'j':
+ if ( operand->mode == M_REGISTER
+ && c4x_oplevel & OP_ENH )
+ {
+ reg = exp->X_add_number;
+ INSERTU (opcode, reg, 12, 8);
+ INSERTU (opcode, 7, 15, 13);
+ continue;
+ }
+ /* Fallthrough */
+
case 'J':
if (operand->mode != M_INDIRECT)
break;
{
if (IS_CPU_C4X (c4x_cpu))
break;
- as_bad ("Invalid indirect addressing mode displacement %d",
- operand->disp);
+ if (!check)
+ as_bad ("Invalid indirect addressing mode displacement %d",
+ operand->disp);
ret = -1;
continue;
}
INSERTU (opcode, reg - REG_R0, 21, 19);
else
{
- as_bad ("Register must be R0--R7");
+ if (!check)
+ as_bad ("Register must be R0--R7");
ret = -1;
}
continue;
INSERTU (opcode, reg - REG_R0, 24, 22);
else
{
- as_bad ("Register must be R0--R7");
+ if (!check)
+ as_bad ("Register must be R0--R7");
ret = -1;
}
continue;
INSERTU (opcode, reg - REG_R2, 22, 22);
else
{
- as_bad ("Destination register must be R2 or R3");
+ if (!check)
+ as_bad ("Destination register must be R2 or R3");
ret = -1;
}
continue;
INSERTU (opcode, reg - REG_R0, 23, 23);
else
{
- as_bad ("Destination register must be R0 or R1");
+ if (!check)
+ as_bad ("Destination register must be R0 or R1");
ret = -1;
}
continue;
if (operand->expr.X_add_number != 0
&& operand->expr.X_add_number != 0x18)
{
- as_bad ("Invalid indirect addressing mode");
+ if (!check)
+ as_bad ("Invalid indirect addressing mode");
ret = -1;
continue;
}
}
else
{
- as_bad ("Displacement value of %ld is too large",
- (long) exp->X_add_number);
+ if (!check)
+ as_bad ("Displacement value of %ld is too large",
+ (long) exp->X_add_number);
ret = -1;
continue;
}
INSERTU (opcode, reg, 15, 0);
else
{
- as_bad ("Register must be Rn");
+ if (!check)
+ as_bad ("Register must be Rn");
ret = -1;
}
continue;
INSERTU (opcode, reg, 20, 16);
else
{
- as_bad ("Register must be Rn");
+ if (!check)
+ as_bad ("Register must be Rn");
ret = -1;
}
continue;
break;
if (exp->X_op == O_big)
{
- as_bad ("Floating point number not valid in expression");
+ if (!check)
+ as_bad ("Floating point number not valid in expression");
ret = -1;
continue;
}
}
else
{
- as_bad ("Signed immediate value %ld too large",
- (long) exp->X_add_number);
+ if (!check)
+ as_bad ("Signed immediate value %ld too large",
+ (long) exp->X_add_number);
ret = -1;
continue;
}
}
else
{
- as_bad ("Immediate value of %ld is too large",
- (long) exp->X_add_number);
+ if (!check)
+ as_bad ("Immediate value of %ld is too large",
+ (long) exp->X_add_number);
ret = -1;
continue;
}
}
else
{
- as_bad ("Unsigned immediate value %ld too large",
- (long) exp->X_add_number);
+ if (!check)
+ as_bad ("Unsigned immediate value %ld too large",
+ (long) exp->X_add_number);
ret = -1;
continue;
}
}
else
{
- as_bad ("Immediate value of %ld is too large",
- (long) exp->X_add_number);
+ if (!check)
+ as_bad ("Immediate value of %ld is too large",
+ (long) exp->X_add_number);
ret = -1;
continue;
}
break;
if (exp->X_op == O_big)
{
- as_bad ("Floating point number not valid in expression");
+ if (!check)
+ as_bad ("Floating point number not valid in expression");
ret = -1;
continue;
}
}
else
{
- as_bad ("Immediate value %ld too large",
- (long) exp->X_add_number);
+ if (!check)
+ as_bad ("Immediate value %ld too large",
+ (long) exp->X_add_number);
ret = -1;
continue;
}
INSERTU (opcode, reg - REG_IVTP, 4, 0);
else
{
- as_bad ("Register must be ivtp or tvtp");
+ if (!check)
+ as_bad ("Register must be ivtp or tvtp");
ret = -1;
}
continue;
INSERTU (opcode, reg, 20, 16);
else
{
- as_bad ("Register must be address register");
+ if (!check)
+ as_bad ("Register must be address register");
ret = -1;
}
continue;
INSERTU (opcode, reg - REG_IVTP, 20, 16);
else
{
- as_bad ("Register must be ivtp or tvtp");
+ if (!check)
+ as_bad ("Register must be ivtp or tvtp");
ret = -1;
}
continue;
}
}
+static void
+c4x_insn_check (insn)
+ c4x_insn_t *insn;
+{
+
+ if (!strcmp(insn->name, "lda"))
+ {
+ if (insn->num_operands < 2 || insn->num_operands > 2)
+ as_fatal ("Illegal internal LDA insn definition");
+
+ if ( insn->operands[0].mode == M_REGISTER
+ && insn->operands[1].mode == M_REGISTER
+ && insn->operands[0].expr.X_add_number == insn->operands[1].expr.X_add_number )
+ as_bad ("Source and destination register should not be equal");
+ }
+ else if( !strcmp(insn->name, "ldi_ldi")
+ || !strcmp(insn->name, "ldi1_ldi2")
+ || !strcmp(insn->name, "ldi2_ldi1")
+ || !strcmp(insn->name, "ldf_ldf")
+ || !strcmp(insn->name, "ldf1_ldf2")
+ || !strcmp(insn->name, "ldf2_ldf1") )
+ {
+ if ( insn->num_operands < 4 && insn->num_operands > 5 )
+ as_fatal ("Illegal internal %s insn definition", insn->name);
+
+ if ( insn->operands[1].mode == M_REGISTER
+ && insn->operands[insn->num_operands-1].mode == M_REGISTER
+ && insn->operands[1].expr.X_add_number == insn->operands[insn->num_operands-1].expr.X_add_number )
+ as_warn ("Equal parallell destination registers, one result will be discarded");
+ }
+}
+
static void
c4x_insn_output (insn)
c4x_insn_t *insn;
int i;
int parsed = 0;
c4x_inst_t *inst; /* Instruction template. */
+ c4x_inst_t *first_inst;
if (str && insn->parallel)
{
return;
}
- /* FIXME: The list of templates should be scanned
- for the candidates with the desired number of operands.
- We shouldn't issue error messages until we have
- whittled the list of candidate templates to the most
- likely one... We could cache a parsed form of the templates
- to reduce the time required to match a template. */
-
inst = insn->inst;
-
+ first_inst = NULL;
do
- ok = c4x_operands_match (inst, insn);
- while (!ok && !strcmp (inst->name, inst[1].name) && inst++);
+ {
+ ok = c4x_operands_match (inst, insn, 1);
+ if (ok < 0)
+ {
+ if (!first_inst)
+ first_inst = inst;
+ ok = 0;
+ }
+ } while (!ok && !strcmp (inst->name, inst[1].name) && inst++);
if (ok > 0)
- c4x_insn_output (insn);
+ {
+ c4x_insn_check (insn);
+ c4x_insn_output (insn);
+ }
else if (!ok)
- as_bad ("Invalid operands for %s", insn->name);
+ {
+ if (first_inst)
+ c4x_operands_match (first_inst, insn, 0);
+ as_bad ("Invalid operands for %s", insn->name);
+ }
else
as_bad ("Invalid instruction %s", insn->name);
}
return 0;
}
-CONST char *md_shortopts = "bm:prs";
-struct option md_longopts[] =
-{
- {NULL, no_argument, NULL, 0}
-};
-
-size_t md_longopts_size = sizeof (md_longopts);
int
md_parse_option (c, arg)
{
switch (c)
{
- case 'b': /* big model */
- c4x_big_model = 1;
- break;
- case 'm': /* -m[c][34]x */
+ case OPTION_CPU: /* cpu brand */
if (tolower (*arg) == 'c')
arg++;
c4x_cpu = atoi (arg);
if (!IS_CPU_C3X (c4x_cpu) && !IS_CPU_C4X (c4x_cpu))
- as_warn ("Unsupported processor generation %d\n", c4x_cpu);
+ as_warn ("Unsupported processor generation %d", c4x_cpu);
break;
- case 'p': /* push args */
+
+ case OPTION_REV: /* cpu revision */
+ c4x_revision = atoi (arg);
+ break;
+
+ case 'b':
+ as_warn ("Option -b is depreciated, please use -mbig");
+ case OPTION_BIG: /* big model */
+ c4x_big_model = 1;
+ break;
+
+ case 'p':
+ as_warn ("Option -p is depreciated, please use -mmemparm");
+ case OPTION_MEMPARM: /* push args */
c4x_reg_args = 0;
break;
- case 'r': /* register args */
+
+ case 'r':
+ as_warn ("Option -r is depreciated, please use -mregparm");
+ case OPTION_REGPARM: /* register args */
c4x_reg_args = 1;
break;
- case 's': /* small model */
+
+ case 's':
+ as_warn ("Option -s is depreciated, please use -msmall");
+ case OPTION_SMALL: /* small model */
c4x_big_model = 0;
break;
+
+ case OPTION_IDLE2:
+ c4x_idle2 = 1;
+ break;
+
+ case OPTION_LOWPOWER:
+ c4x_lowpower = 1;
+ break;
+
+ case OPTION_ENHANCED:
+ c4x_enhanced = 1;
+ break;
+
default:
return 0;
}
md_show_usage (stream)
FILE *stream;
{
- fputs ("\
-C[34]x options:\n\
--m30 | -m31 | -m32 | -m33 | -m40 | -m44\n\
- specify variant of architecture\n\
--b big memory model\n\
--p pass arguments on stack\n\
--r pass arguments in registers (default)\n\
--s small memory model (default)\n",
- stream);
+ fprintf (stream,
+ _("\nTIC4X options:\n"
+ " -mcpu=CPU -mCPU select architecture variant. CPU can be:\n"
+ " 30 - TMS320C30\n"
+ " 31 - TMS320C31, TMS320LC31\n"
+ " 32 - TMS320C32\n"
+ " 33 - TMS320VC33\n"
+ " 40 - TMS320C40\n"
+ " 44 - TMS320C44\n"
+ " -mrev=REV set cpu hardware revision (integer numbers).\n"
+ " Combinations of -mcpu and -mrev will enable/disable\n"
+ " the appropriate options (-midle2, -mlowpower and\n"
+ " -menhanced) according to the selected type\n"
+ " -mbig select big memory model\n"
+ " -msmall select small memory model (default)\n"
+ " -mregparm select register parameters (default)\n"
+ " -mmemparm select memory parameters\n"
+ " -midle2 enable IDLE2 support\n"
+ " -mlowpower enable LOPOWER and MAXSPEED support\n"
+ " -menhanced enable enhanced opcode support\n"));
}
/* This is called when a line is unrecognized. This is used to handle
if (reloc->howto == (reloc_howto_type *) NULL)
{
as_bad_where (fixP->fx_file, fixP->fx_line,
- "reloc %d not supported by object file format",
+ "Reloc %d not supported by object file format",
(int) fixP->fx_r_type);
return NULL;
}
;;
;; Type K - Register (0-7)
;;
-Type_K: ldf *AR0,R0 &|| ldf *AR0,R0
+Type_K: ldf *AR0,R0 &|| ldf *AR0,R1
ldf *AR0,R0 &|| ldf *AR0,R2
ldf *AR0,R0 &|| ldf *AR0,R7
92: 20a02000.*
00000093 <Type_K>:
- 93: c400c0c0.*
+ 93: c408c0c0.*
94: c410c0c0.*
95: c438c0c0.*
95: 20a02000.*
00000096 <Type_K>:
- 96: c400c0c0.*
+ 96: c408c0c0.*
97: c410c0c0.*
98: c438c0c0.*
;;;
;;; To rebuild this file you must use
;;; ./rebuild.sh
+;;;
+;;; These definitions are used within this file:
+;;; TEST_C3X Enables testing of c3x opcodes
+;;; TEST_C4X Enables testing of c4x opcodes
+;;; TEST_ENH Enable testing of enhanced opcodes
+;;; TEST_IDLE2 Enable testing of IDLE2 command
+;;; TEST_LPWR Enable testing of LOPOWER commands
;;;
#include "opclasses.h"
.text
-start: B_CLASS( absf )
- P_CLASS( absf, stf )
- A_CLASS( absi )
- P_CLASS( absi, sti )
- A_CLASS( addc )
- TC_CLASS( addc )
- B_CLASS( addf )
- SC_CLASS( addf )
- QC_CLASS( addf, stf )
- A_CLASS( addi )
- TC_CLASS( addi )
- QC_CLASS( addi, sti )
- AU_CLASS( and )
- TC_CLASS( and )
- QC_CLASS( and, sti )
- AU_CLASS( andn )
- T_CLASS( andn )
- A_CLASS( ash )
- T_CLASS( ash )
- Q_CLASS( ash, sti )
- J_CLASS( bC, b )
- J_CLASS( bCd, bd )
+ ;;------------------------------------
+ ;; C3X INSNS
+ ;;------------------------------------
+start: B_CLASS( absf, TEST_C3X )
+ P_CLASS( absf, stf, TEST_C3X )
+ A_CLASS( absi, TEST_C3X )
+ P_CLASS( absi, sti, TEST_C3X )
+ A_CLASS( addc, TEST_C3X )
+ TC_CLASS( addc, TEST_C3X )
+ B_CLASS( addf, TEST_C3X )
+ SC_CLASS( addf, TEST_C3X )
+ QC_CLASS( addf, stf, TEST_C3X )
+ A_CLASS( addi, TEST_C3X )
+ TC_CLASS( addi, TEST_C3X )
+ QC_CLASS( addi, sti, TEST_C3X )
+ AU_CLASS( and, TEST_C3X )
+ TC_CLASS( and, TEST_C3X )
+ QC_CLASS( and, sti, TEST_C3X )
+ AU_CLASS( andn, TEST_C3X )
+ T_CLASS( andn, TEST_C3X )
+ A_CLASS( ash, TEST_C3X )
+ T_CLASS( ash, TEST_C3X )
+ Q_CLASS( ash, sti, TEST_C3X )
+ J_CLASS( bC, b, TEST_C3X )
+ J_CLASS( bCd, bd, TEST_C3X )
+ .ifdef TEST_C3X
br_I: br start
brd_I: brd start
call_I: call start
call_JS: callc R0
callc start
- B_CLASS( cmpf )
- S2_CLASS( cmpf )
- A_CLASS( cmpi )
- T2_CLASS( cmpi )
- D_CLASS( dbC, db )
- D_CLASS( dbCd, dbd )
- AF_CLASS( fix )
- P_CLASS( fix, sti )
- BI_CLASS( float )
- P_CLASS( float, stf )
+ .endif
+ B_CLASS( cmpf, TEST_C3X )
+ S2_CLASS( cmpf, TEST_C3X )
+ A_CLASS( cmpi, TEST_C3X )
+ T2_CLASS( cmpi, TEST_C3X )
+ D_CLASS( dbC, db, TEST_C3X )
+ D_CLASS( dbCd, dbd, TEST_C3X )
+ AF_CLASS( fix, TEST_C3X )
+ P_CLASS( fix, sti, TEST_C3X )
+ BI_CLASS( float, TEST_C3X )
+ P_CLASS( float, stf, TEST_C3X )
+ .ifdef TEST_C3X
iack_Z: iack @start
iack *+AR0(1)
idle_Z: idle
+ .endif
.ifdef TEST_IDLE2
idle2_Z: idle2
.endif
- B_CLASS( lde )
- B_CLASS( ldf )
- LL_CLASS( ldf )
- P_CLASS( ldf, stf )
- BB_CLASS( ldfC )
- B6_CLASS( ldfi )
- A_CLASS( ldi )
- LL_CLASS( ldi )
- P_CLASS( ldi, sti )
- AB_CLASS( ldiC )
- A6_CLASS( ldii )
+ B_CLASS( lde, TEST_C3X )
+ B_CLASS( ldf, TEST_C3X )
+ LL_CLASS( ldf, TEST_C3X )
+ P_CLASS( ldf, stf, TEST_C3X )
+ BB_CLASS( ldfC, TEST_C3X )
+ B6_CLASS( ldfi, TEST_C3X )
+ A_CLASS( ldi, TEST_C3X )
+ LL_CLASS( ldi, TEST_C3X )
+ P_CLASS( ldi, sti, TEST_C3X )
+ AB_CLASS( ldiC, TEST_C3X )
+ A6_CLASS( ldii, TEST_C3X )
+ .ifdef TEST_C3X
ldp_Z: ldp start
- B_CLASS( ldm )
+ .endif
+ B_CLASS( ldm, TEST_C3X )
.ifdef TEST_LPWR
lopower_Z: lopower
.endif
- A_CLASS( lsh )
- T_CLASS( lsh )
- Q_CLASS( lsh, sti )
+ A_CLASS( lsh, TEST_C3X )
+ T_CLASS( lsh, TEST_C3X )
+ Q_CLASS( lsh, sti, TEST_C3X )
.ifdef TEST_LPWR
maxspeed_Z: maxspeed
.endif
- B_CLASS( mpyf )
- SC_CLASS( mpyf )
- M_CLASS( mpyf, addf )
- QC_CLASS( mpyf, stf )
- M_CLASS( mpyf, subf )
- A_CLASS( mpyi )
- TC_CLASS( mpyi )
- M_CLASS( mpyi, addi )
- QC_CLASS( mpyi, sti )
- M_CLASS( mpyi, subi )
- A_CLASS( negb )
- B_CLASS( negf )
- P_CLASS( negf, stf )
- A_CLASS( negi )
- P_CLASS( negi, sti )
- A2_CLASS( nop )
- B_CLASS( norm )
- AU_CLASS( not )
- P_CLASS( not, sti )
- AU_CLASS( or )
- TC_CLASS( or )
- QC_CLASS( or, sti )
- R_CLASS( pop )
- RF_CLASS( popf )
- R_CLASS( push )
- RF_CLASS( pushf )
+ B_CLASS( mpyf, TEST_C3X )
+ SC_CLASS( mpyf, TEST_C3X )
+ M_CLASS( mpyf, addf, TEST_C3X )
+ QC_CLASS( mpyf, stf, TEST_C3X )
+ M_CLASS( mpyf, subf, TEST_C3X )
+ A_CLASS( mpyi, TEST_C3X )
+ TC_CLASS( mpyi, TEST_C3X )
+ M_CLASS( mpyi, addi, TEST_C3X )
+ QC_CLASS( mpyi, sti, TEST_C3X )
+ M_CLASS( mpyi, subi, TEST_C3X )
+ A_CLASS( negb, TEST_C3X )
+ B_CLASS( negf, TEST_C3X )
+ P_CLASS( negf, stf, TEST_C3X )
+ A_CLASS( negi, TEST_C3X )
+ P_CLASS( negi, sti, TEST_C3X )
+ A2_CLASS( nop, TEST_C3X )
+ B_CLASS( norm, TEST_C3X )
+ AU_CLASS( not, TEST_C3X )
+ P_CLASS( not, sti, TEST_C3X )
+ AU_CLASS( or, TEST_C3X )
+ TC_CLASS( or, TEST_C3X )
+ QC_CLASS( or, sti, TEST_C3X )
+ R_CLASS( pop, TEST_C3X )
+ RF_CLASS( popf, TEST_C3X )
+ R_CLASS( push, TEST_C3X )
+ RF_CLASS( pushf, TEST_C3X )
+ .ifdef TEST_C3X
reti_Z: retiC
reti
rets_Z: retsC
rets
- B_CLASS( rnd )
- R_CLASS( rol )
- R_CLASS( rolc )
- R_CLASS( ror )
- R_CLASS( rorc )
+ .endif
+ B_CLASS( rnd, TEST_C3X )
+ R_CLASS( rol, TEST_C3X )
+ R_CLASS( rolc, TEST_C3X )
+ R_CLASS( ror, TEST_C3X )
+ R_CLASS( rorc, TEST_C3X )
+ .ifdef TEST_C3X
rptb_I2: rptb start
- A3_CLASS( rpts )
+ .endif
+ A3_CLASS( rpts, TEST_C3X )
+ .ifdef TEST_C3X
sigi_Z: sigi
- B7_CLASS( stf )
- LS_CLASS( stf )
- B7_CLASS( stfi )
- A7_CLASS( sti )
- LS_CLASS( sti )
- A7_CLASS( stii )
- A_CLASS( subb )
- T_CLASS( subb )
- A_CLASS( subc )
- B_CLASS( subf )
- S_CLASS( subf )
- Q_CLASS( subf, stf )
- A_CLASS( subi )
- T_CLASS( subi )
- Q_CLASS( subi, sti )
- A_CLASS( subrb )
- B_CLASS( subrf )
- A_CLASS( subri )
+ .endif
+ B7_CLASS( stf, TEST_C3X )
+ LS_CLASS( stf, TEST_C3X )
+ B7_CLASS( stfi, TEST_C3X )
+ A7_CLASS( sti, TEST_C3X )
+ LS_CLASS( sti, TEST_C3X )
+ A7_CLASS( stii, TEST_C3X )
+ A_CLASS( subb, TEST_C3X )
+ T_CLASS( subb, TEST_C3X )
+ A_CLASS( subc, TEST_C3X )
+ B_CLASS( subf, TEST_C3X )
+ S_CLASS( subf, TEST_C3X )
+ Q_CLASS( subf, stf, TEST_C3X )
+ A_CLASS( subi, TEST_C3X )
+ T_CLASS( subi, TEST_C3X )
+ Q_CLASS( subi, sti, TEST_C3X )
+ A_CLASS( subrb, TEST_C3X )
+ B_CLASS( subrf, TEST_C3X )
+ A_CLASS( subri, TEST_C3X )
+ .ifdef TEST_C3X
swi_Z: swi
trap_Z: trapC 10
trap 10
- AU_CLASS( tstb )
- T2C_CLASS( tstb )
- AU_CLASS( xor )
- TC_CLASS( xor )
- QC_CLASS( xor, sti )
-
+ .endif
+ AU_CLASS( tstb, TEST_C3X )
+ T2C_CLASS( tstb, TEST_C3X )
+ AU_CLASS( xor, TEST_C3X )
+ TC_CLASS( xor, TEST_C3X )
+ QC_CLASS( xor, sti, TEST_C3X )
+
+ ;;------------------------------------
+ ;; C4X INSNS
+ ;;------------------------------------
.ifdef TEST_C4X
- J_CLASS( bCaf, baf )
- J_CLASS( bCat, bat )
- B6_CLASS( frieee )
- P_CLASS( frieee, stf )
+ J_CLASS( bCaf, baf, TEST_C4X )
+ J_CLASS( bCat, bat, TEST_C4X )
+ B6_CLASS( frieee, TEST_C4X )
+ P_CLASS( frieee, stf, TEST_C4X )
+ .ifdef TEST_C4X
laj_I: laj start
laj_JS: lajc R0
lajc start
lat_Z: latC 10
- A_CLASS( lb0 )
- A_CLASS( lb1 )
- A_CLASS( lb2 )
- A_CLASS( lb3 )
- AU_CLASS( lbu0 )
- AU_CLASS( lbu1 )
- AU_CLASS( lbu2 )
- AU_CLASS( lbu3 )
- AY_CLASS( lda )
+ .endif
+ A_CLASS( lb0, TEST_C4X )
+ A_CLASS( lb1, TEST_C4X )
+ A_CLASS( lb2, TEST_C4X )
+ A_CLASS( lb3, TEST_C4X )
+ AU_CLASS( lbu0, TEST_C4X )
+ AU_CLASS( lbu1, TEST_C4X )
+ AU_CLASS( lbu2, TEST_C4X )
+ AU_CLASS( lbu3, TEST_C4X )
+ AY_CLASS( lda, TEST_C4X )
+ .ifdef TEST_C4X
ldep_Z: ldep IVTP, AR0
ldhi_Z: ldhi 35, R0
ldhi start, R0
ldpe_Z: ldpe AR0, IVTP
ldpk_Z: ldpk start
- A_CLASS( lh0 )
- A_CLASS( lh1 )
- AU_CLASS( lhu0 )
- AU_CLASS( lhu1 )
- A_CLASS( lwl0 )
- A_CLASS( lwl1 )
- A_CLASS( lwl2 )
- A_CLASS( lwl3 )
- A_CLASS( lwr0 )
- A_CLASS( lwr1 )
- A_CLASS( lwr2 )
- A_CLASS( lwr3 )
- A_CLASS( mb0 )
- A_CLASS( mb1 )
- A_CLASS( mb2 )
- A_CLASS( mb3 )
- A_CLASS( mh0 )
- A_CLASS( mh1 )
- A_CLASS( mh2 )
- A_CLASS( mh3 )
- A_CLASS( mpyshi )
- TC_CLASS( mpyshi )
- A_CLASS( mpyuhi )
- TC_CLASS( mpyuhi )
- BA_CLASS( rcpf )
+ .endif
+ A_CLASS( lh0, TEST_C4X )
+ A_CLASS( lh1, TEST_C4X )
+ AU_CLASS( lhu0, TEST_C4X )
+ AU_CLASS( lhu1, TEST_C4X )
+ A_CLASS( lwl0, TEST_C4X )
+ A_CLASS( lwl1, TEST_C4X )
+ A_CLASS( lwl2, TEST_C4X )
+ A_CLASS( lwl3, TEST_C4X )
+ A_CLASS( lwr0, TEST_C4X )
+ A_CLASS( lwr1, TEST_C4X )
+ A_CLASS( lwr2, TEST_C4X )
+ A_CLASS( lwr3, TEST_C4X )
+ A_CLASS( mb0, TEST_C4X )
+ A_CLASS( mb1, TEST_C4X )
+ A_CLASS( mb2, TEST_C4X )
+ A_CLASS( mb3, TEST_C4X )
+ A_CLASS( mh0, TEST_C4X )
+ A_CLASS( mh1, TEST_C4X )
+ A_CLASS( mh2, TEST_C4X )
+ A_CLASS( mh3, TEST_C4X )
+ A_CLASS( mpyshi, TEST_C4X )
+ TC_CLASS( mpyshi, TEST_C4X )
+ A_CLASS( mpyuhi, TEST_C4X )
+ TC_CLASS( mpyuhi, TEST_C4X )
+ BA_CLASS( rcpf, TEST_C4X )
+ .ifdef TEST_C4X
retid_Z: retiCd
retid
rptb2_I2: rptb AR0
rptbd_I2: rptbd start
rptbd AR0
- B_CLASS( rsqrf )
- A6_CLASS( sigi )
+ .endif
+ B_CLASS( rsqrf, TEST_C4X )
+ A6_CLASS( sigi, TEST_C4X )
+ .ifdef TEST_C4X
sti2_A7: sti -5, @start
sti -5, *+AR0(5)
stik_Z: stik -5, @start
stik -5, *+AR0(5)
- B_CLASS( toieee )
- P_CLASS( toieee, stf )
+ .endif
+ B_CLASS( toieee, TEST_C4X )
+ P_CLASS( toieee, stf, TEST_C4X )
.endif
.end
/* Opcode infix
- B condition 16--20 U,C,Z,LO,HI, etc.
- C condition 23--27 U,C,Z,LO,HI, etc.
+ B condition 16--20 U,C,Z,LO,HI, etc.
+ C condition 23--27 U,C,Z,LO,HI, etc.
Arguments
, required arg follows
; optional arg follows
- General addressing modes
- * indirect 0--15 *+AR0(5), *++AR0(IR0)
- # direct (for ldp only) 0--15 @start, start
- @ direct 0--15 @start, start
- F short float immediate 0--15 3.5, 0e-3.5e-1
- Q register 0--15 R0, AR0, DP, SP
- R register 16--20 R0, AR0, DP, SP
- S short int immediate 0--15 -5, 5
- D src and dst same reg
-
- Three operand addressing modes
- E register 0--7 R0, R7, R11
- G register 8--15 R0, R7, R11
- I indirect(short) 0--7 *+AR0(1), *+AR0(IR0)
- J indirect(short) 8--15 *+AR0(1), *+AR0(IR0)
- R register 16--20 R0, R7, R11
- W short int (C4x) 0--7 -3, 5
- C indirect(short) (C4x) 0--7 *+AR0(5)
- O indirect(short) (C4x) 8--15 *+AR0(5)
-
- Parallel instruction addressing modes
- E register 0--7 R0, R7, R11
- G register 8--15 R0, R7, R11
- H register 18--16 R0, R7
- I indirect(short) 0--7 *+AR0(1), *+AR0(IR0)
- J indirect(short) 8--15 *+AR0(1), *+AR0(IR0)
- K register 19--21 R0, R7
- L register 22--24 R0, R7
- M register (R2,R3) 22--22 R2, R3
- N register (R0,R1) 23--23 R0, R1
-
- Misc. addressing modes
- A address register 22--24 AR0, AR7
- B unsigned integer 0--23 @start, start (absolute on C3x, relative on C4x)
- P displacement (PC Rel) 0--15 @start, start
- U unsigned integer 0--15 0, 65535
- V vector (C4x: 0--8) 0--4 25, 7
- T integer (C4x) 16--20 -5, 12
- Y address reg (C4x) 16--20 AR0, DP, SP, IR0
- X expansion reg (C4x) 0--4 IVTP, TVTP
- Z expansion reg (C4x) 16--20 IVTP, TVTP
+ Argument types bits [classes] - example
+ -----------------------------------------------------------
+ * indirect (all) 0--15 [A,AB,AU,AF,A2,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - *+AR0(5), *++AR0(IR0)
+ # direct (for LDP) 0--15 [Z] - @start, start
+ @ direct 0--15 [A,AB,AU,AF,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - @start, start
+ A address register 22--24 [D] - AR0, AR7
+ B unsigned integer 0--23 [I,I2] - @start, start (absolute on C3x, relative on C4x)
+ C indirect (disp - C4x) 0--7 [S,SC,S2,T,TC,T2,T2C] - *+AR0(5)
+ E register (all) 0--7 [T,TC,T2,T2C] - R0, R7, R11, AR0, DP
+ e register (0-11) 0--7 [S,SC,S2] - R0, R7, R11
+ F short float immediate 0--15 [AF,B,BA,BB] - 3.5, 0e-3.5e-1
+ G register (all) 8--15 [T,TC,T2,T2C] - R0, R7, R11, AR0, DP
+ g register (0-11) 0--7 [S,SC,S2] - R0, R7, R11
+ H register (0-7) 18--16 [LS,M,P,Q] - R0, R7
+ I indirect (no disp) 0--7 [S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
+ i indirect (enhanced) 0--7 [LL,LS,M,P,Q,QC] - *+AR0(1), R5
+ J indirect (no disp) 8--15 [LL,LS,P,Q,QC,S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
+ j indirect (enhanced) 8--15 [M] - *+AR0(1), R5
+ K register 19--21 [LL,M,Q,QC] - R0, R7
+ L register 22--24 [LL,LS,P,Q,QC] - R0, R7
+ M register (R2,R3) 22--22 [M] R2, R3
+ N register (R0,R1) 23--23 [M] R0, R1
+ O indirect(disp - C4x) 8--15 [S,SC,S2,T,TC,T2] - *+AR0(5)
+ P displacement (PC Rel) 0--15 [D,J,JS] - @start, start
+ Q register (all) 0--15 [A,AB,AU,A2,A3,AY,BA,BI,D,I2,J,JS] - R0, AR0, DP, SP
+ q register (0-11) 0--15 [AF,B,BB] - R0, R7, R11
+ R register (all) 16--20 [A,AB,AU,AF,A6,A7,R,T,TC] - R0, AR0, DP, SP
+ r register (0-11) 16--20 [B,BA,BB,BI,B6,B7,RF,S,SC] - R0, R1, R11
+ S short int immediate 0--15 [A,AB,AY,BI] - -5, 5
+ T integer (C4x) 16--20 [Z] - -5, 12
+ U unsigned integer 0--15 [AU,A3] - 0, 65535
+ V vector (C4x: 0--8) 0--4 [Z] - 25, 7
+ W short int (C4x) 0--7 [T,TC,T2,T2C] - -3, 5
+ X expansion reg (C4x) 0--4 [Z] - IVTP, TVTP
+ Y address reg (C4x) 16--20 [Z] - AR0, DP, SP, IR0
+ Z expansion reg (C4x) 16--20 [Z] - IVTP, TVTP
*/
/* A: General 2-operand integer operations
SUBB, SUBC, SUBI, SUBRB, SUBRI, C4x: LBn, LHn, LWLn, LWRn,
MBn, MHn, MPYSHI, MPYUHI
*/
-#define A_CLASS(name) \
+#define A_CLASS(name, level) \
+ .ifdef level &\
name##_A: &\
name AR1, AR0 /* Q;R */ &\
name AR0 /* Q;R */ &\
name @start, AR0 /* @,R */ &\
name *+AR0(5), AR0 /* *,R */ &\
- name -5, AR0 /* S,R */
+ name -5, AR0 /* S,R */ &\
+ .endif
/* AB: General 2-operand integer operation with condition
dst = Register (R)
Instr: 1/0 - LDIc
*/
-#define AB_CLASS(name) \
+#define AB_CLASS(name, level) \
+ .ifdef level &\
name##_AB: &\
name AR1, AR0 /* Q;R */ &\
name AR0 /* Q;R */ &\
name @start, AR0 /* @,R */ &\
name *+AR0(5), AR0 /* *,R */ &\
- name -5, AR0 /* S,R */
+ name -5, AR0 /* S,R */ &\
+ .endif
/* AU: General 2-operand unsigned integer operation
dst = Register (R)
Instr: 6/2 - AND, ANDN, NOT, OR, TSTB, XOR, C4x: LBUn, LHUn
*/
-#define AU_CLASS(name) \
+#define AU_CLASS(name, level) \
+ .ifdef level &\
name##_AU: &\
name AR1, AR0 /* Q;R */ &\
name AR0 /* Q;R */ &\
name @start, AR0 /* @,R */ &\
name *+AR0(5), AR0 /* *,R */ &\
- name 5, AR0 /* U,R */
+ name 5, AR0 /* U,R */ &\
+ .endif
/* AF: General 2-operand float to integer operation
Syntax: <i> src, dst
- src = Register 0-11 (Q), Direct (@), Indirect (*), Float immediate (F)
+ src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
dst = Register (R)
Instr: 1/0 - FIX
*/
-#define AF_CLASS(name) \
+#define AF_CLASS(name, level) \
+ .ifdef level &\
name##_AF: &\
- name R1, R0 /* Q;R */ &\
- name R0 /* Q;R */ &\
+ name R1, R0 /* q;R */ &\
+ name R0 /* q;R */ &\
name @start, AR0 /* @,R */ &\
name *+AR0(5), AR0 /* *,R */ &\
- name 3.5, AR0 /* F,R */
+ name 3.5, AR0 /* F,R */ &\
+ .endif
/* A2: Limited 1-operand (integer) operation
src = Register (Q), Indirect (*), None
Instr: 1/0 - NOP
*/
-#define A2_CLASS(name) \
+#define A2_CLASS(name, level) \
+ .ifdef level &\
name##_A2: &\
name AR0 /* Q */ &\
name *+AR0(5) /* * */ &\
- name /* */
+ name /* */ &\
+ .endif
/* A3: General 1-operand unsigned integer operation
src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U)
Instr: 1/0 - RPTS
*/
-#define A3_CLASS(name) \
+#define A3_CLASS(name, level) \
+ .ifdef level &\
name##_A3: &\
name AR1 /* Q */ &\
name @start /* @ */ &\
name *+AR0(5) /* * */ &\
- name 5 /* U */
+ name 5 /* U */ &\
+ .endif
/* A6: Limited 2-operand integer operation
dst = Register (R)
Instr: 1/1 - LDII, C4x: SIGI
*/
-#define A6_CLASS(name) \
+#define A6_CLASS(name, level) \
+ .ifdef level &\
name##_A6: &\
name @start, AR0 /* @,R */ &\
- name *+AR0(5), AR0 /* *,R */
+ name *+AR0(5), AR0 /* *,R */ &\
+ .endif
/* A7: Limited 2-operand integer store operation
dst = Direct (@), Indirect (*)
Instr: 2/0 - STI, STII
*/
-#define A7_CLASS(name) \
+#define A7_CLASS(name, level) \
+ .ifdef level &\
name##_A7: &\
name AR0, @start /* R,@ */ &\
- name AR0, *+AR0(5) /* R,* */
+ name AR0, *+AR0(5) /* R,* */ &\
+ .endif
/* AY: General 2-operand signed address load operation
Instr: 0/1 - C4x: LDA
Note: Q and Y should *never* be the same register
*/
-#define AY_CLASS(name) \
+#define AY_CLASS(name, level) \
+ .ifdef level &\
name##_AY: &\
name AR1, AR0 /* Q,Y */ &\
name @start, AR0 /* @,Y */ &\
name *+AR0(5), AR0 /* *,Y */ &\
- name -5, AR0 /* S,Y */
+ name -5, AR0 /* S,Y */ &\
+ .endif
/* B: General 2-operand float operation
Syntax: <i> src, dst
- src = Register 0-11 (Q), Direct (@), Indirect (*), Float immediate (F)
- dst = Register 0-11 (R)
+ src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
+ dst = Register 0-11 (r)
Instr: 12/2 - ABSF, ADDF, CMPF, LDE, LDF, LDM, MPYF, NEGF, NORM, RND,
SUBF, SUBRF, C4x: RSQRF, TOIEEE
*/
-#define B_CLASS(name) \
+#define B_CLASS(name, level) \
+ .ifdef level &\
name##_B: &\
- name R1, R0 /* Q;R */ &\
- name R0 /* Q;R */ &\
- name @start, R0 /* @,R */ &\
- name *+AR0(5), R0 /* *,R */ &\
- name 3.5, R0 /* F,R */
+ name R1, R0 /* q;r */ &\
+ name R0 /* q;r */ &\
+ name @start, R0 /* @,r */ &\
+ name *+AR0(5), R0 /* *,r */ &\
+ name 3.5, R0 /* F,r */ &\
+ .endif
/* BA: General 2-operand integer to float operation
Syntax: <i> src, dst
src = Register (Q), Direct (@), Indirect (*), Float immediate (F)
- dst = Register 0-11 (R)
+ dst = Register 0-11 (r)
Instr: 0/1 - C4x: CRCPF
*/
-#define BA_CLASS(name) \
+#define BA_CLASS(name, level) \
+ .ifdef level &\
name##_BA: &\
- name AR1, R0 /* Q;R */ &\
- name R0 /* Q;R */ &\
- name @start, R0 /* @,R */ &\
- name *+AR0(5), R0 /* *,R */ &\
- name 3.5, R0 /* F,R */
+ name AR1, R0 /* Q;r */ &\
+ name R0 /* Q;r */ &\
+ name @start, R0 /* @,r */ &\
+ name *+AR0(5), R0 /* *,r */ &\
+ name 3.5, R0 /* F,r */ &\
+ .endif
/* BB: General 2-operand conditional float operation
Syntax: <i>c src, dst
c = Condition
- src = Register 0-11 (Q), Direct (@), Indirect (*), Float immediate (F)
- dst = Register 0-11 (R)
+ src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)
+ dst = Register 0-11 (r)
Instr: 1/0 - LDFc
*/
-#define BB_CLASS(name) \
+#define BB_CLASS(name, level) \
+ .ifdef level &\
name##_BB: &\
- name R1, R0 /* Q;R */ &\
- name R0 /* Q;R */ &\
- name @start, R0 /* @,R */ &\
- name *+AR0(5), R0 /* *,R */ &\
- name 3.5, R0 /* F,R */
+ name R1, R0 /* q;r */ &\
+ name R0 /* q;r */ &\
+ name @start, R0 /* @,r */ &\
+ name *+AR0(5), R0 /* *,r */ &\
+ name 3.5, R0 /* F,r */ &\
+ .endif
/* BI: General 2-operand integer to float operation (yet different to BA)
Syntax: <i> src, dst
src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)
- dst = Register 0-11 (R)
+ dst = Register 0-11 (r)
Instr: 1/0 - FLOAT
*/
-#define BI_CLASS(name) \
+#define BI_CLASS(name, level) \
+ .ifdef level &\
name##_BI: &\
- name AR1, R0 /* Q;R */ &\
- name R0 /* Q;R */ &\
- name @start, R0 /* @,R */ &\
- name *+AR0(5), R0 /* *,R */ &\
- name -5, R0 /* S,R */
+ name AR1, R0 /* Q;r */ &\
+ name R0 /* Q;r */ &\
+ name @start, R0 /* @,r */ &\
+ name *+AR0(5), R0 /* *,r */ &\
+ name -5, R0 /* S,r */ &\
+ .endif
/* B6: Limited 2-operand float operation
Syntax: <i> src, dst
src = Direct (@), Indirect (*)
- dst = Register 0-11 (R)
+ dst = Register 0-11 (r)
Instr: 1/1 - LDFI, C4x: FRIEEE
*/
-#define B6_CLASS(name) \
+#define B6_CLASS(name, level) \
+ .ifdef level &\
name##_B6: &\
- name @start, R0 /* @,R */ &\
- name *+AR0(5), R0 /* *,R */
+ name @start, R0 /* @,r */ &\
+ name *+AR0(5), R0 /* *,r */ &\
+ .endif
/* B7: Limited 2-operand float store operation
Syntax: <i> src, dst
- src = Register 0-11 (R)
+ src = Register 0-11 (r)
dst = Direct (@), Indirect (*)
Instr: 2/0 - STF, STFI
*/
-#define B7_CLASS(name) \
+#define B7_CLASS(name, level) \
+ .ifdef level &\
name##_B7: &\
- name R0, @start /* R,@ */ &\
- name R0, *+AR0(5) /* R,* */
+ name R0, @start /* r,@ */ &\
+ name R0, *+AR0(5) /* r,* */ &\
+ .endif
/* D: Decrement and brach operations
Syntax: <i>c ARn, dst
c = condition
- ARn = AR register 0-11 (A)
+ ARn = AR register 0-7 (A)
dst = Register (Q), PC-relative (P)
Instr: 2/0 - DBc, DBcD
- Alias: <name1> <name2>
+ Alias: <namea> <nameb>
*/
-#define D_CLASS(name1, name2) \
-name1##_D: &\
- name1 AR0, R0 /* A,Q */ &\
- name1 AR0, start /* A,P */ &\
-name2##_D: &\
- name2 AR0, R0 /* A,Q */ &\
- name2 AR0, start /* A,P */
+#define D_CLASS(namea, nameb, level) \
+ .ifdef level &\
+namea##_D: &\
+ namea AR0, R0 /* A,Q */ &\
+ namea AR0, start /* A,P */ &\
+nameb##_D: &\
+ nameb AR0, R0 /* A,Q */ &\
+ nameb AR0, start /* A,P */ &\
+ .endif
/* J: General conditional branch operations
c = Condition
dst = Register (Q), PC-relative (P)
Instr: 2/3 - Bc, BcD, C4x: BcAF, BcAT, LAJc
- Alias: <name1> <name2>
+ Alias: <namea> <nameb>
*/
-#define J_CLASS(name1, name2) \
-name1##_J: &\
- name1 R0 /* Q */ &\
- name1 start /* P */ &\
-name2##_J: &\
- name2 R0 /* Q */ &\
- name2 start /* P */
+#define J_CLASS(namea, nameb, level) \
+ .ifdef level &\
+namea##_J: &\
+ namea R0 /* Q */ &\
+ namea start /* P */ &\
+nameb##_J: &\
+ nameb R0 /* Q */ &\
+ nameb start /* P */ &\
+ .endif
/* LL: Load-load parallell operation
Syntax: <i> src2, dst2 || <i> src1, dst1
src1 = Indirect 0,1,IR0,IR1 (J)
dst1 = Register 0-7 (K)
- src2 = Indirect 0,1,IR0,IR1 (I)
+ src2 = Indirect 0,1,IR0,IR1, ENH: Register (i)
dst2 = Register 0-7 (L)
Instr: 2/0 - LDF||LDF, LDI||LDI
Alias: i||i, i1||i2, i2||i1
*/
-#define LL_CLASS(name) \
+#define LL_CLASS(name, level) \
+ .ifdef level &\
name##_LL: &\
- name *+AR0(1), R0 &|| name *+AR1(1), R1 /* I,L|J,K */ &\
- name##2 *+AR0(1), R0 &|| name##1 *+AR1(1), R1 /* I,L|J,K */ &\
- name##1 *+AR1(1), R1 &|| name##2 *+AR0(1), R0 /* J,K|I,L */
+ name *+AR0(1), R0 &|| name *+AR1(1), R1 /* i;L|J,K */ &\
+ name##2 *+AR0(1), R0 &|| name##1 *+AR1(1), R1 /* i;L|J,K */ &\
+ name##1 *+AR1(1), R1 &|| name##2 *+AR0(1), R0 /* J,K|i;L */ &\
+ .endif &\
+ .ifdef TEST_ENH &\
+name##_LL_enh: &\
+ name R0, R0 &|| name *+AR1(1), R1 /* i;L|J,K */ &\
+ name R0 &|| name *+AR1(1), R1 /* i;L|J,K */ &\
+ name##2 R0, R0 &|| name##1 *+AR1(1), R1 /* i;L|J,K */ &\
+ name##2 R0 &|| name##1 *+AR1(1), R1 /* i;L|J,K */ &\
+ name##1 *+AR1(1), R1 &|| name##2 R0, R0 /* J,K|i;L */ &\
+ name##1 *+AR1(1), R1 &|| name##2 R0 /* J,K|i;L */ &\
+ .endif
+
/* LS: Store-store parallell operation
src1 = Register 0-7 (H)
dst1 = Indirect 0,1,IR0,IR1 (J)
src2 = Register 0-7 (L)
- dst2 = Indirect 0,1,IR0,IR1 (I)
+ dst2 = Indirect 0,1,IR0,IR1, ENH: register (i)
Instr: 2/0 - STF||STF, STI||STI
Alias: i||i, i1||i2, i2||i1.
*/
-#define LS_CLASS(name) \
+#define LS_CLASS(name, level) \
+ .ifdef level &\
name##_LS: &\
- name R0, *+AR0(1) &|| name R1, *+AR1(1) /* L,I|H,J */ &\
- name##2 R0, *+AR0(1) &|| name##1 R1, *+AR1(1) /* L,I|H,J */ &\
- name##1 R1, *+AR1(1) &|| name##2 R0, *+AR0(1) /* H,J|L,I */
+ name R0, *+AR0(1) &|| name R1, *+AR1(1) /* L;i|H,J */ &\
+ name##2 R0, *+AR0(1) &|| name##1 R1, *+AR1(1) /* L;i|H,J */ &\
+ name##1 R1, *+AR1(1) &|| name##2 R0, *+AR0(1) /* H,J|L;i */ &\
+ .endif &\
+ .ifdef TEST_ENH &\
+name##_LS_enh: &\
+ name R0, R0 &|| name R1, *+AR1(1) /* L;i|H,J */ &\
+ name R0 &|| name R1, *+AR1(1) /* L;i|H,J */ &\
+ name##2 R0, R0 &|| name##1 R1, *+AR1(1) /* L;i|H,J */ &\
+ name##2 R0 &|| name##1 R1, *+AR1(1) /* L;i|H,J */ &\
+ name##1 R1, *+AR1(1) &|| name##2 R0, R0 /* H,J|L;i */ &\
+ name##1 R1, *+AR1(1) &|| name##2 R0 /* H,J|L;i */ &\
+ .endif
/* M: General multiply and add/sub operations
<ia> src1,src3,dst1 || <ib> src4,src2,dst2 [03]
src1 = Register 0-7 (K)
src2 = Register 0-7 (H)
- src3 = Indirect 0,1,IR0,IR1 (J)
- src4 = Indirect 0,1,IR0,IR1 (I)
+ src3 = Indirect 0,1,IR0,IR1, ENH: register (j)
+ src4 = Indirect 0,1,IR0,IR1, ENH: register (i)
dst1 = Register 0-1 (N)
dst2 = Register 2-3 (M)
Instr: 4/0 - MPYF3||ADDF3, MPYF3||SUBF3, MPYI3||ADDI3, MPYI3||SUBI3
Alias: a||b, a3||n, a||b3, a3||b3, b||a, b3||a, b||a3, b3||a3
*/
-#define M_CLASS(namea, nameb) \
+#define M_CLASS(namea, nameb, level) \
+ .ifdef level &\
namea##_##nameb##_M: &\
- namea *+AR0(1), *+AR1(1), R0 &|| nameb R0, R1, R2 /* I,J,N|H,K;M */ &\
- namea *+AR0(1), *+AR1(1), R0 &|| nameb R0, R2 /* I,J,N|H,K;M */ &\
- namea *+AR0(1), R0, R0 &|| nameb R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
- namea *+AR0(1), R0 &|| nameb R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
- namea R0, *+AR0(1), R0 &|| nameb R0, *+AR1(1), R2 /* K,J,N|H,I,M */ &\
- namea R2, R1, R0 &|| nameb *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
- namea R2, R0 &|| nameb *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
- namea *+AR0(1), R1, R0 &|| nameb *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
- namea *+AR0(1), R0 &|| nameb *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
- namea *+AR0(1), R1, R0 &|| nameb *+AR1(1), R2 /* J,K;N|I,H;M */ &\
- namea *+AR0(1), R0 &|| nameb *+AR1(1), R2 /* J,K;N|I,H;M */ &\
- namea R0, *+AR0(1), R0 &|| nameb *+AR1(1), R0, R2 /* K,J,N|I,H;M */ &\
- namea R0, *+AR0(1), R0 &|| nameb *+AR1(1), R2 /* K,J,N|I,H;M */ &\
+ namea *+AR0(1), *+AR1(1), R0 &|| nameb R0, R1, R2 /* i;j;N|H;K;M */ &\
+ namea *+AR0(1), *+AR1(1), R0 &|| nameb R0, R2 /* i;j;N|H;K;M */ &\
+ namea *+AR0(1), R0, R0 &|| nameb R0, *+AR1(1), R2 /* j;K;N|H;i;M */ &\
+ namea *+AR0(1), R0 &|| nameb R0, *+AR1(1), R2 /* j;K;N|H;i;M */ &\
+ namea R0, *+AR0(1), R0 &|| nameb R0, *+AR1(1), R2 /* K;j;N|H;i;M */ &\
+ namea R2, R1, R0 &|| nameb *+AR0(1), *+AR1(1), R2 /* H;K;N|i;j;M */ &\
+ namea R2, R0 &|| nameb *+AR0(1), *+AR1(1), R2 /* H;K;N|i;j;M */ &\
+ namea *+AR0(1), R1, R0 &|| nameb *+AR1(1), R3, R2 /* j;K;N|i;H;M */ &\
+ namea *+AR0(1), R0 &|| nameb *+AR1(1), R3, R2 /* j;K;N|i;H;M */ &\
+ namea *+AR0(1), R1, R0 &|| nameb *+AR1(1), R2 /* j;K;N|i;H;M */ &\
+ namea *+AR0(1), R0 &|| nameb *+AR1(1), R2 /* j;K;N|i;H;M */ &\
+ namea R0, *+AR0(1), R0 &|| nameb *+AR1(1), R0, R2 /* K;j;N|i;H;M */ &\
+ namea R0, *+AR0(1), R0 &|| nameb *+AR1(1), R2 /* K;j;N|i;H;M */ &\
+ .endif &\
+ .ifdef TEST_ENH &\
+namea##_##nameb##_M_enh: &\
+ namea R0, R0, R0 &|| nameb R2, R2, R2 /* i;j;N|H;K;M */ &\
+ namea R0, R0 &|| nameb R2, R2, R2 /* i;j;N|H;K;M */ &\
+ namea R0 &|| nameb R2, R2, R2 /* i;j;N|H;K;M */ &\
+ namea R0, R0 &|| nameb R2, R2 /* i;j;N|H;K;M */ &\
+ namea R0 &|| nameb R2, R2 /* i;j;N|H;K;M */ &\
+ namea R0 &|| nameb R2 /* i;j;N|H;K;M */ &\
+ namea AR0, AR0, R0 &|| nameb R2, R2, R2 /* i;j;N|H;K;M */ &\
+ namea AR0, R0, R0 &|| nameb R0, AR0, R2 /* j;K;N|H;i;M */ &\
+ namea R0, AR0, R0 &|| nameb R0, AR0, R2 /* K;j;N|H;i;M */ &\
+ namea R2, R1, R0 &|| nameb AR0, AR1, R2 /* H;K;N|i;j;M */ &\
+ namea AR0, R1, R0 &|| nameb AR0, R3, R2 /* j;K;N|i;H;M */ &\
+ namea R0, AR0, R0 &|| nameb AR0, R0, R2 /* K;j;N|i;H;M */ &\
+ .endif &\
+ .ifdef level &\
namea##3_##nameb##_M: &\
- namea##3 *+AR0(1), *+AR1(1), R0 &|| nameb R0, R1, R2 /* I,J,N|H,K;M */ &\
- namea##3 *+AR0(1), *+AR1(1), R0 &|| nameb R0, R2 /* I,J,N|H,K;M */ &\
- namea##3 *+AR0(1), R0, R0 &|| nameb R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
- namea##3 *+AR0(1), R0 &|| nameb R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
- namea##3 R0, *+AR0(1), R0 &|| nameb R0, *+AR1(1), R2 /* K,J,N|H,I,M */ &\
- namea##3 R2, R1, R0 &|| nameb *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
- namea##3 R2, R0 &|| nameb *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
- namea##3 *+AR0(1), R1, R0 &|| nameb *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
- namea##3 *+AR0(1), R0 &|| nameb *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
- namea##3 *+AR0(1), R1, R0 &|| nameb *+AR1(1), R2 /* J,K;N|I,H;M */ &\
- namea##3 *+AR0(1), R0 &|| nameb *+AR1(1), R2 /* J,K;N|I,H;M */ &\
- namea##3 R0, *+AR0(1), R0 &|| nameb *+AR1(1), R0, R2 /* K,J,N|I,H;M */ &\
- namea##3 R0, *+AR0(1), R0 &|| nameb *+AR1(1), R2 /* K,J,N|I,H;M */ &\
+ namea##3 *+AR0(1), *+AR1(1), R0 &|| nameb R0, R1, R2 /* i;j;N|H;K;M */ &\
+ namea##3 *+AR0(1), *+AR1(1), R0 &|| nameb R0, R2 /* i;j;N|H;K;M */ &\
+ namea##3 *+AR0(1), R0, R0 &|| nameb R0, *+AR1(1), R2 /* j;K;N|H;i;M */ &\
+ namea##3 *+AR0(1), R0 &|| nameb R0, *+AR1(1), R2 /* j;K;N|H;i;M */ &\
+ namea##3 R0, *+AR0(1), R0 &|| nameb R0, *+AR1(1), R2 /* K;j;N|H;i;M */ &\
+ namea##3 R2, R1, R0 &|| nameb *+AR0(1), *+AR1(1), R2 /* H;K;N|i;j;M */ &\
+ namea##3 R2, R0 &|| nameb *+AR0(1), *+AR1(1), R2 /* H;K;N|i;j;M */ &\
+ namea##3 *+AR0(1), R1, R0 &|| nameb *+AR1(1), R3, R2 /* j;K;N|i;H;M */ &\
+ namea##3 *+AR0(1), R0 &|| nameb *+AR1(1), R3, R2 /* j;K;N|i;H;M */ &\
+ namea##3 *+AR0(1), R1, R0 &|| nameb *+AR1(1), R2 /* j;K;N|i;H;M */ &\
+ namea##3 *+AR0(1), R0 &|| nameb *+AR1(1), R2 /* j;K;N|i;H;M */ &\
+ namea##3 R0, *+AR0(1), R0 &|| nameb *+AR1(1), R0, R2 /* K;j;N|i;H;M */ &\
+ namea##3 R0, *+AR0(1), R0 &|| nameb *+AR1(1), R2 /* K;j;N|i;H;M */ &\
+ .endif &\
+ .ifdef TEST_ENH &\
+namea##3_##nameb##_M_enh: &\
+ namea##3 R0, R0, R0 &|| nameb R2, R2, R2 /* i;j;N|H;K;M */ &\
+ namea##3 R0, R0 &|| nameb R2, R2, R2 /* i;j;N|H;K;M */ &\
+ namea##3 R0 &|| nameb R2, R2, R2 /* i;j;N|H;K;M */ &\
+ namea##3 R0, R0 &|| nameb R2, R2 /* i;j;N|H;K;M */ &\
+ namea##3 R0 &|| nameb R2, R2 /* i;j;N|H;K;M */ &\
+ namea##3 R0 &|| nameb R2 /* i;j;N|H;K;M */ &\
+ namea##3 AR0, AR0, R0 &|| nameb R2, R2, R2 /* i;j;N|H;K;M */ &\
+ namea##3 AR0, R0, R0 &|| nameb R0, AR0, R2 /* j;K;N|H;i;M */ &\
+ namea##3 R0, AR0, R0 &|| nameb R0, AR0, R2 /* K;j;N|H;i;M */ &\
+ namea##3 R2, R1, R0 &|| nameb AR0, AR1, R2 /* H;K;N|i;j;M */ &\
+ namea##3 AR0, R1, R0 &|| nameb AR0, R3, R2 /* j;K;N|i;H;M */ &\
+ namea##3 R0, AR0, R0 &|| nameb AR0, R0, R2 /* K;j;N|i;H;M */ &\
+ .endif &\
+ .ifdef level &\
namea##_##nameb##3_M: &\
- namea *+AR0(1), *+AR1(1), R0 &|| nameb##3 R0, R1, R2 /* I,J,N|H,K;M */ &\
- namea *+AR0(1), *+AR1(1), R0 &|| nameb##3 R0, R2 /* I,J,N|H,K;M */ &\
- namea *+AR0(1), R0, R0 &|| nameb##3 R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
- namea *+AR0(1), R0 &|| nameb##3 R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
- namea R0, *+AR0(1), R0 &|| nameb##3 R0, *+AR1(1), R2 /* K,J,N|H,I,M */ &\
- namea R2, R1, R0 &|| nameb##3 *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
- namea R2, R0 &|| nameb##3 *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
- namea *+AR0(1), R1, R0 &|| nameb##3 *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
- namea *+AR0(1), R0 &|| nameb##3 *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
- namea *+AR0(1), R1, R0 &|| nameb##3 *+AR1(1), R2 /* J,K;N|I,H;M */ &\
- namea *+AR0(1), R0 &|| nameb##3 *+AR1(1), R2 /* J,K;N|I,H;M */ &\
- namea R0, *+AR0(1), R0 &|| nameb##3 *+AR1(1), R0, R2 /* K,J,N|I,H;M */ &\
- namea R0, *+AR0(1), R0 &|| nameb##3 *+AR1(1), R2 /* K,J,N|I,H;M */ &\
+ namea *+AR0(1), *+AR1(1), R0 &|| nameb##3 R0, R1, R2 /* i;j;N|H;K;M */ &\
+ namea *+AR0(1), *+AR1(1), R0 &|| nameb##3 R0, R2 /* i;j;N|H;K;M */ &\
+ namea *+AR0(1), R0, R0 &|| nameb##3 R0, *+AR1(1), R2 /* j;K;N|H;i;M */ &\
+ namea *+AR0(1), R0 &|| nameb##3 R0, *+AR1(1), R2 /* j;K;N|H;i;M */ &\
+ namea R0, *+AR0(1), R0 &|| nameb##3 R0, *+AR1(1), R2 /* K;j;N|H;i;M */ &\
+ namea R2, R1, R0 &|| nameb##3 *+AR0(1), *+AR1(1), R2 /* H;K;N|i;j;M */ &\
+ namea R2, R0 &|| nameb##3 *+AR0(1), *+AR1(1), R2 /* H;K;N|i;j;M */ &\
+ namea *+AR0(1), R1, R0 &|| nameb##3 *+AR1(1), R3, R2 /* j;K;N|i;H;M */ &\
+ namea *+AR0(1), R0 &|| nameb##3 *+AR1(1), R3, R2 /* j;K;N|i;H;M */ &\
+ namea *+AR0(1), R1, R0 &|| nameb##3 *+AR1(1), R2 /* j;K;N|i;H;M */ &\
+ namea *+AR0(1), R0 &|| nameb##3 *+AR1(1), R2 /* j;K;N|i;H;M */ &\
+ namea R0, *+AR0(1), R0 &|| nameb##3 *+AR1(1), R0, R2 /* K;j;N|i;H;M */ &\
+ namea R0, *+AR0(1), R0 &|| nameb##3 *+AR1(1), R2 /* K;j;N|i;H;M */ &\
+ .endif &\
+ .ifdef TEST_ENH &\
+namea##_##nameb##3_M_enh: &\
+ namea R0, R0, R0 &|| nameb##3 R2, R2, R2 /* i;j;N|H;K;M */ &\
+ namea R0, R0 &|| nameb##3 R2, R2, R2 /* i;j;N|H;K;M */ &\
+ namea R0 &|| nameb##3 R2, R2, R2 /* i;j;N|H;K;M */ &\
+ namea R0, R0 &|| nameb##3 R2, R2 /* i;j;N|H;K;M */ &\
+ namea R0 &|| nameb##3 R2, R2 /* i;j;N|H;K;M */ &\
+ namea R0 &|| nameb##3 R2 /* i;j;N|H;K;M */ &\
+ namea AR0, AR0, R0 &|| nameb##3 R2, R2, R2 /* i;j;N|H;K;M */ &\
+ namea AR0, R0, R0 &|| nameb##3 R0, AR0, R2 /* j;K;N|H;i;M */ &\
+ namea R0, AR0, R0 &|| nameb##3 R0, AR0, R2 /* K;j;N|H;i;M */ &\
+ namea R2, R1, R0 &|| nameb##3 AR0, AR1, R2 /* H;K;N|i;j;M */ &\
+ namea AR0, R1, R0 &|| nameb##3 AR0, R3, R2 /* j;K;N|i;H;M */ &\
+ namea R0, AR0, R0 &|| nameb##3 AR0, R0, R2 /* K;j;N|i;H;M */ &\
+ .endif &\
+ .ifdef level &\
namea##3_##nameb##3_M: &\
- namea##3 *+AR0(1), *+AR1(1), R0 &|| nameb##3 R0, R1, R2 /* I,J,N|H,K;M */ &\
- namea##3 *+AR0(1), *+AR1(1), R0 &|| nameb##3 R0, R2 /* I,J,N|H,K;M */ &\
- namea##3 *+AR0(1), R0, R0 &|| nameb##3 R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
- namea##3 *+AR0(1), R0 &|| nameb##3 R0, *+AR1(1), R2 /* J,K;N|H,I,M */ &\
- namea##3 R0, *+AR0(1), R0 &|| nameb##3 R0, *+AR1(1), R2 /* K,J,N|H,I,M */ &\
- namea##3 R2, R1, R0 &|| nameb##3 *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
- namea##3 R2, R0 &|| nameb##3 *+AR0(1), *+AR1(1), R2 /* H,K;N|I,J,M */ &\
- namea##3 *+AR0(1), R1, R0 &|| nameb##3 *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
- namea##3 *+AR0(1), R0 &|| nameb##3 *+AR1(1), R3, R2 /* J,K;N|I,H;M */ &\
- namea##3 *+AR0(1), R1, R0 &|| nameb##3 *+AR1(1), R2 /* J,K;N|I,H;M */ &\
- namea##3 *+AR0(1), R0 &|| nameb##3 *+AR1(1), R2 /* J,K;N|I,H;M */ &\
- namea##3 R0, *+AR0(1), R0 &|| nameb##3 *+AR1(1), R0, R2 /* K,J,N|I,H;M */ &\
- namea##3 R0, *+AR0(1), R0 &|| nameb##3 *+AR1(1), R2 /* K,J,N|I,H;M */ &\
+ namea##3 *+AR0(1), *+AR1(1), R0 &|| nameb##3 R0, R1, R2 /* i;j;N|H;K;M */ &\
+ namea##3 *+AR0(1), *+AR1(1), R0 &|| nameb##3 R0, R2 /* i;j;N|H;K;M */ &\
+ namea##3 *+AR0(1), R0, R0 &|| nameb##3 R0, *+AR1(1), R2 /* j;K;N|H;i;M */ &\
+ namea##3 *+AR0(1), R0 &|| nameb##3 R0, *+AR1(1), R2 /* j;K;N|H;i;M */ &\
+ namea##3 R0, *+AR0(1), R0 &|| nameb##3 R0, *+AR1(1), R2 /* K;j;N|H;i;M */ &\
+ namea##3 R2, R1, R0 &|| nameb##3 *+AR0(1), *+AR1(1), R2 /* H;K;N|i;j;M */ &\
+ namea##3 R2, R0 &|| nameb##3 *+AR0(1), *+AR1(1), R2 /* H;K;N|i;j;M */ &\
+ namea##3 *+AR0(1), R1, R0 &|| nameb##3 *+AR1(1), R3, R2 /* j;K;N|i;H;M */ &\
+ namea##3 *+AR0(1), R0 &|| nameb##3 *+AR1(1), R3, R2 /* j;K;N|i;H;M */ &\
+ namea##3 *+AR0(1), R1, R0 &|| nameb##3 *+AR1(1), R2 /* j;K;N|i;H;M */ &\
+ namea##3 *+AR0(1), R0 &|| nameb##3 *+AR1(1), R2 /* j;K;N|i;H;M */ &\
+ namea##3 R0, *+AR0(1), R0 &|| nameb##3 *+AR1(1), R0, R2 /* K;j;N|i;H;M */ &\
+ namea##3 R0, *+AR0(1), R0 &|| nameb##3 *+AR1(1), R2 /* K;j;N|i;H;M */ &\
+ .endif &\
+ .ifdef TEST_ENH &\
+namea##3_##nameb##3_M_enh: &\
+ namea##3 R0, R0, R0 &|| nameb##3 R2, R2, R2 /* i;j;N|H;K;M */ &\
+ namea##3 R0, R0 &|| nameb##3 R2, R2, R2 /* i;j;N|H;K;M */ &\
+ namea##3 R0 &|| nameb##3 R2, R2, R2 /* i;j;N|H;K;M */ &\
+ namea##3 R0, R0 &|| nameb##3 R2, R2 /* i;j;N|H;K;M */ &\
+ namea##3 R0 &|| nameb##3 R2, R2 /* i;j;N|H;K;M */ &\
+ namea##3 R0 &|| nameb##3 R2 /* i;j;N|H;K;M */ &\
+ namea##3 AR0, AR0, R0 &|| nameb##3 R2, R2, R2 /* i;j;N|H;K;M */ &\
+ namea##3 AR0, R0, R0 &|| nameb##3 R0, AR0, R2 /* j;K;N|H;i;M */ &\
+ namea##3 R0, AR0, R0 &|| nameb##3 R0, AR0, R2 /* K;j;N|H;i;M */ &\
+ namea##3 R2, R1, R0 &|| nameb##3 AR0, AR1, R2 /* H;K;N|i;j;M */ &\
+ namea##3 AR0, R1, R0 &|| nameb##3 AR0, R3, R2 /* j;K;N|i;H;M */ &\
+ namea##3 R0, AR0, R0 &|| nameb##3 AR0, R0, R2 /* K;j;N|i;H;M */ &\
+ .endif &\
+ .ifdef level &\
nameb##_##namea##_M: &\
- nameb R0, R1, R2 &|| namea *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
- nameb R0, R2 &|| namea *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
- nameb R0, *+AR1(1), R2 &|| namea *+AR0(1), R0, R0 /* H,I,M|J,K;N */ &\
- nameb R0, *+AR1(1), R2 &|| namea *+AR0(1), R0 /* H,I,M|J,K;N */ &\
- nameb R0, *+AR1(1), R2 &|| namea R0, *+AR0(1), R0 /* H,I,M|K,J,N */ &\
- nameb *+AR0(1), *+AR1(1), R2 &|| namea R2, R1, R0 /* I,J,M|H,K;N */ &\
- nameb *+AR0(1), *+AR1(1), R2 &|| namea R2, R0 /* I,J,M|H,K;N */ &\
- nameb *+AR1(1), R3, R2 &|| namea *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
- nameb *+AR1(1), R3, R2 &|| namea *+AR0(1), R0 /* I,H;M|J,K;N */ &\
- nameb *+AR1(1), R2 &|| namea *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
- nameb *+AR1(1), R2 &|| namea *+AR0(1), R0 /* I,H;M|J,K;N */ &\
- nameb *+AR1(1), R0, R2 &|| namea R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
- nameb *+AR1(1), R2 &|| namea R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
-nameb##3_##namea##3_M: &\
- nameb##3 R0, R1, R2 &|| namea##3 *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
- nameb##3 R0, R2 &|| namea##3 *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
- nameb##3 R0, *+AR1(1), R2 &|| namea##3 *+AR0(1), R0, R0 /* H,I,M|J,K;N */ &\
- nameb##3 R0, *+AR1(1), R2 &|| namea##3 *+AR0(1), R0 /* H,I,M|J,K;N */ &\
- nameb##3 R0, *+AR1(1), R2 &|| namea##3 R0, *+AR0(1), R0 /* H,I,M|K,J,N */ &\
- nameb##3 *+AR0(1), *+AR1(1), R2 &|| namea##3 R2, R1, R0 /* I,J,M|H,K;N */ &\
- nameb##3 *+AR0(1), *+AR1(1), R2 &|| namea##3 R2, R0 /* I,J,M|H,K;N */ &\
- nameb##3 *+AR1(1), R3, R2 &|| namea##3 *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
- nameb##3 *+AR1(1), R3, R2 &|| namea##3 *+AR0(1), R0 /* I,H;M|J,K;N */ &\
- nameb##3 *+AR1(1), R2 &|| namea##3 *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
- nameb##3 *+AR1(1), R2 &|| namea##3 *+AR0(1), R0 /* I,H;M|J,K;N */ &\
- nameb##3 *+AR1(1), R0, R2 &|| namea##3 R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
- nameb##3 *+AR1(1), R2 &|| namea##3 R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
-nameb##_##namea##3_M: &\
- nameb R0, R1, R2 &|| namea##3 *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
- nameb R0, R2 &|| namea##3 *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
- nameb R0, *+AR1(1), R2 &|| namea##3 *+AR0(1), R0, R0 /* H,I,M|J,K;N */ &\
- nameb R0, *+AR1(1), R2 &|| namea##3 *+AR0(1), R0 /* H,I,M|J,K;N */ &\
- nameb R0, *+AR1(1), R2 &|| namea##3 R0, *+AR0(1), R0 /* H,I,M|K,J,N */ &\
- nameb *+AR0(1), *+AR1(1), R2 &|| namea##3 R2, R1, R0 /* I,J,M|H,K;N */ &\
- nameb *+AR0(1), *+AR1(1), R2 &|| namea##3 R2, R0 /* I,J,M|H,K;N */ &\
- nameb *+AR1(1), R3, R2 &|| namea##3 *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
- nameb *+AR1(1), R3, R2 &|| namea##3 *+AR0(1), R0 /* I,H;M|J,K;N */ &\
- nameb *+AR1(1), R2 &|| namea##3 *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
- nameb *+AR1(1), R2 &|| namea##3 *+AR0(1), R0 /* I,H;M|J,K;N */ &\
- nameb *+AR1(1), R0, R2 &|| namea##3 R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
- nameb *+AR1(1), R2 &|| namea##3 R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
+ nameb R0, R1, R2 &|| namea *+AR0(1), *+AR1(1), R0 /* H;K;M|i;j;N */ &\
+ nameb R0, R2 &|| namea *+AR0(1), *+AR1(1), R0 /* H;K;M|i;j;N */ &\
+ nameb R0, *+AR1(1), R2 &|| namea *+AR0(1), R0, R0 /* H;i;M|j;K;N */ &\
+ nameb R0, *+AR1(1), R2 &|| namea *+AR0(1), R0 /* H;i;M|j;K;N */ &\
+ nameb R0, *+AR1(1), R2 &|| namea R0, *+AR0(1), R0 /* H;i;M|K;j;N */ &\
+ nameb *+AR0(1), *+AR1(1), R2 &|| namea R2, R1, R0 /* i;j;M|H;K;N */ &\
+ nameb *+AR0(1), *+AR1(1), R2 &|| namea R2, R0 /* i;j;M|H;K;N */ &\
+ nameb *+AR1(1), R3, R2 &|| namea *+AR0(1), R1, R0 /* i;H;M|j;K;N */ &\
+ nameb *+AR1(1), R3, R2 &|| namea *+AR0(1), R0 /* i;H;M|j;K;N */ &\
+ nameb *+AR1(1), R2 &|| namea *+AR0(1), R1, R0 /* i;H;M|j;K;N */ &\
+ nameb *+AR1(1), R2 &|| namea *+AR0(1), R0 /* i;H;M|j;K;N */ &\
+ nameb *+AR1(1), R0, R2 &|| namea R0, *+AR0(1), R0 /* i;H;M|K;j;N */ &\
+ nameb *+AR1(1), R2 &|| namea R0, *+AR0(1), R0 /* i;H;M|K;j;N */ &\
+ .endif &\
+ .ifdef TEST_ENH &\
+nameb##_##namea##_M_enh: &\
+ nameb R2, R2, R2 &|| namea R0, R0, R0 /* H;K;M|i;j;N */ &\
+ nameb R2, R2, R2 &|| namea R0, R0 /* H;K;M|i;j;N */ &\
+ nameb R2, R2, R2 &|| namea R0 /* H;K;M|i;j;N */ &\
+ nameb R2, R2 &|| namea R0, R0 /* H;K;M|i;j;N */ &\
+ nameb R2, R2 &|| namea R0 /* H;K;M|i;j;N */ &\
+ nameb R2 &|| namea R0 /* H;K;M|i;j;N */ &\
+ nameb R2, R2, R2 &|| namea AR0, AR0, R0 /* H;K;M|i;j;N */ &\
+ nameb R0, AR0, R2 &|| namea AR0, R0, R0 /* H;i;M|j;K;N */ &\
+ nameb R0, AR0, R2 &|| namea R0, AR0, R0 /* H;i;M|K;j;N */ &\
+ nameb AR0, AR1, R2 &|| namea R2, R1, R0 /* i;j;M|H;K;N */ &\
+ nameb AR0, R3, R2 &|| namea AR0, R1, R0 /* i;H;M|j;K;N */ &\
+ nameb AR0, R0, R2 &|| namea R0, AR0, R0 /* i;H;M|K;j;N */ &\
+ .endif &\
+ .ifdef level &\
nameb##3_##namea##_M: &\
- nameb##3 R0, R1, R2 &|| namea *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
- nameb##3 R0, R2 &|| namea *+AR0(1), *+AR1(1), R0 /* H,K;M|I,J,N */ &\
- nameb##3 R0, *+AR1(1), R2 &|| namea *+AR0(1), R0, R0 /* H,I,M|J,K;N */ &\
- nameb##3 R0, *+AR1(1), R2 &|| namea *+AR0(1), R0 /* H,I,M|J,K;N */ &\
- nameb##3 R0, *+AR1(1), R2 &|| namea R0, *+AR0(1), R0 /* H,I,M|K,J,N */ &\
- nameb##3 *+AR0(1), *+AR1(1), R2 &|| namea R2, R1, R0 /* I,J,M|H,K;N */ &\
- nameb##3 *+AR0(1), *+AR1(1), R2 &|| namea R2, R0 /* I,J,M|H,K;N */ &\
- nameb##3 *+AR1(1), R3, R2 &|| namea *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
- nameb##3 *+AR1(1), R3, R2 &|| namea *+AR0(1), R0 /* I,H;M|J,K;N */ &\
- nameb##3 *+AR1(1), R2 &|| namea *+AR0(1), R1, R0 /* I,H;M|J,K;N */ &\
- nameb##3 *+AR1(1), R2 &|| namea *+AR0(1), R0 /* I,H;M|J,K;N */ &\
- nameb##3 *+AR1(1), R0, R2 &|| namea R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
- nameb##3 *+AR1(1), R2 &|| namea R0, *+AR0(1), R0 /* I,H;M|K,J,N */ &\
-
+ nameb##3 R0, R1, R2 &|| namea *+AR0(1), *+AR1(1), R0 /* H;K;M|i;j;N */ &\
+ nameb##3 R0, R2 &|| namea *+AR0(1), *+AR1(1), R0 /* H;K;M|i;j;N */ &\
+ nameb##3 R0, *+AR1(1), R2 &|| namea *+AR0(1), R0, R0 /* H;i;M|j;K;N */ &\
+ nameb##3 R0, *+AR1(1), R2 &|| namea *+AR0(1), R0 /* H;i;M|j;K;N */ &\
+ nameb##3 R0, *+AR1(1), R2 &|| namea R0, *+AR0(1), R0 /* H;i;M|K;j;N */ &\
+ nameb##3 *+AR0(1), *+AR1(1), R2 &|| namea R2, R1, R0 /* i;j;M|H;K;N */ &\
+ nameb##3 *+AR0(1), *+AR1(1), R2 &|| namea R2, R0 /* i;j;M|H;K;N */ &\
+ nameb##3 *+AR1(1), R3, R2 &|| namea *+AR0(1), R1, R0 /* i;H;M|j;K;N */ &\
+ nameb##3 *+AR1(1), R3, R2 &|| namea *+AR0(1), R0 /* i;H;M|j;K;N */ &\
+ nameb##3 *+AR1(1), R2 &|| namea *+AR0(1), R1, R0 /* i;H;M|j;K;N */ &\
+ nameb##3 *+AR1(1), R2 &|| namea *+AR0(1), R0 /* i;H;M|j;K;N */ &\
+ nameb##3 *+AR1(1), R0, R2 &|| namea R0, *+AR0(1), R0 /* i;H;M|K;j;N */ &\
+ nameb##3 *+AR1(1), R2 &|| namea R0, *+AR0(1), R0 /* i;H;M|K;j;N */ &\
+ .endif &\
+ .ifdef TEST_ENH &\
+nameb##3_##namea##_M_enh: &\
+ nameb##3 R2, R2, R2 &|| namea R0, R0, R0 /* H;K;M|i;j;N */ &\
+ nameb##3 R2, R2, R2 &|| namea R0, R0 /* H;K;M|i;j;N */ &\
+ nameb##3 R2, R2, R2 &|| namea R0 /* H;K;M|i;j;N */ &\
+ nameb##3 R2, R2 &|| namea R0, R0 /* H;K;M|i;j;N */ &\
+ nameb##3 R2, R2 &|| namea R0 /* H;K;M|i;j;N */ &\
+ nameb##3 R2 &|| namea R0 /* H;K;M|i;j;N */ &\
+ nameb##3 R2, R2, R2 &|| namea AR0, AR0, R0 /* H;K;M|i;j;N */ &\
+ nameb##3 R0, AR0, R2 &|| namea AR0, R0, R0 /* H;i;M|j;K;N */ &\
+ nameb##3 R0, AR0, R2 &|| namea R0, AR0, R0 /* H;i;M|K;j;N */ &\
+ nameb##3 AR0, AR1, R2 &|| namea R2, R1, R0 /* i;j;M|H;K;N */ &\
+ nameb##3 AR0, R3, R2 &|| namea AR0, R1, R0 /* i;H;M|j;K;N */ &\
+ nameb##3 AR0, R0, R2 &|| namea R0, AR0, R0 /* i;H;M|K;j;N */ &\
+ .endif &\
+ .ifdef level &\
+nameb##_##namea##3_M: &\
+ nameb R0, R1, R2 &|| namea##3 *+AR0(1), *+AR1(1), R0 /* H;K;M|i;j;N */ &\
+ nameb R0, R2 &|| namea##3 *+AR0(1), *+AR1(1), R0 /* H;K;M|i;j;N */ &\
+ nameb R0, *+AR1(1), R2 &|| namea##3 *+AR0(1), R0, R0 /* H;i;M|j;K;N */ &\
+ nameb R0, *+AR1(1), R2 &|| namea##3 *+AR0(1), R0 /* H;i;M|j;K;N */ &\
+ nameb R0, *+AR1(1), R2 &|| namea##3 R0, *+AR0(1), R0 /* H;i;M|K;j;N */ &\
+ nameb *+AR0(1), *+AR1(1), R2 &|| namea##3 R2, R1, R0 /* i;j;M|H;K;N */ &\
+ nameb *+AR0(1), *+AR1(1), R2 &|| namea##3 R2, R0 /* i;j;M|H;K;N */ &\
+ nameb *+AR1(1), R3, R2 &|| namea##3 *+AR0(1), R1, R0 /* i;H;M|j;K;N */ &\
+ nameb *+AR1(1), R3, R2 &|| namea##3 *+AR0(1), R0 /* i;H;M|j;K;N */ &\
+ nameb *+AR1(1), R2 &|| namea##3 *+AR0(1), R1, R0 /* i;H;M|j;K;N */ &\
+ nameb *+AR1(1), R2 &|| namea##3 *+AR0(1), R0 /* i;H;M|j;K;N */ &\
+ nameb *+AR1(1), R0, R2 &|| namea##3 R0, *+AR0(1), R0 /* i;H;M|K;j;N */ &\
+ nameb *+AR1(1), R2 &|| namea##3 R0, *+AR0(1), R0 /* i;H;M|K;j;N */ &\
+ .endif &\
+ .ifdef TEST_ENH &\
+nameb##_##namea##3_M_enh: &\
+ nameb R2, R2, R2 &|| namea##3 R0, R0, R0 /* H;K;M|i;j;N */ &\
+ nameb R2, R2, R2 &|| namea##3 R0, R0 /* H;K;M|i;j;N */ &\
+ nameb R2, R2, R2 &|| namea##3 R0 /* H;K;M|i;j;N */ &\
+ nameb R2, R2 &|| namea##3 R0, R0 /* H;K;M|i;j;N */ &\
+ nameb R2, R2 &|| namea##3 R0 /* H;K;M|i;j;N */ &\
+ nameb R2 &|| namea##3 R0 /* H;K;M|i;j;N */ &\
+ nameb R2, R2, R2 &|| namea##3 AR0, AR0, R0 /* H;K;M|i;j;N */ &\
+ nameb R0, AR0, R2 &|| namea##3 AR0, R0, R0 /* H;i;M|j;K;N */ &\
+ nameb R0, AR0, R2 &|| namea##3 R0, AR0, R0 /* H;i;M|K;j;N */ &\
+ nameb AR0, AR1, R2 &|| namea##3 R2, R1, R0 /* i;j;M|H;K;N */ &\
+ nameb AR0, R3, R2 &|| namea##3 AR0, R1, R0 /* i;H;M|j;K;N */ &\
+ nameb AR0, R0, R2 &|| namea##3 R0, AR0, R0 /* i;H;M|K;j;N */ &\
+ .endif &\
+ .ifdef level &\
+nameb##3_##namea##3_M: &\
+ nameb##3 R0, R1, R2 &|| namea##3 *+AR0(1), *+AR1(1), R0 /* H;K;M|i;j;N */ &\
+ nameb##3 R0, R2 &|| namea##3 *+AR0(1), *+AR1(1), R0 /* H;K;M|i;j;N */ &\
+ nameb##3 R0, *+AR1(1), R2 &|| namea##3 *+AR0(1), R0, R0 /* H;i;M|j;K;N */ &\
+ nameb##3 R0, *+AR1(1), R2 &|| namea##3 *+AR0(1), R0 /* H;i;M|j;K;N */ &\
+ nameb##3 R0, *+AR1(1), R2 &|| namea##3 R0, *+AR0(1), R0 /* H;i;M|K;j;N */ &\
+ nameb##3 *+AR0(1), *+AR1(1), R2 &|| namea##3 R2, R1, R0 /* i;j;M|H;K;N */ &\
+ nameb##3 *+AR0(1), *+AR1(1), R2 &|| namea##3 R2, R0 /* i;j;M|H;K;N */ &\
+ nameb##3 *+AR1(1), R3, R2 &|| namea##3 *+AR0(1), R1, R0 /* i;H;M|j;K;N */ &\
+ nameb##3 *+AR1(1), R3, R2 &|| namea##3 *+AR0(1), R0 /* i;H;M|j;K;N */ &\
+ nameb##3 *+AR1(1), R2 &|| namea##3 *+AR0(1), R1, R0 /* i;H;M|j;K;N */ &\
+ nameb##3 *+AR1(1), R2 &|| namea##3 *+AR0(1), R0 /* i;H;M|j;K;N */ &\
+ nameb##3 *+AR1(1), R0, R2 &|| namea##3 R0, *+AR0(1), R0 /* i;H;M|K;j;N */ &\
+ nameb##3 *+AR1(1), R2 &|| namea##3 R0, *+AR0(1), R0 /* i;H;M|K;j;N */ &\
+ .endif &\
+ .ifdef TEST_ENH &\
+nameb##3_##namea##3_M_enh: &\
+ nameb##3 R2, R2, R2 &|| namea##3 R0, R0, R0 /* H;K;M|i;j;N */ &\
+ nameb##3 R2, R2, R2 &|| namea##3 R0, R0 /* H;K;M|i;j;N */ &\
+ nameb##3 R2, R2, R2 &|| namea##3 R0 /* H;K;M|i;j;N */ &\
+ nameb##3 R2, R2 &|| namea##3 R0, R0 /* H;K;M|i;j;N */ &\
+ nameb##3 R2, R2 &|| namea##3 R0 /* H;K;M|i;j;N */ &\
+ nameb##3 R2 &|| namea##3 R0 /* H;K;M|i;j;N */ &\
+ nameb##3 R2, R2, R2 &|| namea##3 AR0, AR0, R0 /* H;K;M|i;j;N */ &\
+ nameb##3 R0, AR0, R2 &|| namea##3 AR0, R0, R0 /* H;i;M|j;K;N */ &\
+ nameb##3 R0, AR0, R2 &|| namea##3 R0, AR0, R0 /* H;i;M|K;j;N */ &\
+ nameb##3 AR0, AR1, R2 &|| namea##3 R2, R1, R0 /* i;j;M|H;K;N */ &\
+ nameb##3 AR0, R3, R2 &|| namea##3 AR0, R1, R0 /* i;H;M|j;K;N */ &\
+ nameb##3 AR0, R0, R2 &|| namea##3 R0, AR0, R0 /* i;H;M|K;j;N */ &\
+ .endif
/* P: General 2-operand operation with parallell store
Syntax: <ia> src2, dst1 || <ib> src3, dst2
- src2 = Indirect 0,1,IR0,IR1 (I)
+ src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
dst1 = Register 0-7 (L)
src3 = Register 0-7 (H)
dst2 = Indirect 0,1,IR0,IR1 (J)
TOIEEE||STF
Alias: a||b, b||a
*/
-#define P_CLASS(namea, nameb) \
+#define P_CLASS(namea, nameb, level) \
+ .ifdef level &\
namea##_##nameb##_P: &\
- namea *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* I,L|H,J */ &\
- nameb R1, *+AR1(1) &|| namea *+AR0(1), R0 /* H,J|I,L */
-
+ namea *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* i;L|H,J */ &\
+ nameb R1, *+AR1(1) &|| namea *+AR0(1), R0 /* H,J|i;L */ &\
+ .endif &\
+ .ifdef TEST_ENH &\
+namea##_##nameb##_P_enh: &\
+ namea R0, R0 &|| nameb R1, *+AR1(1) /* i;L|H,J */ &\
+ namea R0 &|| nameb R1, *+AR1(1) /* i;L|H,J */ &\
+ nameb R1, *+AR1(1) &|| namea R0, R0 /* H,J|i;L */ &\
+ nameb R1, *+AR1(1) &|| namea R0 /* H,J|i;L */ &\
+ .endif
+
/* Q: General 3-operand operation with parallell store
Syntax: <ia> src1, src2, dst1 || <ib> src3, dst2
src1 = Register 0-7 (K)
- src2 = Indirect 0,1,IR0,IR1 (I)
+ src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
dst1 = Register 0-7 (L)
src3 = Register 0-7 (H)
dst2 = Indirect 0,1,IR0,IR1 (J)
Instr: 4/0 - ASH3||STI, LSH3||STI, SUBF3||STF, SUBI3||STI
Alias: a||b, b||a, a3||b, b||a3
*/
-#define Q_CLASS(namea, nameb) \
+#define Q_CLASS(namea, nameb, level) \
+ .ifdef level &\
namea##_##nameb##_Q: &\
- namea R0, *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* K,I,L|H,J */ &\
- nameb R1, *+AR1(1) &|| namea R0, *+AR0(1), R0 /* H,J|K,I,L */ &\
+ namea R0, *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* K,i;L|H,J */ &\
+ nameb R1, *+AR1(1) &|| namea R0, *+AR0(1), R0 /* H,J|K,i;L */ &\
+ .endif &\
+ .ifdef TEST_ENH &\
+namea##_##nameb##_Q_enh: &\
+ namea R0, R0, R0 &|| nameb R1, *+AR1(1) /* K,i;L|H,J */ &\
+ namea R0, R0 &|| nameb R1, *+AR1(1) /* K,i;L|H,J */ &\
+ nameb R1, *+AR1(1) &|| namea R0, R0, R0 /* H,J|K,i;L */ &\
+ nameb R1, *+AR1(1) &|| namea R0, R0 /* H,J|K,i;L */ &\
+ .endif &\
+ .ifdef level &\
namea##3_##nameb##_Q: &\
- namea##3 R0, *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* K,I,L|H,J */ &\
- nameb R1, *+AR1(1) &|| namea##3 R0, *+AR0(1), R0 /* H,J|K,I,L */
+ namea##3 R0, *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* K,i;L|H,J */ &\
+ nameb R1, *+AR1(1) &|| namea##3 R0, *+AR0(1), R0 /* H,J|K,i;L */ &\
+ .endif &\
+ .ifdef TEST_ENH &\
+namea##3_##nameb##_Q_enh: &\
+ namea##3 R0, R0, R0 &|| nameb R1, *+AR1(1) /* K,i;L|H,J */ &\
+ namea##3 R0, R0 &|| nameb R1, *+AR1(1) /* K,i;L|H,J */ &\
+ nameb R1, *+AR1(1) &|| namea##3 R0, R0, R0 /* H,J|K,i;L */ &\
+ nameb R1, *+AR1(1) &|| namea##3 R0, R0 /* H,J|K,i;L */ &\
+ .endif
/* QC: General commutative 3-operand operation with parallell store
Syntax: <ia> src2, src1, dst1 || <ib> src3, dst2
<ia> src1, src2, dst1 || <ib> src3, dst2 - Manual
src1 = Register 0-7 (K)
- src2 = Indirect 0,1,IR0,IR1 (I)
+ src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
dst1 = Register 0-7 (L)
src3 = Register 0-7 (H)
dst2 = Indirect 0,1,IR0,IR1 (J)
OR3||STI, XOR3||STI
Alias: a||b, b||a, a3||b, b||a3
*/
-#define QC_CLASS(namea, nameb) \
+#define QC_CLASS(namea, nameb, level) \
+ .ifdef level &\
namea##_##nameb##_QC: &\
- namea *+AR0(1), R1, R0 &|| nameb R1, *+AR1(1) /* I,K;L|H,J */ &\
- namea *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* I,K;L|H,J */ &\
- namea R0, *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* K,I,L|H,J */ &\
- nameb R1, *+AR1(1) &|| namea *+AR0(1), R1, R0 /* H,J|I,K;L */ &\
- nameb R1, *+AR1(1) &|| namea *+AR0(1), R0 /* H,J|I,K;L */ &\
- nameb R1, *+AR1(1) &|| namea R0, *+AR0(1), R0 /* H,J|K,I,L */ &\
+ namea *+AR0(1), R1, R0 &|| nameb R1, *+AR1(1) /* i;K;L|H,J */ &\
+ namea *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* i;K;L|H,J */ &\
+ namea R0, *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* K;i;L|H,J */ &\
+ nameb R1, *+AR1(1) &|| namea *+AR0(1), R1, R0 /* H,J|i;K;L */ &\
+ nameb R1, *+AR1(1) &|| namea *+AR0(1), R0 /* H,J|i;K;L */ &\
+ nameb R1, *+AR1(1) &|| namea R0, *+AR0(1), R0 /* H,J|K;i;L */ &\
+ .endif &\
+ .ifdef TEST_ENH &\
+namea##_##nameb##_QC_enh: &\
+ namea AR0, R1, R0 &|| nameb R1, *+AR1(1) /* i;K;L|H,J */ &\
+ namea R2, R1, R0 &|| nameb R1, *+AR1(1) /* i;K;L|H,J */ &\
+ namea R1, R0 &|| nameb R1, *+AR1(1) /* i;K;L|H,J */ &\
+ namea R0 &|| nameb R1, *+AR1(1) /* i;K;L|H,J */ &\
+ namea R0, AR0, R0 &|| nameb R1, *+AR1(1) /* K;i;L|H,J */ &\
+ nameb R1, *+AR1(1) &|| namea AR0, R1, R0 /* H,J|i;K;L */ &\
+ nameb R1, *+AR1(1) &|| namea R2, R1, R0 /* H,J|i;K;L */ &\
+ nameb R1, *+AR1(1) &|| namea R1, R0 /* H,J|i;K;L */ &\
+ nameb R1, *+AR1(1) &|| namea R0 /* H,J|i;K;L */ &\
+ nameb R1, *+AR1(1) &|| namea R0, AR0, R0 /* H,J|K;i;L */ &\
+ .endif &\
+ .ifdef level &\
namea##3_##nameb##_QC: &\
- namea##3 *+AR0(1), R1, R0 &|| nameb R1, *+AR1(1) /* I,K;L|H,J */ &\
- namea##3 *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* I,K;L|H,J */ &\
- namea##3 R0, *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* K,I,L|H,J */ &\
- nameb R1, *+AR1(1) &|| namea##3 *+AR0(1), R1, R0 /* H,J|I,K;L */ &\
- nameb R1, *+AR1(1) &|| namea##3 *+AR0(1), R0 /* H,J|I,K;L */ &\
- nameb R1, *+AR1(1) &|| namea##3 R0, *+AR0(1), R0 /* H,J|K,I,L */
+ namea##3 *+AR0(1), R1, R0 &|| nameb R1, *+AR1(1) /* i;K;L|H,J */ &\
+ namea##3 *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* i;K;L|H,J */ &\
+ namea##3 R0, *+AR0(1), R0 &|| nameb R1, *+AR1(1) /* K;i;L|H,J */ &\
+ nameb R1, *+AR1(1) &|| namea##3 *+AR0(1), R1, R0 /* H,J|i;K;L */ &\
+ nameb R1, *+AR1(1) &|| namea##3 *+AR0(1), R0 /* H,J|i;K;L */ &\
+ nameb R1, *+AR1(1) &|| namea##3 R0, *+AR0(1), R0 /* H,J|K;i;L */ &\
+ .endif &\
+ .ifdef TEST_ENH &\
+namea##3_##nameb##_QC_enh: &\
+ namea##3 AR0, R1, R0 &|| nameb R1, *+AR1(1) /* i;K;L|H,J */ &\
+ namea##3 R2, R1, R0 &|| nameb R1, *+AR1(1) /* i;K;L|H,J */ &\
+ namea##3 R1, R0 &|| nameb R1, *+AR1(1) /* i;K;L|H,J */ &\
+ namea##3 R0 &|| nameb R1, *+AR1(1) /* i;K;L|H,J */ &\
+ namea##3 R0, AR0, R0 &|| nameb R1, *+AR1(1) /* K;i;L|H,J */ &\
+ nameb R1, *+AR1(1) &|| namea##3 AR0, R1, R0 /* H,J|i;K;L */ &\
+ nameb R1, *+AR1(1) &|| namea##3 R2, R1, R0 /* H,J|i;K;L */ &\
+ nameb R1, *+AR1(1) &|| namea##3 R1, R0 /* H,J|i;K;L */ &\
+ nameb R1, *+AR1(1) &|| namea##3 R0 /* H,J|i;K;L */ &\
+ nameb R1, *+AR1(1) &|| namea##3 R0, AR0, R0 /* H,J|K;i;L */ &\
+ .endif
/* R: General register integer operation
dst = Register (R)
Instr: 6/0 - POP, PUSH, ROL, ROLC, ROR, RORC
*/
-#define R_CLASS(name) \
-name##_R: &\
- name AR0 /* R */
+#define R_CLASS(name, level) \
+ .ifdef level &\
+name##_R: &\
+ name AR0 /* R */ &\
+ .endif
/* RF: General register float operation
Syntax: <i> dst
- dst = Register 0-11 (R)
+ dst = Register 0-11 (r)
Instr: 2/0 - POPF, PUSHF
*/
-#define RF_CLASS(name) \
-name##_RF: &\
- name F0 /* R */
+#define RF_CLASS(name, level) \
+ .ifdef level &\
+name##_RF: &\
+ name F0 /* r */ &\
+ .endif
/* S: General 3-operand float operation
Syntax: <i> src2, src1, dst
- src2 = Register 0-11 (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
- src1 = Register 0-11 (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
- dst = Register 0-11 (R)
+ src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
+ src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
+ dst = Register 0-11 (r)
Instr: 1/0 - SUBF3
Alias: i, i3
*/
-#define S_CLASS(name) \
+#define S_CLASS(name, level) \
+ .ifdef level &\
name##_S: &\
- name R2, R1, R0 /* E,G;R */ &\
- name R1, R0 /* E,G;R */ &\
- name R1, *+AR0(1), R0 /* E,J,R */ &\
- name *+AR0(1), R1, R0 /* I,G;R */ &\
- name *+AR0(1), R0 /* I,G;R */ &\
- name *+AR0(1), *+AR1(1), R0 /* I,J,R */ &\
+ name R2, R1, R0 /* e,g;r */ &\
+ name R1, R0 /* e,g;r */ &\
+ name R1, *+AR0(1), R0 /* e,J,r */ &\
+ name *+AR0(1), R1, R0 /* I,g;r */ &\
+ name *+AR0(1), R0 /* I,g;r */ &\
+ name *+AR0(1), *+AR1(1), R0 /* I,J,r */ &\
+ .endif &\
.ifdef TEST_C4X &\
- name *+AR0(5), R1, R0 /* C,G;R */ &\
- name *+AR0(5), R0 /* C,G;R */ &\
- name *+AR0(5), *+AR1(5), R0 /* C,O,R */ &\
+name##_S_c4x: &\
+ name *+AR0(5), R1, R0 /* C,g;r */ &\
+ name *+AR0(5), R0 /* C,g;r */ &\
+ name *+AR0(5), *+AR1(5), R0 /* C,O,r */ &\
.endif &\
+ .ifdef level &\
name##3_S: &\
- name##3 R2, R1, R0 /* E,G;R */ &\
- name##3 R1, R0 /* E,G;R */ &\
- name##3 R1, *+AR0(1), R0 /* E,J,R */ &\
- name##3 *+AR0(1), R1, R0 /* I,G;R */ &\
- name##3 *+AR0(1), R0 /* I,G;R */ &\
- name##3 *+AR0(1), *+AR1(1), R0 /* I,J,R */ &\
+ name##3 R2, R1, R0 /* e,g;r */ &\
+ name##3 R1, R0 /* e,g;r */ &\
+ name##3 R1, *+AR0(1), R0 /* e,J,r */ &\
+ name##3 *+AR0(1), R1, R0 /* I,g;r */ &\
+ name##3 *+AR0(1), R0 /* I,g;r */ &\
+ name##3 *+AR0(1), *+AR1(1), R0 /* I,J,r */ &\
+ .endif &\
.ifdef TEST_C4X &\
- name##3 *+AR0(5), R1, R0 /* C,G;R */ &\
- name##3 *+AR0(5), R0 /* C,G;R */ &\
- name##3 *+AR0(5), *+AR1(5), R0 /* C,O,R */ &\
+name##3_S_c4x: &\
+ name##3 *+AR0(5), R1, R0 /* C,g;r */ &\
+ name##3 *+AR0(5), R0 /* C,g;r */ &\
+ name##3 *+AR0(5), *+AR1(5), R0 /* C,O,r */ &\
.endif
/* SC: General commutative 3-operand float operation
Syntax: <i> src2, src1, dst - Manual
<i> src1, src2, dst
- src2 = Register 0-11 (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
- src1 = Register 0-11 (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
- dst = Register 0-11 (R)
+ src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
+ src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
+ dst = Register 0-11 (r)
Instr: 2/0 - ADDF3, MPYF3
Alias: i, i3
*/
-#define SC_CLASS(name) \
+#define SC_CLASS(name, level) \
+ .ifdef level &\
name##_SC: &\
- name R2, R1, R0 /* E,G;R */ &\
- name R1, R0 /* E,G;R */ &\
- name R1, *+AR0(1), R0 /* E,J,R */ &\
- name *+AR0(1), R1, R0 /* I,G;R */ &\
- name *+AR0(1), R0 /* I,G;R */ &\
- name *+AR0(1), *+AR1(1), R0 /* I,J,R */ &\
+ name R2, R1, R0 /* e,g;r */ &\
+ name R1, R0 /* e,g;r */ &\
+ name R1, *+AR0(1), R0 /* e,J,r */ &\
+ name *+AR0(1), R1, R0 /* I,g;r */ &\
+ name *+AR0(1), R0 /* I,g;r */ &\
+ name *+AR0(1), *+AR1(1), R0 /* I,J,r */ &\
+ .endif &\
.ifdef TEST_C4X &\
- name *+AR0(5), R1, R0 /* C,G;R */ &\
- name *+AR0(5), R0 /* C,G;R */ &\
- name R1, *+AR0(5), R0 /* G,C,R */ &\
- name *+AR0(5), *+AR1(5), R0 /* C,O,R */ &\
+name##_SC_c4x: &\
+ name *+AR0(5), R1, R0 /* C,g;r */ &\
+ name *+AR0(5), R0 /* C,g;r */ &\
+ name R1, *+AR0(5), R0 /* g,C,r */ &\
+ name *+AR0(5), *+AR1(5), R0 /* C,O,r */ &\
.endif &\
+ .ifdef level &\
name##3_SC: &\
- name##3 R2, R1, R0 /* E,G;R */ &\
- name##3 R1, R0 /* E,G;R */ &\
- name##3 R1, *+AR0(1), R0 /* E,J,R */ &\
- name##3 *+AR0(1), R1, R0 /* I,G;R */ &\
- name##3 *+AR0(1), R0 /* I,G;R */ &\
- name##3 *+AR0(1), *+AR1(1), R0 /* I,J,R */ &\
+ name##3 R2, R1, R0 /* e,g;r */ &\
+ name##3 R1, R0 /* e,g;r */ &\
+ name##3 R1, *+AR0(1), R0 /* e,J,r */ &\
+ name##3 *+AR0(1), R1, R0 /* I,g;r */ &\
+ name##3 *+AR0(1), R0 /* I,g;r */ &\
+ name##3 *+AR0(1), *+AR1(1), R0 /* I,J,r */ &\
+ .endif &\
.ifdef TEST_C4X &\
- name##3 *+AR0(5), R1, R0 /* C,G;R */ &\
- name##3 *+AR0(5), R0 /* C,G;R */ &\
- name##3 R1, *+AR0(5), R0 /* G,C,R */ &\
- name##3 *+AR0(5), *+AR1(5), R0 /* C,O,R */ &\
+name##3_SC_c4x: &\
+ name##3 *+AR0(5), R1, R0 /* C,g;r */ &\
+ name##3 *+AR0(5), R0 /* C,g;r */ &\
+ name##3 R1, *+AR0(5), R0 /* g,C,r */ &\
+ name##3 *+AR0(5), *+AR1(5), R0 /* C,O,r */ &\
.endif
/* S2: General 3-operand float operation with 2 args
Syntax: <i> src2, src1
- src2 = Register 0-11 (E), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
- src1 = Register 0-11 (G), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
+ src2 = Register 0-11 (e), Indirect 0,1,IR0,IR1 (I), C4x T2: Indirect (C)
+ src1 = Register 0-11 (g), Indirect 0,1,IR0,IR1 (J), C4x T2: Indirect (O)
Instr: 1/0 - CMPF3
Alias: i, i3
*/
-#define S2_CLASS(name) \
+#define S2_CLASS(name, level) \
+ .ifdef level &\
name##_S2: &\
- name R2, R1 /* E,G */ &\
- name R1, *+AR0(1) /* E,J */ &\
- name *+AR0(1), R1 /* I,G */ &\
+ name R2, R1 /* e,g */ &\
+ name R1, *+AR0(1) /* e,J */ &\
+ name *+AR0(1), R1 /* I,g */ &\
name *+AR0(1), *+AR1(1) /* I,J */ &\
+ .endif &\
.ifdef TEST_C4X &\
- name *+AR0(5), R1 /* C,G */ &\
+name##_S2_c4x: &\
+ name *+AR0(5), R1 /* C,g */ &\
name *+AR0(5), *+AR1(5) /* C,O */ &\
.endif &\
+ .ifdef level &\
name##3_S2: &\
- name##3 R2, R1 /* E,G */ &\
- name##3 R1, *+AR0(1) /* E,J */ &\
- name##3 *+AR0(1), R1 /* I,G */ &\
+ name##3 R2, R1 /* e,g */ &\
+ name##3 R1, *+AR0(1) /* e,J */ &\
+ name##3 *+AR0(1), R1 /* I,g */ &\
name##3 *+AR0(1), *+AR1(1) /* I,J */ &\
+ .endif &\
.ifdef TEST_C4X &\
- name##3 *+AR0(5), R1 /* C,G */ &\
+name##3_S2_c4x: &\
+ name##3 *+AR0(5), R1 /* C,g */ &\
name##3 *+AR0(5), *+AR1(5) /* C,O */ &\
.endif
Instr: 5/0 - ANDN3, ASH3, LSH3, SUBB3, SUBI3
Alias: i, i3
*/
-#define T_CLASS(name) \
+#define T_CLASS(name, level) \
+ .ifdef level &\
name##_T: &\
name AR2, AR1, AR0 /* E,G;R */ &\
name AR1, AR0 /* E,G;R */ &\
name *+AR0(1), AR1, AR0 /* I,G;R */ &\
name *+AR0(1), AR0 /* I,G;R */ &\
name *+AR1(1), *+AR0(1), AR0 /* I,J,R */ &\
+ .endif &\
.ifdef TEST_C4X &\
- name 5, AR1, AR0 /* W,G;R */ &\
- name 5, AR0 /* W,G;R */ &\
+name##_T_sc: &\
+ name -5, AR1, AR0 /* W,G;R */ &\
+ name -5, AR0 /* W,G;R */ &\
name *+AR0(5), AR1, AR0 /* C,G;R */ &\
name *+AR0(5), AR0 /* C,G;R */ &\
- name 5, *+AR0(5), AR0 /* W,O,R */ &\
+ name -5, *+AR0(5), AR0 /* W,O,R */ &\
name *+AR0(5), *+AR1(5), AR0 /* C,O,R */ &\
.endif &\
+ .ifdef level &\
name##3_T: &\
name##3 AR2, AR1, AR0 /* E,G;R */ &\
name##3 AR1, AR0 /* E,G;R */ &\
name##3 *+AR0(1), AR1, AR0 /* I,G;R */ &\
name##3 *+AR0(1), AR0 /* I,G;R */ &\
name##3 *+AR1(1), *+AR0(1), AR0 /* I,J,R */ &\
+ .endif &\
.ifdef TEST_C4X &\
+name##3_T_sc: &\
name##3 -5, AR1, AR0 /* W,G;R */ &\
name##3 -5, AR0 /* W,G;R */ &\
name##3 *+AR0(5), AR1, AR0 /* C,G;R */ &\
Instr: 6/2 - ADDC3, ADDI3, AND3, MPYI3, OR3, XOR3, C4x: MPYSHI, MPYUHI
Alias: i, i3
*/
-#define TC_CLASS(name) \
+#define TC_CLASS(name, level) \
+ .ifdef level &\
name##_TC: &\
name AR2, AR1, AR0 /* E,G;R */ &\
name AR1, AR0 /* E,G;R */ &\
name *+AR0(1), AR1, AR0 /* I,G;R */ &\
name *+AR0(1), AR0 /* I,G;R */ &\
name *+AR1(1), *+AR0(1), AR0 /* I,J,R */ &\
+ .endif &\
.ifdef TEST_C4X &\
- name 5, AR1, AR0 /* W,G;R */ &\
- name 5, AR0 /* W,G;R */ &\
+name##_TC_c4x: &\
+ name -5, AR1, AR0 /* W,G;R */ &\
+ name -5, AR0 /* W,G;R */ &\
name AR1, -5, AR0 /* G,W,R */ &\
name *+AR0(5), AR1, AR0 /* C,G;R */ &\
name *+AR0(5), AR0 /* C,G;R */ &\
name AR1, *+AR0(5), AR0 /* G,C,R */ &\
- name 5, *+AR0(5), AR0 /* W,O,R */ &\
+ name -5, *+AR0(5), AR0 /* W,O,R */ &\
name *+AR0(5), -5, AR0 /* O,W,R */ &\
name *+AR0(5), *+AR1(5), AR0 /* C,O,R */ &\
.endif &\
+ .ifdef level &\
name##3_TC: &\
name##3 AR2, AR1, AR0 /* E,G;R */ &\
name##3 AR1, AR0 /* E,G;R */ &\
name##3 *+AR0(1), AR1, AR0 /* I,G;R */ &\
name##3 *+AR0(1), AR0 /* I,G;R */ &\
name##3 *+AR1(1), *+AR0(1), AR0 /* I,J,R */ &\
+ .endif &\
.ifdef TEST_C4X &\
+name##3_TC_c4x: &\
name##3 -5, AR1, AR0 /* W,G;R */ &\
name##3 -5, AR0 /* W,G;R */ &\
name##3 AR1, -5, AR0 /* G,W,R */ &\
Instr: 1/0 - CMPI3
Alias: i, i3
*/
-#define T2_CLASS(name) \
+#define T2_CLASS(name, level) \
+ .ifdef level &\
name##_T2: &\
name AR2, AR1 /* E,G */ &\
name AR1, *+AR0(1) /* E,J */ &\
name *+AR0(1), AR1 /* I,G */ &\
name *+AR1(1), *+AR0(1) /* I,J */ &\
+ .endif &\
.ifdef TEST_C4X &\
+name##_T2_c4x: &\
name -5, AR1 /* W,G */ &\
name *+AR0(5), AR1 /* C,G */ &\
name -5, *+AR0(5) /* W,O */ &\
name *+AR0(5), *+AR1(5) /* C,O */ &\
.endif &\
+ .ifdef level &\
name##3_T2: &\
name##3 AR2, AR1 /* E,G */ &\
name##3 AR1, *+AR0(1) /* E,J */ &\
name##3 *+AR0(1), AR1 /* I,G */ &\
name##3 *+AR1(1), *+AR0(1) /* I,J */ &\
+ .endif &\
.ifdef TEST_C4X &\
+name##3_T2_c4x: &\
name##3 -5, AR1 /* W,G */ &\
name##3 *+AR0(5), AR1 /* C,G */ &\
name##3 -5, *+AR0(5) /* W,O */ &\
Instr: 1/0 - TSTB3
Alias: i, i3
*/
-#define T2C_CLASS(name) \
+#define T2C_CLASS(name, level) \
+ .ifdef level &\
name##_T2C: &\
name AR2, AR1 /* E,G */ &\
name AR1, *+AR0(1) /* E,J */ &\
name *+AR0(1), AR1 /* I,G */ &\
name *+AR1(1), *+AR0(1) /* I,J */ &\
+ .endif &\
.ifdef TEST_C4X &\
- name 5, AR1 /* W,G */ &\
+name##_T2C_c4x: &\
+ name -5, AR1 /* W,G */ &\
name AR1, -5 /* G,W */ &\
name *+AR0(5), AR1 /* C,G */ &\
name AR1, *+AR0(5) /* G,C */ &\
- name 5, *+AR0(5) /* W,O */ &\
+ name -5, *+AR0(5) /* W,O */ &\
name *+AR0(5), -5 /* O,W */ &\
name *+AR0(5), *+AR1(5) /* C,O */ &\
.endif &\
+ .ifdef level &\
name##3_T2C: &\
name##3 AR2, AR1 /* E,G */ &\
name##3 AR1, *+AR0(1) /* E,J */ &\
name##3 *+AR0(1), AR1 /* I,G */ &\
name##3 *+AR1(1), *+AR0(1) /* I,J */ &\
+ .endif &\
.ifdef TEST_C4X &\
+name##3_T2C_c4x: &\
name##3 -5, AR1 /* W,G */ &\
name##3 AR1, -5 /* G,W */ &\
name##3 *+AR0(5), AR1 /* C,G */ &\
;;;
;;; To rebuild this file you must use
;;; ./rebuild.sh
+;;;
+;;; These definitions are used within this file:
+;;; TEST_C3X Enables testing of c3x opcodes
+;;; TEST_C4X Enables testing of c4x opcodes
+;;; TEST_ENH Enable testing of enhanced opcodes
+;;; TEST_IDLE2 Enable testing of IDLE2 command
+;;; TEST_LPWR Enable testing of LOPOWER commands
;;;
-
-
-
-
-
+
-
+
.text
-start: absf_B: & absf R1, R0 & absf R0 & absf @start, R0 & absf *+AR0(5), R0 & absf 3.5, R0
- absf_stf_P: & absf *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| absf *+AR0(1), R0
- absi_A: & absi AR1, AR0 & absi AR0 & absi @start, AR0 & absi *+AR0(5), AR0 & absi -5, AR0
- absi_sti_P: & absi *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| absi *+AR0(1), R0
- addc_A: & addc AR1, AR0 & addc AR0 & addc @start, AR0 & addc *+AR0(5), AR0 & addc -5, AR0
- addc_TC: & addc AR2, AR1, AR0 & addc AR1, AR0 & addc AR1, *+AR0(1), AR0 & addc *+AR0(1), AR1, AR0 & addc *+AR0(1), AR0 & addc *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & addc 5, AR1, AR0 & addc 5, AR0 & addc AR1, -5, AR0 & addc *+AR0(5), AR1, AR0 & addc *+AR0(5), AR0 & addc AR1, *+AR0(5), AR0 & addc 5, *+AR0(5), AR0 & addc *+AR0(5), -5, AR0 & addc *+AR0(5), *+AR1(5), AR0 & .endif & addc3_TC: & addc3 AR2, AR1, AR0 & addc3 AR1, AR0 & addc3 AR1, *+AR0(1), AR0 & addc3 *+AR0(1), AR1, AR0 & addc3 *+AR0(1), AR0 & addc3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & addc3 -5, AR1, AR0 & addc3 -5, AR0 & addc3 AR1, -5, AR0 & addc3 *+AR0(5), AR1, AR0 & addc3 *+AR0(5), AR0 & addc3 AR1, *+AR0(5), AR0 & addc3 -5, *+AR0(5), AR0 & addc3 *+AR0(5), -5, AR0 & addc3 *+AR0(5), *+AR1(5), AR0 & .endif
- addf_B: & addf R1, R0 & addf R0 & addf @start, R0 & addf *+AR0(5), R0 & addf 3.5, R0
- addf_SC: & addf R2, R1, R0 & addf R1, R0 & addf R1, *+AR0(1), R0 & addf *+AR0(1), R1, R0 & addf *+AR0(1), R0 & addf *+AR0(1), *+AR1(1), R0 & .ifdef TEST_C4X & addf *+AR0(5), R1, R0 & addf *+AR0(5), R0 & addf R1, *+AR0(5), R0 & addf *+AR0(5), *+AR1(5), R0 & .endif & addf3_SC: & addf3 R2, R1, R0 & addf3 R1, R0 & addf3 R1, *+AR0(1), R0 & addf3 *+AR0(1), R1, R0 & addf3 *+AR0(1), R0 & addf3 *+AR0(1), *+AR1(1), R0 & .ifdef TEST_C4X & addf3 *+AR0(5), R1, R0 & addf3 *+AR0(5), R0 & addf3 R1, *+AR0(5), R0 & addf3 *+AR0(5), *+AR1(5), R0 & .endif
- addf_stf_QC: & addf *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & addf *+AR0(1), R0 &|| stf R1, *+AR1(1) & addf R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| addf *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| addf *+AR0(1), R0 & stf R1, *+AR1(1) &|| addf R0, *+AR0(1), R0 & addf3_stf_QC: & addf3 *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & addf3 *+AR0(1), R0 &|| stf R1, *+AR1(1) & addf3 R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| addf3 *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| addf3 *+AR0(1), R0 & stf R1, *+AR1(1) &|| addf3 R0, *+AR0(1), R0
- addi_A: & addi AR1, AR0 & addi AR0 & addi @start, AR0 & addi *+AR0(5), AR0 & addi -5, AR0
- addi_TC: & addi AR2, AR1, AR0 & addi AR1, AR0 & addi AR1, *+AR0(1), AR0 & addi *+AR0(1), AR1, AR0 & addi *+AR0(1), AR0 & addi *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & addi 5, AR1, AR0 & addi 5, AR0 & addi AR1, -5, AR0 & addi *+AR0(5), AR1, AR0 & addi *+AR0(5), AR0 & addi AR1, *+AR0(5), AR0 & addi 5, *+AR0(5), AR0 & addi *+AR0(5), -5, AR0 & addi *+AR0(5), *+AR1(5), AR0 & .endif & addi3_TC: & addi3 AR2, AR1, AR0 & addi3 AR1, AR0 & addi3 AR1, *+AR0(1), AR0 & addi3 *+AR0(1), AR1, AR0 & addi3 *+AR0(1), AR0 & addi3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & addi3 -5, AR1, AR0 & addi3 -5, AR0 & addi3 AR1, -5, AR0 & addi3 *+AR0(5), AR1, AR0 & addi3 *+AR0(5), AR0 & addi3 AR1, *+AR0(5), AR0 & addi3 -5, *+AR0(5), AR0 & addi3 *+AR0(5), -5, AR0 & addi3 *+AR0(5), *+AR1(5), AR0 & .endif
- addi_sti_QC: & addi *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & addi *+AR0(1), R0 &|| sti R1, *+AR1(1) & addi R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| addi *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| addi *+AR0(1), R0 & sti R1, *+AR1(1) &|| addi R0, *+AR0(1), R0 & addi3_sti_QC: & addi3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & addi3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & addi3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| addi3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| addi3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| addi3 R0, *+AR0(1), R0
- and_AU: & and AR1, AR0 & and AR0 & and @start, AR0 & and *+AR0(5), AR0 & and 5, AR0
- and_TC: & and AR2, AR1, AR0 & and AR1, AR0 & and AR1, *+AR0(1), AR0 & and *+AR0(1), AR1, AR0 & and *+AR0(1), AR0 & and *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & and 5, AR1, AR0 & and 5, AR0 & and AR1, -5, AR0 & and *+AR0(5), AR1, AR0 & and *+AR0(5), AR0 & and AR1, *+AR0(5), AR0 & and 5, *+AR0(5), AR0 & and *+AR0(5), -5, AR0 & and *+AR0(5), *+AR1(5), AR0 & .endif & and3_TC: & and3 AR2, AR1, AR0 & and3 AR1, AR0 & and3 AR1, *+AR0(1), AR0 & and3 *+AR0(1), AR1, AR0 & and3 *+AR0(1), AR0 & and3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & and3 -5, AR1, AR0 & and3 -5, AR0 & and3 AR1, -5, AR0 & and3 *+AR0(5), AR1, AR0 & and3 *+AR0(5), AR0 & and3 AR1, *+AR0(5), AR0 & and3 -5, *+AR0(5), AR0 & and3 *+AR0(5), -5, AR0 & and3 *+AR0(5), *+AR1(5), AR0 & .endif
- and_sti_QC: & and *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & and *+AR0(1), R0 &|| sti R1, *+AR1(1) & and R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| and *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| and *+AR0(1), R0 & sti R1, *+AR1(1) &|| and R0, *+AR0(1), R0 & and3_sti_QC: & and3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & and3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & and3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| and3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| and3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| and3 R0, *+AR0(1), R0
- andn_AU: & andn AR1, AR0 & andn AR0 & andn @start, AR0 & andn *+AR0(5), AR0 & andn 5, AR0
- andn_T: & andn AR2, AR1, AR0 & andn AR1, AR0 & andn AR1, *+AR0(1), AR0 & andn *+AR0(1), AR1, AR0 & andn *+AR0(1), AR0 & andn *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & andn 5, AR1, AR0 & andn 5, AR0 & andn *+AR0(5), AR1, AR0 & andn *+AR0(5), AR0 & andn 5, *+AR0(5), AR0 & andn *+AR0(5), *+AR1(5), AR0 & .endif & andn3_T: & andn3 AR2, AR1, AR0 & andn3 AR1, AR0 & andn3 AR1, *+AR0(1), AR0 & andn3 *+AR0(1), AR1, AR0 & andn3 *+AR0(1), AR0 & andn3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & andn3 -5, AR1, AR0 & andn3 -5, AR0 & andn3 *+AR0(5), AR1, AR0 & andn3 *+AR0(5), AR0 & andn3 -5, *+AR0(5), AR0 & andn3 *+AR0(5), *+AR1(5), AR0 & .endif
- ash_A: & ash AR1, AR0 & ash AR0 & ash @start, AR0 & ash *+AR0(5), AR0 & ash -5, AR0
- ash_T: & ash AR2, AR1, AR0 & ash AR1, AR0 & ash AR1, *+AR0(1), AR0 & ash *+AR0(1), AR1, AR0 & ash *+AR0(1), AR0 & ash *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & ash 5, AR1, AR0 & ash 5, AR0 & ash *+AR0(5), AR1, AR0 & ash *+AR0(5), AR0 & ash 5, *+AR0(5), AR0 & ash *+AR0(5), *+AR1(5), AR0 & .endif & ash3_T: & ash3 AR2, AR1, AR0 & ash3 AR1, AR0 & ash3 AR1, *+AR0(1), AR0 & ash3 *+AR0(1), AR1, AR0 & ash3 *+AR0(1), AR0 & ash3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & ash3 -5, AR1, AR0 & ash3 -5, AR0 & ash3 *+AR0(5), AR1, AR0 & ash3 *+AR0(5), AR0 & ash3 -5, *+AR0(5), AR0 & ash3 *+AR0(5), *+AR1(5), AR0 & .endif
- ash_sti_Q: & ash R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ash R0, *+AR0(1), R0 & ash3_sti_Q: & ash3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ash3 R0, *+AR0(1), R0
- bC_J: & bC R0 & bC start & b_J: & b R0 & b start
- bCd_J: & bCd R0 & bCd start & bd_J: & bd R0 & bd start
+ ;;------------------------------------
+ ;; C3X INSNS
+ ;;------------------------------------
+start: .ifdef TEST_C3X & absf_B: & absf R1, R0 & absf R0 & absf @start, R0 & absf *+AR0(5), R0 & absf 3.5, R0 & .endif
+ .ifdef TEST_C3X & absf_stf_P: & absf *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| absf *+AR0(1), R0 & .endif & .ifdef TEST_ENH & absf_stf_P_enh: & absf R0, R0 &|| stf R1, *+AR1(1) & absf R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| absf R0, R0 & stf R1, *+AR1(1) &|| absf R0 & .endif
+ .ifdef TEST_C3X & absi_A: & absi AR1, AR0 & absi AR0 & absi @start, AR0 & absi *+AR0(5), AR0 & absi -5, AR0 & .endif
+ .ifdef TEST_C3X & absi_sti_P: & absi *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| absi *+AR0(1), R0 & .endif & .ifdef TEST_ENH & absi_sti_P_enh: & absi R0, R0 &|| sti R1, *+AR1(1) & absi R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| absi R0, R0 & sti R1, *+AR1(1) &|| absi R0 & .endif
+ .ifdef TEST_C3X & addc_A: & addc AR1, AR0 & addc AR0 & addc @start, AR0 & addc *+AR0(5), AR0 & addc -5, AR0 & .endif
+ .ifdef TEST_C3X & addc_TC: & addc AR2, AR1, AR0 & addc AR1, AR0 & addc AR1, *+AR0(1), AR0 & addc *+AR0(1), AR1, AR0 & addc *+AR0(1), AR0 & addc *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & addc_TC_c4x: & addc -5, AR1, AR0 & addc -5, AR0 & addc AR1, -5, AR0 & addc *+AR0(5), AR1, AR0 & addc *+AR0(5), AR0 & addc AR1, *+AR0(5), AR0 & addc -5, *+AR0(5), AR0 & addc *+AR0(5), -5, AR0 & addc *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & addc3_TC: & addc3 AR2, AR1, AR0 & addc3 AR1, AR0 & addc3 AR1, *+AR0(1), AR0 & addc3 *+AR0(1), AR1, AR0 & addc3 *+AR0(1), AR0 & addc3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & addc3_TC_c4x: & addc3 -5, AR1, AR0 & addc3 -5, AR0 & addc3 AR1, -5, AR0 & addc3 *+AR0(5), AR1, AR0 & addc3 *+AR0(5), AR0 & addc3 AR1, *+AR0(5), AR0 & addc3 -5, *+AR0(5), AR0 & addc3 *+AR0(5), -5, AR0 & addc3 *+AR0(5), *+AR1(5), AR0 & .endif
+ .ifdef TEST_C3X & addf_B: & addf R1, R0 & addf R0 & addf @start, R0 & addf *+AR0(5), R0 & addf 3.5, R0 & .endif
+ .ifdef TEST_C3X & addf_SC: & addf R2, R1, R0 & addf R1, R0 & addf R1, *+AR0(1), R0 & addf *+AR0(1), R1, R0 & addf *+AR0(1), R0 & addf *+AR0(1), *+AR1(1), R0 & .endif & .ifdef TEST_C4X & addf_SC_c4x: & addf *+AR0(5), R1, R0 & addf *+AR0(5), R0 & addf R1, *+AR0(5), R0 & addf *+AR0(5), *+AR1(5), R0 & .endif & .ifdef TEST_C3X & addf3_SC: & addf3 R2, R1, R0 & addf3 R1, R0 & addf3 R1, *+AR0(1), R0 & addf3 *+AR0(1), R1, R0 & addf3 *+AR0(1), R0 & addf3 *+AR0(1), *+AR1(1), R0 & .endif & .ifdef TEST_C4X & addf3_SC_c4x: & addf3 *+AR0(5), R1, R0 & addf3 *+AR0(5), R0 & addf3 R1, *+AR0(5), R0 & addf3 *+AR0(5), *+AR1(5), R0 & .endif
+ .ifdef TEST_C3X & addf_stf_QC: & addf *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & addf *+AR0(1), R0 &|| stf R1, *+AR1(1) & addf R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| addf *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| addf *+AR0(1), R0 & stf R1, *+AR1(1) &|| addf R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addf_stf_QC_enh: & addf AR0, R1, R0 &|| stf R1, *+AR1(1) & addf R2, R1, R0 &|| stf R1, *+AR1(1) & addf R1, R0 &|| stf R1, *+AR1(1) & addf R0 &|| stf R1, *+AR1(1) & addf R0, AR0, R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| addf AR0, R1, R0 & stf R1, *+AR1(1) &|| addf R2, R1, R0 & stf R1, *+AR1(1) &|| addf R1, R0 & stf R1, *+AR1(1) &|| addf R0 & stf R1, *+AR1(1) &|| addf R0, AR0, R0 & .endif & .ifdef TEST_C3X & addf3_stf_QC: & addf3 *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & addf3 *+AR0(1), R0 &|| stf R1, *+AR1(1) & addf3 R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| addf3 *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| addf3 *+AR0(1), R0 & stf R1, *+AR1(1) &|| addf3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addf3_stf_QC_enh: & addf3 AR0, R1, R0 &|| stf R1, *+AR1(1) & addf3 R2, R1, R0 &|| stf R1, *+AR1(1) & addf3 R1, R0 &|| stf R1, *+AR1(1) & addf3 R0 &|| stf R1, *+AR1(1) & addf3 R0, AR0, R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| addf3 AR0, R1, R0 & stf R1, *+AR1(1) &|| addf3 R2, R1, R0 & stf R1, *+AR1(1) &|| addf3 R1, R0 & stf R1, *+AR1(1) &|| addf3 R0 & stf R1, *+AR1(1) &|| addf3 R0, AR0, R0 & .endif
+ .ifdef TEST_C3X & addi_A: & addi AR1, AR0 & addi AR0 & addi @start, AR0 & addi *+AR0(5), AR0 & addi -5, AR0 & .endif
+ .ifdef TEST_C3X & addi_TC: & addi AR2, AR1, AR0 & addi AR1, AR0 & addi AR1, *+AR0(1), AR0 & addi *+AR0(1), AR1, AR0 & addi *+AR0(1), AR0 & addi *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & addi_TC_c4x: & addi -5, AR1, AR0 & addi -5, AR0 & addi AR1, -5, AR0 & addi *+AR0(5), AR1, AR0 & addi *+AR0(5), AR0 & addi AR1, *+AR0(5), AR0 & addi -5, *+AR0(5), AR0 & addi *+AR0(5), -5, AR0 & addi *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & addi3_TC: & addi3 AR2, AR1, AR0 & addi3 AR1, AR0 & addi3 AR1, *+AR0(1), AR0 & addi3 *+AR0(1), AR1, AR0 & addi3 *+AR0(1), AR0 & addi3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & addi3_TC_c4x: & addi3 -5, AR1, AR0 & addi3 -5, AR0 & addi3 AR1, -5, AR0 & addi3 *+AR0(5), AR1, AR0 & addi3 *+AR0(5), AR0 & addi3 AR1, *+AR0(5), AR0 & addi3 -5, *+AR0(5), AR0 & addi3 *+AR0(5), -5, AR0 & addi3 *+AR0(5), *+AR1(5), AR0 & .endif
+ .ifdef TEST_C3X & addi_sti_QC: & addi *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & addi *+AR0(1), R0 &|| sti R1, *+AR1(1) & addi R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| addi *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| addi *+AR0(1), R0 & sti R1, *+AR1(1) &|| addi R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addi_sti_QC_enh: & addi AR0, R1, R0 &|| sti R1, *+AR1(1) & addi R2, R1, R0 &|| sti R1, *+AR1(1) & addi R1, R0 &|| sti R1, *+AR1(1) & addi R0 &|| sti R1, *+AR1(1) & addi R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| addi AR0, R1, R0 & sti R1, *+AR1(1) &|| addi R2, R1, R0 & sti R1, *+AR1(1) &|| addi R1, R0 & sti R1, *+AR1(1) &|| addi R0 & sti R1, *+AR1(1) &|| addi R0, AR0, R0 & .endif & .ifdef TEST_C3X & addi3_sti_QC: & addi3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & addi3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & addi3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| addi3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| addi3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| addi3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addi3_sti_QC_enh: & addi3 AR0, R1, R0 &|| sti R1, *+AR1(1) & addi3 R2, R1, R0 &|| sti R1, *+AR1(1) & addi3 R1, R0 &|| sti R1, *+AR1(1) & addi3 R0 &|| sti R1, *+AR1(1) & addi3 R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| addi3 AR0, R1, R0 & sti R1, *+AR1(1) &|| addi3 R2, R1, R0 & sti R1, *+AR1(1) &|| addi3 R1, R0 & sti R1, *+AR1(1) &|| addi3 R0 & sti R1, *+AR1(1) &|| addi3 R0, AR0, R0 & .endif
+ .ifdef TEST_C3X & and_AU: & and AR1, AR0 & and AR0 & and @start, AR0 & and *+AR0(5), AR0 & and 5, AR0 & .endif
+ .ifdef TEST_C3X & and_TC: & and AR2, AR1, AR0 & and AR1, AR0 & and AR1, *+AR0(1), AR0 & and *+AR0(1), AR1, AR0 & and *+AR0(1), AR0 & and *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & and_TC_c4x: & and -5, AR1, AR0 & and -5, AR0 & and AR1, -5, AR0 & and *+AR0(5), AR1, AR0 & and *+AR0(5), AR0 & and AR1, *+AR0(5), AR0 & and -5, *+AR0(5), AR0 & and *+AR0(5), -5, AR0 & and *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & and3_TC: & and3 AR2, AR1, AR0 & and3 AR1, AR0 & and3 AR1, *+AR0(1), AR0 & and3 *+AR0(1), AR1, AR0 & and3 *+AR0(1), AR0 & and3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & and3_TC_c4x: & and3 -5, AR1, AR0 & and3 -5, AR0 & and3 AR1, -5, AR0 & and3 *+AR0(5), AR1, AR0 & and3 *+AR0(5), AR0 & and3 AR1, *+AR0(5), AR0 & and3 -5, *+AR0(5), AR0 & and3 *+AR0(5), -5, AR0 & and3 *+AR0(5), *+AR1(5), AR0 & .endif
+ .ifdef TEST_C3X & and_sti_QC: & and *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & and *+AR0(1), R0 &|| sti R1, *+AR1(1) & and R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| and *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| and *+AR0(1), R0 & sti R1, *+AR1(1) &|| and R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & and_sti_QC_enh: & and AR0, R1, R0 &|| sti R1, *+AR1(1) & and R2, R1, R0 &|| sti R1, *+AR1(1) & and R1, R0 &|| sti R1, *+AR1(1) & and R0 &|| sti R1, *+AR1(1) & and R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| and AR0, R1, R0 & sti R1, *+AR1(1) &|| and R2, R1, R0 & sti R1, *+AR1(1) &|| and R1, R0 & sti R1, *+AR1(1) &|| and R0 & sti R1, *+AR1(1) &|| and R0, AR0, R0 & .endif & .ifdef TEST_C3X & and3_sti_QC: & and3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & and3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & and3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| and3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| and3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| and3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & and3_sti_QC_enh: & and3 AR0, R1, R0 &|| sti R1, *+AR1(1) & and3 R2, R1, R0 &|| sti R1, *+AR1(1) & and3 R1, R0 &|| sti R1, *+AR1(1) & and3 R0 &|| sti R1, *+AR1(1) & and3 R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| and3 AR0, R1, R0 & sti R1, *+AR1(1) &|| and3 R2, R1, R0 & sti R1, *+AR1(1) &|| and3 R1, R0 & sti R1, *+AR1(1) &|| and3 R0 & sti R1, *+AR1(1) &|| and3 R0, AR0, R0 & .endif
+ .ifdef TEST_C3X & andn_AU: & andn AR1, AR0 & andn AR0 & andn @start, AR0 & andn *+AR0(5), AR0 & andn 5, AR0 & .endif
+ .ifdef TEST_C3X & andn_T: & andn AR2, AR1, AR0 & andn AR1, AR0 & andn AR1, *+AR0(1), AR0 & andn *+AR0(1), AR1, AR0 & andn *+AR0(1), AR0 & andn *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & andn_T_sc: & andn -5, AR1, AR0 & andn -5, AR0 & andn *+AR0(5), AR1, AR0 & andn *+AR0(5), AR0 & andn -5, *+AR0(5), AR0 & andn *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & andn3_T: & andn3 AR2, AR1, AR0 & andn3 AR1, AR0 & andn3 AR1, *+AR0(1), AR0 & andn3 *+AR0(1), AR1, AR0 & andn3 *+AR0(1), AR0 & andn3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & andn3_T_sc: & andn3 -5, AR1, AR0 & andn3 -5, AR0 & andn3 *+AR0(5), AR1, AR0 & andn3 *+AR0(5), AR0 & andn3 -5, *+AR0(5), AR0 & andn3 *+AR0(5), *+AR1(5), AR0 & .endif
+ .ifdef TEST_C3X & ash_A: & ash AR1, AR0 & ash AR0 & ash @start, AR0 & ash *+AR0(5), AR0 & ash -5, AR0 & .endif
+ .ifdef TEST_C3X & ash_T: & ash AR2, AR1, AR0 & ash AR1, AR0 & ash AR1, *+AR0(1), AR0 & ash *+AR0(1), AR1, AR0 & ash *+AR0(1), AR0 & ash *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & ash_T_sc: & ash -5, AR1, AR0 & ash -5, AR0 & ash *+AR0(5), AR1, AR0 & ash *+AR0(5), AR0 & ash -5, *+AR0(5), AR0 & ash *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & ash3_T: & ash3 AR2, AR1, AR0 & ash3 AR1, AR0 & ash3 AR1, *+AR0(1), AR0 & ash3 *+AR0(1), AR1, AR0 & ash3 *+AR0(1), AR0 & ash3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & ash3_T_sc: & ash3 -5, AR1, AR0 & ash3 -5, AR0 & ash3 *+AR0(5), AR1, AR0 & ash3 *+AR0(5), AR0 & ash3 -5, *+AR0(5), AR0 & ash3 *+AR0(5), *+AR1(5), AR0 & .endif
+ .ifdef TEST_C3X & ash_sti_Q: & ash R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ash R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & ash_sti_Q_enh: & ash R0, R0, R0 &|| sti R1, *+AR1(1) & ash R0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ash R0, R0, R0 & sti R1, *+AR1(1) &|| ash R0, R0 & .endif & .ifdef TEST_C3X & ash3_sti_Q: & ash3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ash3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & ash3_sti_Q_enh: & ash3 R0, R0, R0 &|| sti R1, *+AR1(1) & ash3 R0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ash3 R0, R0, R0 & sti R1, *+AR1(1) &|| ash3 R0, R0 & .endif
+ .ifdef TEST_C3X & bC_J: & bC R0 & bC start & b_J: & b R0 & b start & .endif
+ .ifdef TEST_C3X & bCd_J: & bCd R0 & bCd start & bd_J: & bd R0 & bd start & .endif
+ .ifdef TEST_C3X
br_I: br start
brd_I: brd start
call_I: call start
call_JS: callc R0
callc start
- cmpf_B: & cmpf R1, R0 & cmpf R0 & cmpf @start, R0 & cmpf *+AR0(5), R0 & cmpf 3.5, R0
- cmpf_S2: & cmpf R2, R1 & cmpf R1, *+AR0(1) & cmpf *+AR0(1), R1 & cmpf *+AR0(1), *+AR1(1) & .ifdef TEST_C4X & cmpf *+AR0(5), R1 & cmpf *+AR0(5), *+AR1(5) & .endif & cmpf3_S2: & cmpf3 R2, R1 & cmpf3 R1, *+AR0(1) & cmpf3 *+AR0(1), R1 & cmpf3 *+AR0(1), *+AR1(1) & .ifdef TEST_C4X & cmpf3 *+AR0(5), R1 & cmpf3 *+AR0(5), *+AR1(5) & .endif
- cmpi_A: & cmpi AR1, AR0 & cmpi AR0 & cmpi @start, AR0 & cmpi *+AR0(5), AR0 & cmpi -5, AR0
- cmpi_T2: & cmpi AR2, AR1 & cmpi AR1, *+AR0(1) & cmpi *+AR0(1), AR1 & cmpi *+AR1(1), *+AR0(1) & .ifdef TEST_C4X & cmpi -5, AR1 & cmpi *+AR0(5), AR1 & cmpi -5, *+AR0(5) & cmpi *+AR0(5), *+AR1(5) & .endif & cmpi3_T2: & cmpi3 AR2, AR1 & cmpi3 AR1, *+AR0(1) & cmpi3 *+AR0(1), AR1 & cmpi3 *+AR1(1), *+AR0(1) & .ifdef TEST_C4X & cmpi3 -5, AR1 & cmpi3 *+AR0(5), AR1 & cmpi3 -5, *+AR0(5) & cmpi3 *+AR0(5), *+AR1(5) & .endif
- dbC_D: & dbC AR0, R0 & dbC AR0, start & db_D: & db AR0, R0 & db AR0, start
- dbCd_D: & dbCd AR0, R0 & dbCd AR0, start & dbd_D: & dbd AR0, R0 & dbd AR0, start
- fix_AF: & fix R1, R0 & fix R0 & fix @start, AR0 & fix *+AR0(5), AR0 & fix 3.5, AR0
- fix_sti_P: & fix *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| fix *+AR0(1), R0
- float_BI: & float AR1, R0 & float R0 & float @start, R0 & float *+AR0(5), R0 & float -5, R0
- float_stf_P: & float *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| float *+AR0(1), R0
+ .endif
+ .ifdef TEST_C3X & cmpf_B: & cmpf R1, R0 & cmpf R0 & cmpf @start, R0 & cmpf *+AR0(5), R0 & cmpf 3.5, R0 & .endif
+ .ifdef TEST_C3X & cmpf_S2: & cmpf R2, R1 & cmpf R1, *+AR0(1) & cmpf *+AR0(1), R1 & cmpf *+AR0(1), *+AR1(1) & .endif & .ifdef TEST_C4X & cmpf_S2_c4x: & cmpf *+AR0(5), R1 & cmpf *+AR0(5), *+AR1(5) & .endif & .ifdef TEST_C3X & cmpf3_S2: & cmpf3 R2, R1 & cmpf3 R1, *+AR0(1) & cmpf3 *+AR0(1), R1 & cmpf3 *+AR0(1), *+AR1(1) & .endif & .ifdef TEST_C4X & cmpf3_S2_c4x: & cmpf3 *+AR0(5), R1 & cmpf3 *+AR0(5), *+AR1(5) & .endif
+ .ifdef TEST_C3X & cmpi_A: & cmpi AR1, AR0 & cmpi AR0 & cmpi @start, AR0 & cmpi *+AR0(5), AR0 & cmpi -5, AR0 & .endif
+ .ifdef TEST_C3X & cmpi_T2: & cmpi AR2, AR1 & cmpi AR1, *+AR0(1) & cmpi *+AR0(1), AR1 & cmpi *+AR1(1), *+AR0(1) & .endif & .ifdef TEST_C4X & cmpi_T2_c4x: & cmpi -5, AR1 & cmpi *+AR0(5), AR1 & cmpi -5, *+AR0(5) & cmpi *+AR0(5), *+AR1(5) & .endif & .ifdef TEST_C3X & cmpi3_T2: & cmpi3 AR2, AR1 & cmpi3 AR1, *+AR0(1) & cmpi3 *+AR0(1), AR1 & cmpi3 *+AR1(1), *+AR0(1) & .endif & .ifdef TEST_C4X & cmpi3_T2_c4x: & cmpi3 -5, AR1 & cmpi3 *+AR0(5), AR1 & cmpi3 -5, *+AR0(5) & cmpi3 *+AR0(5), *+AR1(5) & .endif
+ .ifdef TEST_C3X & dbC_D: & dbC AR0, R0 & dbC AR0, start & db_D: & db AR0, R0 & db AR0, start & .endif
+ .ifdef TEST_C3X & dbCd_D: & dbCd AR0, R0 & dbCd AR0, start & dbd_D: & dbd AR0, R0 & dbd AR0, start & .endif
+ .ifdef TEST_C3X & fix_AF: & fix R1, R0 & fix R0 & fix @start, AR0 & fix *+AR0(5), AR0 & fix 3.5, AR0 & .endif
+ .ifdef TEST_C3X & fix_sti_P: & fix *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| fix *+AR0(1), R0 & .endif & .ifdef TEST_ENH & fix_sti_P_enh: & fix R0, R0 &|| sti R1, *+AR1(1) & fix R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| fix R0, R0 & sti R1, *+AR1(1) &|| fix R0 & .endif
+ .ifdef TEST_C3X & float_BI: & float AR1, R0 & float R0 & float @start, R0 & float *+AR0(5), R0 & float -5, R0 & .endif
+ .ifdef TEST_C3X & float_stf_P: & float *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| float *+AR0(1), R0 & .endif & .ifdef TEST_ENH & float_stf_P_enh: & float R0, R0 &|| stf R1, *+AR1(1) & float R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| float R0, R0 & stf R1, *+AR1(1) &|| float R0 & .endif
+ .ifdef TEST_C3X
iack_Z: iack @start
iack *+AR0(1)
idle_Z: idle
+ .endif
.ifdef TEST_IDLE2
idle2_Z: idle2
.endif
- lde_B: & lde R1, R0 & lde R0 & lde @start, R0 & lde *+AR0(5), R0 & lde 3.5, R0
- ldf_B: & ldf R1, R0 & ldf R0 & ldf @start, R0 & ldf *+AR0(5), R0 & ldf 3.5, R0
- ldf_LL: & ldf *+AR0(1), R0 &|| ldf *+AR1(1), R1 & ldf2 *+AR0(1), R0 &|| ldf1 *+AR1(1), R1 & ldf1 *+AR1(1), R1 &|| ldf2 *+AR0(1), R0
- ldf_stf_P: & ldf *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| ldf *+AR0(1), R0
- ldfC_BB: & ldfC R1, R0 & ldfC R0 & ldfC @start, R0 & ldfC *+AR0(5), R0 & ldfC 3.5, R0
- ldfi_B6: & ldfi @start, R0 & ldfi *+AR0(5), R0
- ldi_A: & ldi AR1, AR0 & ldi AR0 & ldi @start, AR0 & ldi *+AR0(5), AR0 & ldi -5, AR0
- ldi_LL: & ldi *+AR0(1), R0 &|| ldi *+AR1(1), R1 & ldi2 *+AR0(1), R0 &|| ldi1 *+AR1(1), R1 & ldi1 *+AR1(1), R1 &|| ldi2 *+AR0(1), R0
- ldi_sti_P: & ldi *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ldi *+AR0(1), R0
- ldiC_AB: & ldiC AR1, AR0 & ldiC AR0 & ldiC @start, AR0 & ldiC *+AR0(5), AR0 & ldiC -5, AR0
- ldii_A6: & ldii @start, AR0 & ldii *+AR0(5), AR0
+ .ifdef TEST_C3X & lde_B: & lde R1, R0 & lde R0 & lde @start, R0 & lde *+AR0(5), R0 & lde 3.5, R0 & .endif
+ .ifdef TEST_C3X & ldf_B: & ldf R1, R0 & ldf R0 & ldf @start, R0 & ldf *+AR0(5), R0 & ldf 3.5, R0 & .endif
+ .ifdef TEST_C3X & ldf_LL: & ldf *+AR0(1), R0 &|| ldf *+AR1(1), R1 & ldf2 *+AR0(1), R0 &|| ldf1 *+AR1(1), R1 & ldf1 *+AR1(1), R1 &|| ldf2 *+AR0(1), R0 & .endif & .ifdef TEST_ENH & ldf_LL_enh: & ldf R0, R0 &|| ldf *+AR1(1), R1 & ldf R0 &|| ldf *+AR1(1), R1 & ldf2 R0, R0 &|| ldf1 *+AR1(1), R1 & ldf2 R0 &|| ldf1 *+AR1(1), R1 & ldf1 *+AR1(1), R1 &|| ldf2 R0, R0 & ldf1 *+AR1(1), R1 &|| ldf2 R0 & .endif
+ .ifdef TEST_C3X & ldf_stf_P: & ldf *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| ldf *+AR0(1), R0 & .endif & .ifdef TEST_ENH & ldf_stf_P_enh: & ldf R0, R0 &|| stf R1, *+AR1(1) & ldf R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| ldf R0, R0 & stf R1, *+AR1(1) &|| ldf R0 & .endif
+ .ifdef TEST_C3X & ldfC_BB: & ldfC R1, R0 & ldfC R0 & ldfC @start, R0 & ldfC *+AR0(5), R0 & ldfC 3.5, R0 & .endif
+ .ifdef TEST_C3X & ldfi_B6: & ldfi @start, R0 & ldfi *+AR0(5), R0 & .endif
+ .ifdef TEST_C3X & ldi_A: & ldi AR1, AR0 & ldi AR0 & ldi @start, AR0 & ldi *+AR0(5), AR0 & ldi -5, AR0 & .endif
+ .ifdef TEST_C3X & ldi_LL: & ldi *+AR0(1), R0 &|| ldi *+AR1(1), R1 & ldi2 *+AR0(1), R0 &|| ldi1 *+AR1(1), R1 & ldi1 *+AR1(1), R1 &|| ldi2 *+AR0(1), R0 & .endif & .ifdef TEST_ENH & ldi_LL_enh: & ldi R0, R0 &|| ldi *+AR1(1), R1 & ldi R0 &|| ldi *+AR1(1), R1 & ldi2 R0, R0 &|| ldi1 *+AR1(1), R1 & ldi2 R0 &|| ldi1 *+AR1(1), R1 & ldi1 *+AR1(1), R1 &|| ldi2 R0, R0 & ldi1 *+AR1(1), R1 &|| ldi2 R0 & .endif
+ .ifdef TEST_C3X & ldi_sti_P: & ldi *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ldi *+AR0(1), R0 & .endif & .ifdef TEST_ENH & ldi_sti_P_enh: & ldi R0, R0 &|| sti R1, *+AR1(1) & ldi R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| ldi R0, R0 & sti R1, *+AR1(1) &|| ldi R0 & .endif
+ .ifdef TEST_C3X & ldiC_AB: & ldiC AR1, AR0 & ldiC AR0 & ldiC @start, AR0 & ldiC *+AR0(5), AR0 & ldiC -5, AR0 & .endif
+ .ifdef TEST_C3X & ldii_A6: & ldii @start, AR0 & ldii *+AR0(5), AR0 & .endif
+ .ifdef TEST_C3X
ldp_Z: ldp start
- ldm_B: & ldm R1, R0 & ldm R0 & ldm @start, R0 & ldm *+AR0(5), R0 & ldm 3.5, R0
+ .endif
+ .ifdef TEST_C3X & ldm_B: & ldm R1, R0 & ldm R0 & ldm @start, R0 & ldm *+AR0(5), R0 & ldm 3.5, R0 & .endif
.ifdef TEST_LPWR
lopower_Z: lopower
.endif
- lsh_A: & lsh AR1, AR0 & lsh AR0 & lsh @start, AR0 & lsh *+AR0(5), AR0 & lsh -5, AR0
- lsh_T: & lsh AR2, AR1, AR0 & lsh AR1, AR0 & lsh AR1, *+AR0(1), AR0 & lsh *+AR0(1), AR1, AR0 & lsh *+AR0(1), AR0 & lsh *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & lsh 5, AR1, AR0 & lsh 5, AR0 & lsh *+AR0(5), AR1, AR0 & lsh *+AR0(5), AR0 & lsh 5, *+AR0(5), AR0 & lsh *+AR0(5), *+AR1(5), AR0 & .endif & lsh3_T: & lsh3 AR2, AR1, AR0 & lsh3 AR1, AR0 & lsh3 AR1, *+AR0(1), AR0 & lsh3 *+AR0(1), AR1, AR0 & lsh3 *+AR0(1), AR0 & lsh3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & lsh3 -5, AR1, AR0 & lsh3 -5, AR0 & lsh3 *+AR0(5), AR1, AR0 & lsh3 *+AR0(5), AR0 & lsh3 -5, *+AR0(5), AR0 & lsh3 *+AR0(5), *+AR1(5), AR0 & .endif
- lsh_sti_Q: & lsh R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| lsh R0, *+AR0(1), R0 & lsh3_sti_Q: & lsh3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| lsh3 R0, *+AR0(1), R0
+ .ifdef TEST_C3X & lsh_A: & lsh AR1, AR0 & lsh AR0 & lsh @start, AR0 & lsh *+AR0(5), AR0 & lsh -5, AR0 & .endif
+ .ifdef TEST_C3X & lsh_T: & lsh AR2, AR1, AR0 & lsh AR1, AR0 & lsh AR1, *+AR0(1), AR0 & lsh *+AR0(1), AR1, AR0 & lsh *+AR0(1), AR0 & lsh *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & lsh_T_sc: & lsh -5, AR1, AR0 & lsh -5, AR0 & lsh *+AR0(5), AR1, AR0 & lsh *+AR0(5), AR0 & lsh -5, *+AR0(5), AR0 & lsh *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & lsh3_T: & lsh3 AR2, AR1, AR0 & lsh3 AR1, AR0 & lsh3 AR1, *+AR0(1), AR0 & lsh3 *+AR0(1), AR1, AR0 & lsh3 *+AR0(1), AR0 & lsh3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & lsh3_T_sc: & lsh3 -5, AR1, AR0 & lsh3 -5, AR0 & lsh3 *+AR0(5), AR1, AR0 & lsh3 *+AR0(5), AR0 & lsh3 -5, *+AR0(5), AR0 & lsh3 *+AR0(5), *+AR1(5), AR0 & .endif
+ .ifdef TEST_C3X & lsh_sti_Q: & lsh R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| lsh R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & lsh_sti_Q_enh: & lsh R0, R0, R0 &|| sti R1, *+AR1(1) & lsh R0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| lsh R0, R0, R0 & sti R1, *+AR1(1) &|| lsh R0, R0 & .endif & .ifdef TEST_C3X & lsh3_sti_Q: & lsh3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| lsh3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & lsh3_sti_Q_enh: & lsh3 R0, R0, R0 &|| sti R1, *+AR1(1) & lsh3 R0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| lsh3 R0, R0, R0 & sti R1, *+AR1(1) &|| lsh3 R0, R0 & .endif
.ifdef TEST_LPWR
maxspeed_Z: maxspeed
.endif
- mpyf_B: & mpyf R1, R0 & mpyf R0 & mpyf @start, R0 & mpyf *+AR0(5), R0 & mpyf 3.5, R0
- mpyf_SC: & mpyf R2, R1, R0 & mpyf R1, R0 & mpyf R1, *+AR0(1), R0 & mpyf *+AR0(1), R1, R0 & mpyf *+AR0(1), R0 & mpyf *+AR0(1), *+AR1(1), R0 & .ifdef TEST_C4X & mpyf *+AR0(5), R1, R0 & mpyf *+AR0(5), R0 & mpyf R1, *+AR0(5), R0 & mpyf *+AR0(5), *+AR1(5), R0 & .endif & mpyf3_SC: & mpyf3 R2, R1, R0 & mpyf3 R1, R0 & mpyf3 R1, *+AR0(1), R0 & mpyf3 *+AR0(1), R1, R0 & mpyf3 *+AR0(1), R0 & mpyf3 *+AR0(1), *+AR1(1), R0 & .ifdef TEST_C4X & mpyf3 *+AR0(5), R1, R0 & mpyf3 *+AR0(5), R0 & mpyf3 R1, *+AR0(5), R0 & mpyf3 *+AR0(5), *+AR1(5), R0 & .endif
- mpyf_addf_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| addf R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| addf R0, R2 & mpyf *+AR0(1), R0, R0 &|| addf R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| addf *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| addf *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| addf *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| addf *+AR1(1), R2 & mpyf3_addf_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| addf R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| addf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| addf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| addf *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| addf *+AR1(1), R2 & mpyf_addf3_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R2 & mpyf *+AR0(1), R0, R0 &|| addf3 R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| addf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & mpyf3_addf3_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| addf3 R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| addf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & addf_mpyf_M: & addf R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & addf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & addf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & addf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & addf *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & addf3_mpyf3_M: & addf3 R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf3 R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & addf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & addf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf3 *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & addf_mpyf3_M: & addf R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & addf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & addf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & addf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & addf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & addf3_mpyf_M: & addf3 R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf3 R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & addf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & addf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf3 *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 &
- mpyf_stf_QC: & mpyf *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & mpyf *+AR0(1), R0 &|| stf R1, *+AR1(1) & mpyf R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| mpyf *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| mpyf *+AR0(1), R0 & stf R1, *+AR1(1) &|| mpyf R0, *+AR0(1), R0 & mpyf3_stf_QC: & mpyf3 *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & mpyf3 *+AR0(1), R0 &|| stf R1, *+AR1(1) & mpyf3 R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| mpyf3 *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| mpyf3 *+AR0(1), R0 & stf R1, *+AR1(1) &|| mpyf3 R0, *+AR0(1), R0
- mpyf_subf_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| subf R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| subf R0, R2 & mpyf *+AR0(1), R0, R0 &|| subf R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| subf *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| subf *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| subf *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| subf *+AR1(1), R2 & mpyf3_subf_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| subf R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| subf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| subf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| subf *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| subf *+AR1(1), R2 & mpyf_subf3_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R2 & mpyf *+AR0(1), R0, R0 &|| subf3 R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| subf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & mpyf3_subf3_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| subf3 R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| subf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & subf_mpyf_M: & subf R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & subf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & subf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & subf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & subf *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & subf3_mpyf3_M: & subf3 R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf3 R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & subf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & subf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf3 *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & subf_mpyf3_M: & subf R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & subf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & subf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & subf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & subf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & subf3_mpyf_M: & subf3 R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf3 R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & subf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & subf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf3 *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 &
- mpyi_A: & mpyi AR1, AR0 & mpyi AR0 & mpyi @start, AR0 & mpyi *+AR0(5), AR0 & mpyi -5, AR0
- mpyi_TC: & mpyi AR2, AR1, AR0 & mpyi AR1, AR0 & mpyi AR1, *+AR0(1), AR0 & mpyi *+AR0(1), AR1, AR0 & mpyi *+AR0(1), AR0 & mpyi *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & mpyi 5, AR1, AR0 & mpyi 5, AR0 & mpyi AR1, -5, AR0 & mpyi *+AR0(5), AR1, AR0 & mpyi *+AR0(5), AR0 & mpyi AR1, *+AR0(5), AR0 & mpyi 5, *+AR0(5), AR0 & mpyi *+AR0(5), -5, AR0 & mpyi *+AR0(5), *+AR1(5), AR0 & .endif & mpyi3_TC: & mpyi3 AR2, AR1, AR0 & mpyi3 AR1, AR0 & mpyi3 AR1, *+AR0(1), AR0 & mpyi3 *+AR0(1), AR1, AR0 & mpyi3 *+AR0(1), AR0 & mpyi3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & mpyi3 -5, AR1, AR0 & mpyi3 -5, AR0 & mpyi3 AR1, -5, AR0 & mpyi3 *+AR0(5), AR1, AR0 & mpyi3 *+AR0(5), AR0 & mpyi3 AR1, *+AR0(5), AR0 & mpyi3 -5, *+AR0(5), AR0 & mpyi3 *+AR0(5), -5, AR0 & mpyi3 *+AR0(5), *+AR1(5), AR0 & .endif
- mpyi_addi_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| addi R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| addi R0, R2 & mpyi *+AR0(1), R0, R0 &|| addi R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| addi *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| addi *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| addi *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| addi *+AR1(1), R2 & mpyi3_addi_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| addi R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| addi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| addi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| addi *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| addi *+AR1(1), R2 & mpyi_addi3_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R2 & mpyi *+AR0(1), R0, R0 &|| addi3 R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| addi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & mpyi3_addi3_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| addi3 R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| addi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & addi_mpyi_M: & addi R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & addi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & addi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & addi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & addi *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & addi3_mpyi3_M: & addi3 R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi3 R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & addi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & addi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi3 *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & addi_mpyi3_M: & addi R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & addi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & addi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & addi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & addi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & addi3_mpyi_M: & addi3 R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi3 R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & addi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & addi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi3 *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 &
- mpyi_sti_QC: & mpyi *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & mpyi *+AR0(1), R0 &|| sti R1, *+AR1(1) & mpyi R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| mpyi *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| mpyi *+AR0(1), R0 & sti R1, *+AR1(1) &|| mpyi R0, *+AR0(1), R0 & mpyi3_sti_QC: & mpyi3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & mpyi3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & mpyi3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| mpyi3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| mpyi3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| mpyi3 R0, *+AR0(1), R0
- mpyi_subi_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| subi R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| subi R0, R2 & mpyi *+AR0(1), R0, R0 &|| subi R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| subi *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| subi *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| subi *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| subi *+AR1(1), R2 & mpyi3_subi_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| subi R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| subi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| subi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| subi *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| subi *+AR1(1), R2 & mpyi_subi3_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R2 & mpyi *+AR0(1), R0, R0 &|| subi3 R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| subi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & mpyi3_subi3_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| subi3 R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| subi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & subi_mpyi_M: & subi R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & subi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & subi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & subi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & subi *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & subi3_mpyi3_M: & subi3 R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi3 R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & subi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & subi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi3 *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & subi_mpyi3_M: & subi R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & subi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & subi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & subi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & subi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & subi3_mpyi_M: & subi3 R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi3 R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & subi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & subi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi3 *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 &
- negb_A: & negb AR1, AR0 & negb AR0 & negb @start, AR0 & negb *+AR0(5), AR0 & negb -5, AR0
- negf_B: & negf R1, R0 & negf R0 & negf @start, R0 & negf *+AR0(5), R0 & negf 3.5, R0
- negf_stf_P: & negf *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| negf *+AR0(1), R0
- negi_A: & negi AR1, AR0 & negi AR0 & negi @start, AR0 & negi *+AR0(5), AR0 & negi -5, AR0
- negi_sti_P: & negi *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| negi *+AR0(1), R0
- nop_A2: & nop AR0 & nop *+AR0(5) & nop
- norm_B: & norm R1, R0 & norm R0 & norm @start, R0 & norm *+AR0(5), R0 & norm 3.5, R0
- not_AU: & not AR1, AR0 & not AR0 & not @start, AR0 & not *+AR0(5), AR0 & not 5, AR0
- not_sti_P: & not *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| not *+AR0(1), R0
- or_AU: & or AR1, AR0 & or AR0 & or @start, AR0 & or *+AR0(5), AR0 & or 5, AR0
- or_TC: & or AR2, AR1, AR0 & or AR1, AR0 & or AR1, *+AR0(1), AR0 & or *+AR0(1), AR1, AR0 & or *+AR0(1), AR0 & or *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & or 5, AR1, AR0 & or 5, AR0 & or AR1, -5, AR0 & or *+AR0(5), AR1, AR0 & or *+AR0(5), AR0 & or AR1, *+AR0(5), AR0 & or 5, *+AR0(5), AR0 & or *+AR0(5), -5, AR0 & or *+AR0(5), *+AR1(5), AR0 & .endif & or3_TC: & or3 AR2, AR1, AR0 & or3 AR1, AR0 & or3 AR1, *+AR0(1), AR0 & or3 *+AR0(1), AR1, AR0 & or3 *+AR0(1), AR0 & or3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & or3 -5, AR1, AR0 & or3 -5, AR0 & or3 AR1, -5, AR0 & or3 *+AR0(5), AR1, AR0 & or3 *+AR0(5), AR0 & or3 AR1, *+AR0(5), AR0 & or3 -5, *+AR0(5), AR0 & or3 *+AR0(5), -5, AR0 & or3 *+AR0(5), *+AR1(5), AR0 & .endif
- or_sti_QC: & or *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & or *+AR0(1), R0 &|| sti R1, *+AR1(1) & or R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| or *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| or *+AR0(1), R0 & sti R1, *+AR1(1) &|| or R0, *+AR0(1), R0 & or3_sti_QC: & or3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & or3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & or3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| or3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| or3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| or3 R0, *+AR0(1), R0
- pop_R: & pop AR0
- popf_RF: & popf F0
- push_R: & push AR0
- pushf_RF: & pushf F0
+ .ifdef TEST_C3X & mpyf_B: & mpyf R1, R0 & mpyf R0 & mpyf @start, R0 & mpyf *+AR0(5), R0 & mpyf 3.5, R0 & .endif
+ .ifdef TEST_C3X & mpyf_SC: & mpyf R2, R1, R0 & mpyf R1, R0 & mpyf R1, *+AR0(1), R0 & mpyf *+AR0(1), R1, R0 & mpyf *+AR0(1), R0 & mpyf *+AR0(1), *+AR1(1), R0 & .endif & .ifdef TEST_C4X & mpyf_SC_c4x: & mpyf *+AR0(5), R1, R0 & mpyf *+AR0(5), R0 & mpyf R1, *+AR0(5), R0 & mpyf *+AR0(5), *+AR1(5), R0 & .endif & .ifdef TEST_C3X & mpyf3_SC: & mpyf3 R2, R1, R0 & mpyf3 R1, R0 & mpyf3 R1, *+AR0(1), R0 & mpyf3 *+AR0(1), R1, R0 & mpyf3 *+AR0(1), R0 & mpyf3 *+AR0(1), *+AR1(1), R0 & .endif & .ifdef TEST_C4X & mpyf3_SC_c4x: & mpyf3 *+AR0(5), R1, R0 & mpyf3 *+AR0(5), R0 & mpyf3 R1, *+AR0(5), R0 & mpyf3 *+AR0(5), *+AR1(5), R0 & .endif
+ .ifdef TEST_C3X & mpyf_addf_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| addf R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| addf R0, R2 & mpyf *+AR0(1), R0, R0 &|| addf R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| addf *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| addf *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| addf *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| addf *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf_addf_M_enh: & mpyf R0, R0, R0 &|| addf R2, R2, R2 & mpyf R0, R0 &|| addf R2, R2, R2 & mpyf R0 &|| addf R2, R2, R2 & mpyf R0, R0 &|| addf R2, R2 & mpyf R0 &|| addf R2, R2 & mpyf R0 &|| addf R2 & mpyf AR0, AR0, R0 &|| addf R2, R2, R2 & mpyf AR0, R0, R0 &|| addf R0, AR0, R2 & mpyf R0, AR0, R0 &|| addf R0, AR0, R2 & mpyf R2, R1, R0 &|| addf AR0, AR1, R2 & mpyf AR0, R1, R0 &|| addf AR0, R3, R2 & mpyf R0, AR0, R0 &|| addf AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyf3_addf_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| addf R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| addf *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| addf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| addf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| addf *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| addf *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf3_addf_M_enh: & mpyf3 R0, R0, R0 &|| addf R2, R2, R2 & mpyf3 R0, R0 &|| addf R2, R2, R2 & mpyf3 R0 &|| addf R2, R2, R2 & mpyf3 R0, R0 &|| addf R2, R2 & mpyf3 R0 &|| addf R2, R2 & mpyf3 R0 &|| addf R2 & mpyf3 AR0, AR0, R0 &|| addf R2, R2, R2 & mpyf3 AR0, R0, R0 &|| addf R0, AR0, R2 & mpyf3 R0, AR0, R0 &|| addf R0, AR0, R2 & mpyf3 R2, R1, R0 &|| addf AR0, AR1, R2 & mpyf3 AR0, R1, R0 &|| addf AR0, R3, R2 & mpyf3 R0, AR0, R0 &|| addf AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyf_addf3_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R2 & mpyf *+AR0(1), R0, R0 &|| addf3 R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| addf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf_addf3_M_enh: & mpyf R0, R0, R0 &|| addf3 R2, R2, R2 & mpyf R0, R0 &|| addf3 R2, R2, R2 & mpyf R0 &|| addf3 R2, R2, R2 & mpyf R0, R0 &|| addf3 R2, R2 & mpyf R0 &|| addf3 R2, R2 & mpyf R0 &|| addf3 R2 & mpyf AR0, AR0, R0 &|| addf3 R2, R2, R2 & mpyf AR0, R0, R0 &|| addf3 R0, AR0, R2 & mpyf R0, AR0, R0 &|| addf3 R0, AR0, R2 & mpyf R2, R1, R0 &|| addf3 AR0, AR1, R2 & mpyf AR0, R1, R0 &|| addf3 AR0, R3, R2 & mpyf R0, AR0, R0 &|| addf3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyf3_addf3_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| addf3 R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| addf3 R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf3 R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| addf3 *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| addf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| addf3 *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| addf3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf3_addf3_M_enh: & mpyf3 R0, R0, R0 &|| addf3 R2, R2, R2 & mpyf3 R0, R0 &|| addf3 R2, R2, R2 & mpyf3 R0 &|| addf3 R2, R2, R2 & mpyf3 R0, R0 &|| addf3 R2, R2 & mpyf3 R0 &|| addf3 R2, R2 & mpyf3 R0 &|| addf3 R2 & mpyf3 AR0, AR0, R0 &|| addf3 R2, R2, R2 & mpyf3 AR0, R0, R0 &|| addf3 R0, AR0, R2 & mpyf3 R0, AR0, R0 &|| addf3 R0, AR0, R2 & mpyf3 R2, R1, R0 &|| addf3 AR0, AR1, R2 & mpyf3 AR0, R1, R0 &|| addf3 AR0, R3, R2 & mpyf3 R0, AR0, R0 &|| addf3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & addf_mpyf_M: & addf R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & addf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & addf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & addf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & addf *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addf_mpyf_M_enh: & addf R2, R2, R2 &|| mpyf R0, R0, R0 & addf R2, R2, R2 &|| mpyf R0, R0 & addf R2, R2, R2 &|| mpyf R0 & addf R2, R2 &|| mpyf R0, R0 & addf R2, R2 &|| mpyf R0 & addf R2 &|| mpyf R0 & addf R2, R2, R2 &|| mpyf AR0, AR0, R0 & addf R0, AR0, R2 &|| mpyf AR0, R0, R0 & addf R0, AR0, R2 &|| mpyf R0, AR0, R0 & addf AR0, AR1, R2 &|| mpyf R2, R1, R0 & addf AR0, R3, R2 &|| mpyf AR0, R1, R0 & addf AR0, R0, R2 &|| mpyf R0, AR0, R0 & .endif & .ifdef TEST_C3X & addf3_mpyf_M: & addf3 R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf3 R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & addf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & addf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & addf3 *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addf3_mpyf_M_enh: & addf3 R2, R2, R2 &|| mpyf R0, R0, R0 & addf3 R2, R2, R2 &|| mpyf R0, R0 & addf3 R2, R2, R2 &|| mpyf R0 & addf3 R2, R2 &|| mpyf R0, R0 & addf3 R2, R2 &|| mpyf R0 & addf3 R2 &|| mpyf R0 & addf3 R2, R2, R2 &|| mpyf AR0, AR0, R0 & addf3 R0, AR0, R2 &|| mpyf AR0, R0, R0 & addf3 R0, AR0, R2 &|| mpyf R0, AR0, R0 & addf3 AR0, AR1, R2 &|| mpyf R2, R1, R0 & addf3 AR0, R3, R2 &|| mpyf AR0, R1, R0 & addf3 AR0, R0, R2 &|| mpyf R0, AR0, R0 & .endif & .ifdef TEST_C3X & addf_mpyf3_M: & addf R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & addf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & addf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & addf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & addf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & addf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & addf *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addf_mpyf3_M_enh: & addf R2, R2, R2 &|| mpyf3 R0, R0, R0 & addf R2, R2, R2 &|| mpyf3 R0, R0 & addf R2, R2, R2 &|| mpyf3 R0 & addf R2, R2 &|| mpyf3 R0, R0 & addf R2, R2 &|| mpyf3 R0 & addf R2 &|| mpyf3 R0 & addf R2, R2, R2 &|| mpyf3 AR0, AR0, R0 & addf R0, AR0, R2 &|| mpyf3 AR0, R0, R0 & addf R0, AR0, R2 &|| mpyf3 R0, AR0, R0 & addf AR0, AR1, R2 &|| mpyf3 R2, R1, R0 & addf AR0, R3, R2 &|| mpyf3 AR0, R1, R0 & addf AR0, R0, R2 &|| mpyf3 R0, AR0, R0 & .endif & .ifdef TEST_C3X & addf3_mpyf3_M: & addf3 R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf3 R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & addf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf3 R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & addf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & addf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & addf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & addf3 *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & addf3 *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addf3_mpyf3_M_enh: & addf3 R2, R2, R2 &|| mpyf3 R0, R0, R0 & addf3 R2, R2, R2 &|| mpyf3 R0, R0 & addf3 R2, R2, R2 &|| mpyf3 R0 & addf3 R2, R2 &|| mpyf3 R0, R0 & addf3 R2, R2 &|| mpyf3 R0 & addf3 R2 &|| mpyf3 R0 & addf3 R2, R2, R2 &|| mpyf3 AR0, AR0, R0 & addf3 R0, AR0, R2 &|| mpyf3 AR0, R0, R0 & addf3 R0, AR0, R2 &|| mpyf3 R0, AR0, R0 & addf3 AR0, AR1, R2 &|| mpyf3 R2, R1, R0 & addf3 AR0, R3, R2 &|| mpyf3 AR0, R1, R0 & addf3 AR0, R0, R2 &|| mpyf3 R0, AR0, R0 & .endif
+ .ifdef TEST_C3X & mpyf_stf_QC: & mpyf *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & mpyf *+AR0(1), R0 &|| stf R1, *+AR1(1) & mpyf R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| mpyf *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| mpyf *+AR0(1), R0 & stf R1, *+AR1(1) &|| mpyf R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & mpyf_stf_QC_enh: & mpyf AR0, R1, R0 &|| stf R1, *+AR1(1) & mpyf R2, R1, R0 &|| stf R1, *+AR1(1) & mpyf R1, R0 &|| stf R1, *+AR1(1) & mpyf R0 &|| stf R1, *+AR1(1) & mpyf R0, AR0, R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| mpyf AR0, R1, R0 & stf R1, *+AR1(1) &|| mpyf R2, R1, R0 & stf R1, *+AR1(1) &|| mpyf R1, R0 & stf R1, *+AR1(1) &|| mpyf R0 & stf R1, *+AR1(1) &|| mpyf R0, AR0, R0 & .endif & .ifdef TEST_C3X & mpyf3_stf_QC: & mpyf3 *+AR0(1), R1, R0 &|| stf R1, *+AR1(1) & mpyf3 *+AR0(1), R0 &|| stf R1, *+AR1(1) & mpyf3 R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| mpyf3 *+AR0(1), R1, R0 & stf R1, *+AR1(1) &|| mpyf3 *+AR0(1), R0 & stf R1, *+AR1(1) &|| mpyf3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & mpyf3_stf_QC_enh: & mpyf3 AR0, R1, R0 &|| stf R1, *+AR1(1) & mpyf3 R2, R1, R0 &|| stf R1, *+AR1(1) & mpyf3 R1, R0 &|| stf R1, *+AR1(1) & mpyf3 R0 &|| stf R1, *+AR1(1) & mpyf3 R0, AR0, R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| mpyf3 AR0, R1, R0 & stf R1, *+AR1(1) &|| mpyf3 R2, R1, R0 & stf R1, *+AR1(1) &|| mpyf3 R1, R0 & stf R1, *+AR1(1) &|| mpyf3 R0 & stf R1, *+AR1(1) &|| mpyf3 R0, AR0, R0 & .endif
+ .ifdef TEST_C3X & mpyf_subf_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| subf R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| subf R0, R2 & mpyf *+AR0(1), R0, R0 &|| subf R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| subf *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| subf *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| subf *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| subf *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf_subf_M_enh: & mpyf R0, R0, R0 &|| subf R2, R2, R2 & mpyf R0, R0 &|| subf R2, R2, R2 & mpyf R0 &|| subf R2, R2, R2 & mpyf R0, R0 &|| subf R2, R2 & mpyf R0 &|| subf R2, R2 & mpyf R0 &|| subf R2 & mpyf AR0, AR0, R0 &|| subf R2, R2, R2 & mpyf AR0, R0, R0 &|| subf R0, AR0, R2 & mpyf R0, AR0, R0 &|| subf R0, AR0, R2 & mpyf R2, R1, R0 &|| subf AR0, AR1, R2 & mpyf AR0, R1, R0 &|| subf AR0, R3, R2 & mpyf R0, AR0, R0 &|| subf AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyf3_subf_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| subf R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| subf *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| subf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| subf *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| subf *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| subf *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf3_subf_M_enh: & mpyf3 R0, R0, R0 &|| subf R2, R2, R2 & mpyf3 R0, R0 &|| subf R2, R2, R2 & mpyf3 R0 &|| subf R2, R2, R2 & mpyf3 R0, R0 &|| subf R2, R2 & mpyf3 R0 &|| subf R2, R2 & mpyf3 R0 &|| subf R2 & mpyf3 AR0, AR0, R0 &|| subf R2, R2, R2 & mpyf3 AR0, R0, R0 &|| subf R0, AR0, R2 & mpyf3 R0, AR0, R0 &|| subf R0, AR0, R2 & mpyf3 R2, R1, R0 &|| subf AR0, AR1, R2 & mpyf3 AR0, R1, R0 &|| subf AR0, R3, R2 & mpyf3 R0, AR0, R0 &|| subf AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyf_subf3_M: & mpyf *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R1, R2 & mpyf *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R2 & mpyf *+AR0(1), R0, R0 &|| subf3 R0, *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf R2, R1, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf R2, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R0 &|| subf3 *+AR1(1), R3, R2 & mpyf *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R2 & mpyf *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & mpyf R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R0, R2 & mpyf R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf_subf3_M_enh: & mpyf R0, R0, R0 &|| subf3 R2, R2, R2 & mpyf R0, R0 &|| subf3 R2, R2, R2 & mpyf R0 &|| subf3 R2, R2, R2 & mpyf R0, R0 &|| subf3 R2, R2 & mpyf R0 &|| subf3 R2, R2 & mpyf R0 &|| subf3 R2 & mpyf AR0, AR0, R0 &|| subf3 R2, R2, R2 & mpyf AR0, R0, R0 &|| subf3 R0, AR0, R2 & mpyf R0, AR0, R0 &|| subf3 R0, AR0, R2 & mpyf R2, R1, R0 &|| subf3 AR0, AR1, R2 & mpyf AR0, R1, R0 &|| subf3 AR0, R3, R2 & mpyf R0, AR0, R0 &|| subf3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyf3_subf3_M: & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R1, R2 & mpyf3 *+AR0(1), *+AR1(1), R0 &|| subf3 R0, R2 & mpyf3 *+AR0(1), R0, R0 &|| subf3 R0, *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf3 R0, *+AR1(1), R2 & mpyf3 R2, R1, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf3 R2, R0 &|| subf3 *+AR0(1), *+AR1(1), R2 & mpyf3 *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R0 &|| subf3 *+AR1(1), R3, R2 & mpyf3 *+AR0(1), R1, R0 &|| subf3 *+AR1(1), R2 & mpyf3 *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & mpyf3 R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R0, R2 & mpyf3 R0, *+AR0(1), R0 &|| subf3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyf3_subf3_M_enh: & mpyf3 R0, R0, R0 &|| subf3 R2, R2, R2 & mpyf3 R0, R0 &|| subf3 R2, R2, R2 & mpyf3 R0 &|| subf3 R2, R2, R2 & mpyf3 R0, R0 &|| subf3 R2, R2 & mpyf3 R0 &|| subf3 R2, R2 & mpyf3 R0 &|| subf3 R2 & mpyf3 AR0, AR0, R0 &|| subf3 R2, R2, R2 & mpyf3 AR0, R0, R0 &|| subf3 R0, AR0, R2 & mpyf3 R0, AR0, R0 &|| subf3 R0, AR0, R2 & mpyf3 R2, R1, R0 &|| subf3 AR0, AR1, R2 & mpyf3 AR0, R1, R0 &|| subf3 AR0, R3, R2 & mpyf3 R0, AR0, R0 &|| subf3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & subf_mpyf_M: & subf R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & subf R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & subf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & subf *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & subf *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subf_mpyf_M_enh: & subf R2, R2, R2 &|| mpyf R0, R0, R0 & subf R2, R2, R2 &|| mpyf R0, R0 & subf R2, R2, R2 &|| mpyf R0 & subf R2, R2 &|| mpyf R0, R0 & subf R2, R2 &|| mpyf R0 & subf R2 &|| mpyf R0 & subf R2, R2, R2 &|| mpyf AR0, AR0, R0 & subf R0, AR0, R2 &|| mpyf AR0, R0, R0 & subf R0, AR0, R2 &|| mpyf R0, AR0, R0 & subf AR0, AR1, R2 &|| mpyf R2, R1, R0 & subf AR0, R3, R2 &|| mpyf AR0, R1, R0 & subf AR0, R0, R2 &|| mpyf R0, AR0, R0 & .endif & .ifdef TEST_C3X & subf3_mpyf_M: & subf3 R0, R1, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf3 R0, R2 &|| mpyf *+AR0(1), *+AR1(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0, R0 & subf3 R0, *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R1, R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf R2, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R1, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R1, R0 & subf3 *+AR1(1), R2 &|| mpyf *+AR0(1), R0 & subf3 *+AR1(1), R0, R2 &|| mpyf R0, *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subf3_mpyf_M_enh: & subf3 R2, R2, R2 &|| mpyf R0, R0, R0 & subf3 R2, R2, R2 &|| mpyf R0, R0 & subf3 R2, R2, R2 &|| mpyf R0 & subf3 R2, R2 &|| mpyf R0, R0 & subf3 R2, R2 &|| mpyf R0 & subf3 R2 &|| mpyf R0 & subf3 R2, R2, R2 &|| mpyf AR0, AR0, R0 & subf3 R0, AR0, R2 &|| mpyf AR0, R0, R0 & subf3 R0, AR0, R2 &|| mpyf R0, AR0, R0 & subf3 AR0, AR1, R2 &|| mpyf R2, R1, R0 & subf3 AR0, R3, R2 &|| mpyf AR0, R1, R0 & subf3 AR0, R0, R2 &|| mpyf R0, AR0, R0 & .endif & .ifdef TEST_C3X & subf_mpyf3_M: & subf R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & subf R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & subf *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & subf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & subf *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & subf *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & subf *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subf_mpyf3_M_enh: & subf R2, R2, R2 &|| mpyf3 R0, R0, R0 & subf R2, R2, R2 &|| mpyf3 R0, R0 & subf R2, R2, R2 &|| mpyf3 R0 & subf R2, R2 &|| mpyf3 R0, R0 & subf R2, R2 &|| mpyf3 R0 & subf R2 &|| mpyf3 R0 & subf R2, R2, R2 &|| mpyf3 AR0, AR0, R0 & subf R0, AR0, R2 &|| mpyf3 AR0, R0, R0 & subf R0, AR0, R2 &|| mpyf3 R0, AR0, R0 & subf AR0, AR1, R2 &|| mpyf3 R2, R1, R0 & subf AR0, R3, R2 &|| mpyf3 AR0, R1, R0 & subf AR0, R0, R2 &|| mpyf3 R0, AR0, R0 & .endif & .ifdef TEST_C3X & subf3_mpyf3_M: & subf3 R0, R1, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf3 R0, R2 &|| mpyf3 *+AR0(1), *+AR1(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0, R0 & subf3 R0, *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf3 R0, *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R1, R0 & subf3 *+AR0(1), *+AR1(1), R2 &|| mpyf3 R2, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R1, R0 & subf3 *+AR1(1), R3, R2 &|| mpyf3 *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R1, R0 & subf3 *+AR1(1), R2 &|| mpyf3 *+AR0(1), R0 & subf3 *+AR1(1), R0, R2 &|| mpyf3 R0, *+AR0(1), R0 & subf3 *+AR1(1), R2 &|| mpyf3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subf3_mpyf3_M_enh: & subf3 R2, R2, R2 &|| mpyf3 R0, R0, R0 & subf3 R2, R2, R2 &|| mpyf3 R0, R0 & subf3 R2, R2, R2 &|| mpyf3 R0 & subf3 R2, R2 &|| mpyf3 R0, R0 & subf3 R2, R2 &|| mpyf3 R0 & subf3 R2 &|| mpyf3 R0 & subf3 R2, R2, R2 &|| mpyf3 AR0, AR0, R0 & subf3 R0, AR0, R2 &|| mpyf3 AR0, R0, R0 & subf3 R0, AR0, R2 &|| mpyf3 R0, AR0, R0 & subf3 AR0, AR1, R2 &|| mpyf3 R2, R1, R0 & subf3 AR0, R3, R2 &|| mpyf3 AR0, R1, R0 & subf3 AR0, R0, R2 &|| mpyf3 R0, AR0, R0 & .endif
+ .ifdef TEST_C3X & mpyi_A: & mpyi AR1, AR0 & mpyi AR0 & mpyi @start, AR0 & mpyi *+AR0(5), AR0 & mpyi -5, AR0 & .endif
+ .ifdef TEST_C3X & mpyi_TC: & mpyi AR2, AR1, AR0 & mpyi AR1, AR0 & mpyi AR1, *+AR0(1), AR0 & mpyi *+AR0(1), AR1, AR0 & mpyi *+AR0(1), AR0 & mpyi *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & mpyi_TC_c4x: & mpyi -5, AR1, AR0 & mpyi -5, AR0 & mpyi AR1, -5, AR0 & mpyi *+AR0(5), AR1, AR0 & mpyi *+AR0(5), AR0 & mpyi AR1, *+AR0(5), AR0 & mpyi -5, *+AR0(5), AR0 & mpyi *+AR0(5), -5, AR0 & mpyi *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & mpyi3_TC: & mpyi3 AR2, AR1, AR0 & mpyi3 AR1, AR0 & mpyi3 AR1, *+AR0(1), AR0 & mpyi3 *+AR0(1), AR1, AR0 & mpyi3 *+AR0(1), AR0 & mpyi3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & mpyi3_TC_c4x: & mpyi3 -5, AR1, AR0 & mpyi3 -5, AR0 & mpyi3 AR1, -5, AR0 & mpyi3 *+AR0(5), AR1, AR0 & mpyi3 *+AR0(5), AR0 & mpyi3 AR1, *+AR0(5), AR0 & mpyi3 -5, *+AR0(5), AR0 & mpyi3 *+AR0(5), -5, AR0 & mpyi3 *+AR0(5), *+AR1(5), AR0 & .endif
+ .ifdef TEST_C3X & mpyi_addi_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| addi R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| addi R0, R2 & mpyi *+AR0(1), R0, R0 &|| addi R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| addi *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| addi *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| addi *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| addi *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi_addi_M_enh: & mpyi R0, R0, R0 &|| addi R2, R2, R2 & mpyi R0, R0 &|| addi R2, R2, R2 & mpyi R0 &|| addi R2, R2, R2 & mpyi R0, R0 &|| addi R2, R2 & mpyi R0 &|| addi R2, R2 & mpyi R0 &|| addi R2 & mpyi AR0, AR0, R0 &|| addi R2, R2, R2 & mpyi AR0, R0, R0 &|| addi R0, AR0, R2 & mpyi R0, AR0, R0 &|| addi R0, AR0, R2 & mpyi R2, R1, R0 &|| addi AR0, AR1, R2 & mpyi AR0, R1, R0 &|| addi AR0, R3, R2 & mpyi R0, AR0, R0 &|| addi AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyi3_addi_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| addi R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| addi *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| addi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| addi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| addi *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| addi *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi3_addi_M_enh: & mpyi3 R0, R0, R0 &|| addi R2, R2, R2 & mpyi3 R0, R0 &|| addi R2, R2, R2 & mpyi3 R0 &|| addi R2, R2, R2 & mpyi3 R0, R0 &|| addi R2, R2 & mpyi3 R0 &|| addi R2, R2 & mpyi3 R0 &|| addi R2 & mpyi3 AR0, AR0, R0 &|| addi R2, R2, R2 & mpyi3 AR0, R0, R0 &|| addi R0, AR0, R2 & mpyi3 R0, AR0, R0 &|| addi R0, AR0, R2 & mpyi3 R2, R1, R0 &|| addi AR0, AR1, R2 & mpyi3 AR0, R1, R0 &|| addi AR0, R3, R2 & mpyi3 R0, AR0, R0 &|| addi AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyi_addi3_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R2 & mpyi *+AR0(1), R0, R0 &|| addi3 R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| addi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi_addi3_M_enh: & mpyi R0, R0, R0 &|| addi3 R2, R2, R2 & mpyi R0, R0 &|| addi3 R2, R2, R2 & mpyi R0 &|| addi3 R2, R2, R2 & mpyi R0, R0 &|| addi3 R2, R2 & mpyi R0 &|| addi3 R2, R2 & mpyi R0 &|| addi3 R2 & mpyi AR0, AR0, R0 &|| addi3 R2, R2, R2 & mpyi AR0, R0, R0 &|| addi3 R0, AR0, R2 & mpyi R0, AR0, R0 &|| addi3 R0, AR0, R2 & mpyi R2, R1, R0 &|| addi3 AR0, AR1, R2 & mpyi AR0, R1, R0 &|| addi3 AR0, R3, R2 & mpyi R0, AR0, R0 &|| addi3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyi3_addi3_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| addi3 R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| addi3 R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi3 R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| addi3 *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| addi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| addi3 *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| addi3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi3_addi3_M_enh: & mpyi3 R0, R0, R0 &|| addi3 R2, R2, R2 & mpyi3 R0, R0 &|| addi3 R2, R2, R2 & mpyi3 R0 &|| addi3 R2, R2, R2 & mpyi3 R0, R0 &|| addi3 R2, R2 & mpyi3 R0 &|| addi3 R2, R2 & mpyi3 R0 &|| addi3 R2 & mpyi3 AR0, AR0, R0 &|| addi3 R2, R2, R2 & mpyi3 AR0, R0, R0 &|| addi3 R0, AR0, R2 & mpyi3 R0, AR0, R0 &|| addi3 R0, AR0, R2 & mpyi3 R2, R1, R0 &|| addi3 AR0, AR1, R2 & mpyi3 AR0, R1, R0 &|| addi3 AR0, R3, R2 & mpyi3 R0, AR0, R0 &|| addi3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & addi_mpyi_M: & addi R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & addi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & addi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & addi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & addi *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addi_mpyi_M_enh: & addi R2, R2, R2 &|| mpyi R0, R0, R0 & addi R2, R2, R2 &|| mpyi R0, R0 & addi R2, R2, R2 &|| mpyi R0 & addi R2, R2 &|| mpyi R0, R0 & addi R2, R2 &|| mpyi R0 & addi R2 &|| mpyi R0 & addi R2, R2, R2 &|| mpyi AR0, AR0, R0 & addi R0, AR0, R2 &|| mpyi AR0, R0, R0 & addi R0, AR0, R2 &|| mpyi R0, AR0, R0 & addi AR0, AR1, R2 &|| mpyi R2, R1, R0 & addi AR0, R3, R2 &|| mpyi AR0, R1, R0 & addi AR0, R0, R2 &|| mpyi R0, AR0, R0 & .endif & .ifdef TEST_C3X & addi3_mpyi_M: & addi3 R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi3 R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & addi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & addi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & addi3 *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addi3_mpyi_M_enh: & addi3 R2, R2, R2 &|| mpyi R0, R0, R0 & addi3 R2, R2, R2 &|| mpyi R0, R0 & addi3 R2, R2, R2 &|| mpyi R0 & addi3 R2, R2 &|| mpyi R0, R0 & addi3 R2, R2 &|| mpyi R0 & addi3 R2 &|| mpyi R0 & addi3 R2, R2, R2 &|| mpyi AR0, AR0, R0 & addi3 R0, AR0, R2 &|| mpyi AR0, R0, R0 & addi3 R0, AR0, R2 &|| mpyi R0, AR0, R0 & addi3 AR0, AR1, R2 &|| mpyi R2, R1, R0 & addi3 AR0, R3, R2 &|| mpyi AR0, R1, R0 & addi3 AR0, R0, R2 &|| mpyi R0, AR0, R0 & .endif & .ifdef TEST_C3X & addi_mpyi3_M: & addi R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & addi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & addi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & addi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & addi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & addi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & addi *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addi_mpyi3_M_enh: & addi R2, R2, R2 &|| mpyi3 R0, R0, R0 & addi R2, R2, R2 &|| mpyi3 R0, R0 & addi R2, R2, R2 &|| mpyi3 R0 & addi R2, R2 &|| mpyi3 R0, R0 & addi R2, R2 &|| mpyi3 R0 & addi R2 &|| mpyi3 R0 & addi R2, R2, R2 &|| mpyi3 AR0, AR0, R0 & addi R0, AR0, R2 &|| mpyi3 AR0, R0, R0 & addi R0, AR0, R2 &|| mpyi3 R0, AR0, R0 & addi AR0, AR1, R2 &|| mpyi3 R2, R1, R0 & addi AR0, R3, R2 &|| mpyi3 AR0, R1, R0 & addi AR0, R0, R2 &|| mpyi3 R0, AR0, R0 & .endif & .ifdef TEST_C3X & addi3_mpyi3_M: & addi3 R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi3 R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & addi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi3 R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & addi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & addi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & addi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & addi3 *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & addi3 *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & addi3_mpyi3_M_enh: & addi3 R2, R2, R2 &|| mpyi3 R0, R0, R0 & addi3 R2, R2, R2 &|| mpyi3 R0, R0 & addi3 R2, R2, R2 &|| mpyi3 R0 & addi3 R2, R2 &|| mpyi3 R0, R0 & addi3 R2, R2 &|| mpyi3 R0 & addi3 R2 &|| mpyi3 R0 & addi3 R2, R2, R2 &|| mpyi3 AR0, AR0, R0 & addi3 R0, AR0, R2 &|| mpyi3 AR0, R0, R0 & addi3 R0, AR0, R2 &|| mpyi3 R0, AR0, R0 & addi3 AR0, AR1, R2 &|| mpyi3 R2, R1, R0 & addi3 AR0, R3, R2 &|| mpyi3 AR0, R1, R0 & addi3 AR0, R0, R2 &|| mpyi3 R0, AR0, R0 & .endif
+ .ifdef TEST_C3X & mpyi_sti_QC: & mpyi *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & mpyi *+AR0(1), R0 &|| sti R1, *+AR1(1) & mpyi R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| mpyi *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| mpyi *+AR0(1), R0 & sti R1, *+AR1(1) &|| mpyi R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & mpyi_sti_QC_enh: & mpyi AR0, R1, R0 &|| sti R1, *+AR1(1) & mpyi R2, R1, R0 &|| sti R1, *+AR1(1) & mpyi R1, R0 &|| sti R1, *+AR1(1) & mpyi R0 &|| sti R1, *+AR1(1) & mpyi R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| mpyi AR0, R1, R0 & sti R1, *+AR1(1) &|| mpyi R2, R1, R0 & sti R1, *+AR1(1) &|| mpyi R1, R0 & sti R1, *+AR1(1) &|| mpyi R0 & sti R1, *+AR1(1) &|| mpyi R0, AR0, R0 & .endif & .ifdef TEST_C3X & mpyi3_sti_QC: & mpyi3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & mpyi3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & mpyi3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| mpyi3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| mpyi3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| mpyi3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & mpyi3_sti_QC_enh: & mpyi3 AR0, R1, R0 &|| sti R1, *+AR1(1) & mpyi3 R2, R1, R0 &|| sti R1, *+AR1(1) & mpyi3 R1, R0 &|| sti R1, *+AR1(1) & mpyi3 R0 &|| sti R1, *+AR1(1) & mpyi3 R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| mpyi3 AR0, R1, R0 & sti R1, *+AR1(1) &|| mpyi3 R2, R1, R0 & sti R1, *+AR1(1) &|| mpyi3 R1, R0 & sti R1, *+AR1(1) &|| mpyi3 R0 & sti R1, *+AR1(1) &|| mpyi3 R0, AR0, R0 & .endif
+ .ifdef TEST_C3X & mpyi_subi_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| subi R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| subi R0, R2 & mpyi *+AR0(1), R0, R0 &|| subi R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| subi *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| subi *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| subi *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| subi *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi_subi_M_enh: & mpyi R0, R0, R0 &|| subi R2, R2, R2 & mpyi R0, R0 &|| subi R2, R2, R2 & mpyi R0 &|| subi R2, R2, R2 & mpyi R0, R0 &|| subi R2, R2 & mpyi R0 &|| subi R2, R2 & mpyi R0 &|| subi R2 & mpyi AR0, AR0, R0 &|| subi R2, R2, R2 & mpyi AR0, R0, R0 &|| subi R0, AR0, R2 & mpyi R0, AR0, R0 &|| subi R0, AR0, R2 & mpyi R2, R1, R0 &|| subi AR0, AR1, R2 & mpyi AR0, R1, R0 &|| subi AR0, R3, R2 & mpyi R0, AR0, R0 &|| subi AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyi3_subi_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| subi R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| subi *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| subi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| subi *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| subi *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| subi *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi3_subi_M_enh: & mpyi3 R0, R0, R0 &|| subi R2, R2, R2 & mpyi3 R0, R0 &|| subi R2, R2, R2 & mpyi3 R0 &|| subi R2, R2, R2 & mpyi3 R0, R0 &|| subi R2, R2 & mpyi3 R0 &|| subi R2, R2 & mpyi3 R0 &|| subi R2 & mpyi3 AR0, AR0, R0 &|| subi R2, R2, R2 & mpyi3 AR0, R0, R0 &|| subi R0, AR0, R2 & mpyi3 R0, AR0, R0 &|| subi R0, AR0, R2 & mpyi3 R2, R1, R0 &|| subi AR0, AR1, R2 & mpyi3 AR0, R1, R0 &|| subi AR0, R3, R2 & mpyi3 R0, AR0, R0 &|| subi AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyi_subi3_M: & mpyi *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R1, R2 & mpyi *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R2 & mpyi *+AR0(1), R0, R0 &|| subi3 R0, *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi R2, R1, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi R2, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R0 &|| subi3 *+AR1(1), R3, R2 & mpyi *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R2 & mpyi *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & mpyi R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R0, R2 & mpyi R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi_subi3_M_enh: & mpyi R0, R0, R0 &|| subi3 R2, R2, R2 & mpyi R0, R0 &|| subi3 R2, R2, R2 & mpyi R0 &|| subi3 R2, R2, R2 & mpyi R0, R0 &|| subi3 R2, R2 & mpyi R0 &|| subi3 R2, R2 & mpyi R0 &|| subi3 R2 & mpyi AR0, AR0, R0 &|| subi3 R2, R2, R2 & mpyi AR0, R0, R0 &|| subi3 R0, AR0, R2 & mpyi R0, AR0, R0 &|| subi3 R0, AR0, R2 & mpyi R2, R1, R0 &|| subi3 AR0, AR1, R2 & mpyi AR0, R1, R0 &|| subi3 AR0, R3, R2 & mpyi R0, AR0, R0 &|| subi3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & mpyi3_subi3_M: & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R1, R2 & mpyi3 *+AR0(1), *+AR1(1), R0 &|| subi3 R0, R2 & mpyi3 *+AR0(1), R0, R0 &|| subi3 R0, *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi3 R0, *+AR1(1), R2 & mpyi3 R2, R1, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi3 R2, R0 &|| subi3 *+AR0(1), *+AR1(1), R2 & mpyi3 *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R0 &|| subi3 *+AR1(1), R3, R2 & mpyi3 *+AR0(1), R1, R0 &|| subi3 *+AR1(1), R2 & mpyi3 *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & mpyi3 R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R0, R2 & mpyi3 R0, *+AR0(1), R0 &|| subi3 *+AR1(1), R2 & .endif & .ifdef TEST_ENH & mpyi3_subi3_M_enh: & mpyi3 R0, R0, R0 &|| subi3 R2, R2, R2 & mpyi3 R0, R0 &|| subi3 R2, R2, R2 & mpyi3 R0 &|| subi3 R2, R2, R2 & mpyi3 R0, R0 &|| subi3 R2, R2 & mpyi3 R0 &|| subi3 R2, R2 & mpyi3 R0 &|| subi3 R2 & mpyi3 AR0, AR0, R0 &|| subi3 R2, R2, R2 & mpyi3 AR0, R0, R0 &|| subi3 R0, AR0, R2 & mpyi3 R0, AR0, R0 &|| subi3 R0, AR0, R2 & mpyi3 R2, R1, R0 &|| subi3 AR0, AR1, R2 & mpyi3 AR0, R1, R0 &|| subi3 AR0, R3, R2 & mpyi3 R0, AR0, R0 &|| subi3 AR0, R0, R2 & .endif & .ifdef TEST_C3X & subi_mpyi_M: & subi R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & subi R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & subi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & subi *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & subi *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subi_mpyi_M_enh: & subi R2, R2, R2 &|| mpyi R0, R0, R0 & subi R2, R2, R2 &|| mpyi R0, R0 & subi R2, R2, R2 &|| mpyi R0 & subi R2, R2 &|| mpyi R0, R0 & subi R2, R2 &|| mpyi R0 & subi R2 &|| mpyi R0 & subi R2, R2, R2 &|| mpyi AR0, AR0, R0 & subi R0, AR0, R2 &|| mpyi AR0, R0, R0 & subi R0, AR0, R2 &|| mpyi R0, AR0, R0 & subi AR0, AR1, R2 &|| mpyi R2, R1, R0 & subi AR0, R3, R2 &|| mpyi AR0, R1, R0 & subi AR0, R0, R2 &|| mpyi R0, AR0, R0 & .endif & .ifdef TEST_C3X & subi3_mpyi_M: & subi3 R0, R1, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi3 R0, R2 &|| mpyi *+AR0(1), *+AR1(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0, R0 & subi3 R0, *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R1, R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi R2, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R1, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R1, R0 & subi3 *+AR1(1), R2 &|| mpyi *+AR0(1), R0 & subi3 *+AR1(1), R0, R2 &|| mpyi R0, *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subi3_mpyi_M_enh: & subi3 R2, R2, R2 &|| mpyi R0, R0, R0 & subi3 R2, R2, R2 &|| mpyi R0, R0 & subi3 R2, R2, R2 &|| mpyi R0 & subi3 R2, R2 &|| mpyi R0, R0 & subi3 R2, R2 &|| mpyi R0 & subi3 R2 &|| mpyi R0 & subi3 R2, R2, R2 &|| mpyi AR0, AR0, R0 & subi3 R0, AR0, R2 &|| mpyi AR0, R0, R0 & subi3 R0, AR0, R2 &|| mpyi R0, AR0, R0 & subi3 AR0, AR1, R2 &|| mpyi R2, R1, R0 & subi3 AR0, R3, R2 &|| mpyi AR0, R1, R0 & subi3 AR0, R0, R2 &|| mpyi R0, AR0, R0 & .endif & .ifdef TEST_C3X & subi_mpyi3_M: & subi R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & subi R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & subi *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & subi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & subi *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & subi *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & subi *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subi_mpyi3_M_enh: & subi R2, R2, R2 &|| mpyi3 R0, R0, R0 & subi R2, R2, R2 &|| mpyi3 R0, R0 & subi R2, R2, R2 &|| mpyi3 R0 & subi R2, R2 &|| mpyi3 R0, R0 & subi R2, R2 &|| mpyi3 R0 & subi R2 &|| mpyi3 R0 & subi R2, R2, R2 &|| mpyi3 AR0, AR0, R0 & subi R0, AR0, R2 &|| mpyi3 AR0, R0, R0 & subi R0, AR0, R2 &|| mpyi3 R0, AR0, R0 & subi AR0, AR1, R2 &|| mpyi3 R2, R1, R0 & subi AR0, R3, R2 &|| mpyi3 AR0, R1, R0 & subi AR0, R0, R2 &|| mpyi3 R0, AR0, R0 & .endif & .ifdef TEST_C3X & subi3_mpyi3_M: & subi3 R0, R1, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi3 R0, R2 &|| mpyi3 *+AR0(1), *+AR1(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0, R0 & subi3 R0, *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi3 R0, *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R1, R0 & subi3 *+AR0(1), *+AR1(1), R2 &|| mpyi3 R2, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R1, R0 & subi3 *+AR1(1), R3, R2 &|| mpyi3 *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R1, R0 & subi3 *+AR1(1), R2 &|| mpyi3 *+AR0(1), R0 & subi3 *+AR1(1), R0, R2 &|| mpyi3 R0, *+AR0(1), R0 & subi3 *+AR1(1), R2 &|| mpyi3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subi3_mpyi3_M_enh: & subi3 R2, R2, R2 &|| mpyi3 R0, R0, R0 & subi3 R2, R2, R2 &|| mpyi3 R0, R0 & subi3 R2, R2, R2 &|| mpyi3 R0 & subi3 R2, R2 &|| mpyi3 R0, R0 & subi3 R2, R2 &|| mpyi3 R0 & subi3 R2 &|| mpyi3 R0 & subi3 R2, R2, R2 &|| mpyi3 AR0, AR0, R0 & subi3 R0, AR0, R2 &|| mpyi3 AR0, R0, R0 & subi3 R0, AR0, R2 &|| mpyi3 R0, AR0, R0 & subi3 AR0, AR1, R2 &|| mpyi3 R2, R1, R0 & subi3 AR0, R3, R2 &|| mpyi3 AR0, R1, R0 & subi3 AR0, R0, R2 &|| mpyi3 R0, AR0, R0 & .endif
+ .ifdef TEST_C3X & negb_A: & negb AR1, AR0 & negb AR0 & negb @start, AR0 & negb *+AR0(5), AR0 & negb -5, AR0 & .endif
+ .ifdef TEST_C3X & negf_B: & negf R1, R0 & negf R0 & negf @start, R0 & negf *+AR0(5), R0 & negf 3.5, R0 & .endif
+ .ifdef TEST_C3X & negf_stf_P: & negf *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| negf *+AR0(1), R0 & .endif & .ifdef TEST_ENH & negf_stf_P_enh: & negf R0, R0 &|| stf R1, *+AR1(1) & negf R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| negf R0, R0 & stf R1, *+AR1(1) &|| negf R0 & .endif
+ .ifdef TEST_C3X & negi_A: & negi AR1, AR0 & negi AR0 & negi @start, AR0 & negi *+AR0(5), AR0 & negi -5, AR0 & .endif
+ .ifdef TEST_C3X & negi_sti_P: & negi *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| negi *+AR0(1), R0 & .endif & .ifdef TEST_ENH & negi_sti_P_enh: & negi R0, R0 &|| sti R1, *+AR1(1) & negi R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| negi R0, R0 & sti R1, *+AR1(1) &|| negi R0 & .endif
+ .ifdef TEST_C3X & nop_A2: & nop AR0 & nop *+AR0(5) & nop & .endif
+ .ifdef TEST_C3X & norm_B: & norm R1, R0 & norm R0 & norm @start, R0 & norm *+AR0(5), R0 & norm 3.5, R0 & .endif
+ .ifdef TEST_C3X & not_AU: & not AR1, AR0 & not AR0 & not @start, AR0 & not *+AR0(5), AR0 & not 5, AR0 & .endif
+ .ifdef TEST_C3X & not_sti_P: & not *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| not *+AR0(1), R0 & .endif & .ifdef TEST_ENH & not_sti_P_enh: & not R0, R0 &|| sti R1, *+AR1(1) & not R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| not R0, R0 & sti R1, *+AR1(1) &|| not R0 & .endif
+ .ifdef TEST_C3X & or_AU: & or AR1, AR0 & or AR0 & or @start, AR0 & or *+AR0(5), AR0 & or 5, AR0 & .endif
+ .ifdef TEST_C3X & or_TC: & or AR2, AR1, AR0 & or AR1, AR0 & or AR1, *+AR0(1), AR0 & or *+AR0(1), AR1, AR0 & or *+AR0(1), AR0 & or *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & or_TC_c4x: & or -5, AR1, AR0 & or -5, AR0 & or AR1, -5, AR0 & or *+AR0(5), AR1, AR0 & or *+AR0(5), AR0 & or AR1, *+AR0(5), AR0 & or -5, *+AR0(5), AR0 & or *+AR0(5), -5, AR0 & or *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & or3_TC: & or3 AR2, AR1, AR0 & or3 AR1, AR0 & or3 AR1, *+AR0(1), AR0 & or3 *+AR0(1), AR1, AR0 & or3 *+AR0(1), AR0 & or3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & or3_TC_c4x: & or3 -5, AR1, AR0 & or3 -5, AR0 & or3 AR1, -5, AR0 & or3 *+AR0(5), AR1, AR0 & or3 *+AR0(5), AR0 & or3 AR1, *+AR0(5), AR0 & or3 -5, *+AR0(5), AR0 & or3 *+AR0(5), -5, AR0 & or3 *+AR0(5), *+AR1(5), AR0 & .endif
+ .ifdef TEST_C3X & or_sti_QC: & or *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & or *+AR0(1), R0 &|| sti R1, *+AR1(1) & or R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| or *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| or *+AR0(1), R0 & sti R1, *+AR1(1) &|| or R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & or_sti_QC_enh: & or AR0, R1, R0 &|| sti R1, *+AR1(1) & or R2, R1, R0 &|| sti R1, *+AR1(1) & or R1, R0 &|| sti R1, *+AR1(1) & or R0 &|| sti R1, *+AR1(1) & or R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| or AR0, R1, R0 & sti R1, *+AR1(1) &|| or R2, R1, R0 & sti R1, *+AR1(1) &|| or R1, R0 & sti R1, *+AR1(1) &|| or R0 & sti R1, *+AR1(1) &|| or R0, AR0, R0 & .endif & .ifdef TEST_C3X & or3_sti_QC: & or3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & or3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & or3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| or3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| or3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| or3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & or3_sti_QC_enh: & or3 AR0, R1, R0 &|| sti R1, *+AR1(1) & or3 R2, R1, R0 &|| sti R1, *+AR1(1) & or3 R1, R0 &|| sti R1, *+AR1(1) & or3 R0 &|| sti R1, *+AR1(1) & or3 R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| or3 AR0, R1, R0 & sti R1, *+AR1(1) &|| or3 R2, R1, R0 & sti R1, *+AR1(1) &|| or3 R1, R0 & sti R1, *+AR1(1) &|| or3 R0 & sti R1, *+AR1(1) &|| or3 R0, AR0, R0 & .endif
+ .ifdef TEST_C3X & pop_R: & pop AR0 & .endif
+ .ifdef TEST_C3X & popf_RF: & popf F0 & .endif
+ .ifdef TEST_C3X & push_R: & push AR0 & .endif
+ .ifdef TEST_C3X & pushf_RF: & pushf F0 & .endif
+ .ifdef TEST_C3X
reti_Z: retiC
reti
rets_Z: retsC
rets
- rnd_B: & rnd R1, R0 & rnd R0 & rnd @start, R0 & rnd *+AR0(5), R0 & rnd 3.5, R0
- rol_R: & rol AR0
- rolc_R: & rolc AR0
- ror_R: & ror AR0
- rorc_R: & rorc AR0
+ .endif
+ .ifdef TEST_C3X & rnd_B: & rnd R1, R0 & rnd R0 & rnd @start, R0 & rnd *+AR0(5), R0 & rnd 3.5, R0 & .endif
+ .ifdef TEST_C3X & rol_R: & rol AR0 & .endif
+ .ifdef TEST_C3X & rolc_R: & rolc AR0 & .endif
+ .ifdef TEST_C3X & ror_R: & ror AR0 & .endif
+ .ifdef TEST_C3X & rorc_R: & rorc AR0 & .endif
+ .ifdef TEST_C3X
rptb_I2: rptb start
- rpts_A3: & rpts AR1 & rpts @start & rpts *+AR0(5) & rpts 5
+ .endif
+ .ifdef TEST_C3X & rpts_A3: & rpts AR1 & rpts @start & rpts *+AR0(5) & rpts 5 & .endif
+ .ifdef TEST_C3X
sigi_Z: sigi
- stf_B7: & stf R0, @start & stf R0, *+AR0(5)
- stf_LS: & stf R0, *+AR0(1) &|| stf R1, *+AR1(1) & stf2 R0, *+AR0(1) &|| stf1 R1, *+AR1(1) & stf1 R1, *+AR1(1) &|| stf2 R0, *+AR0(1)
- stfi_B7: & stfi R0, @start & stfi R0, *+AR0(5)
- sti_A7: & sti AR0, @start & sti AR0, *+AR0(5)
- sti_LS: & sti R0, *+AR0(1) &|| sti R1, *+AR1(1) & sti2 R0, *+AR0(1) &|| sti1 R1, *+AR1(1) & sti1 R1, *+AR1(1) &|| sti2 R0, *+AR0(1)
- stii_A7: & stii AR0, @start & stii AR0, *+AR0(5)
- subb_A: & subb AR1, AR0 & subb AR0 & subb @start, AR0 & subb *+AR0(5), AR0 & subb -5, AR0
- subb_T: & subb AR2, AR1, AR0 & subb AR1, AR0 & subb AR1, *+AR0(1), AR0 & subb *+AR0(1), AR1, AR0 & subb *+AR0(1), AR0 & subb *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & subb 5, AR1, AR0 & subb 5, AR0 & subb *+AR0(5), AR1, AR0 & subb *+AR0(5), AR0 & subb 5, *+AR0(5), AR0 & subb *+AR0(5), *+AR1(5), AR0 & .endif & subb3_T: & subb3 AR2, AR1, AR0 & subb3 AR1, AR0 & subb3 AR1, *+AR0(1), AR0 & subb3 *+AR0(1), AR1, AR0 & subb3 *+AR0(1), AR0 & subb3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & subb3 -5, AR1, AR0 & subb3 -5, AR0 & subb3 *+AR0(5), AR1, AR0 & subb3 *+AR0(5), AR0 & subb3 -5, *+AR0(5), AR0 & subb3 *+AR0(5), *+AR1(5), AR0 & .endif
- subc_A: & subc AR1, AR0 & subc AR0 & subc @start, AR0 & subc *+AR0(5), AR0 & subc -5, AR0
- subf_B: & subf R1, R0 & subf R0 & subf @start, R0 & subf *+AR0(5), R0 & subf 3.5, R0
- subf_S: & subf R2, R1, R0 & subf R1, R0 & subf R1, *+AR0(1), R0 & subf *+AR0(1), R1, R0 & subf *+AR0(1), R0 & subf *+AR0(1), *+AR1(1), R0 & .ifdef TEST_C4X & subf *+AR0(5), R1, R0 & subf *+AR0(5), R0 & subf *+AR0(5), *+AR1(5), R0 & .endif & subf3_S: & subf3 R2, R1, R0 & subf3 R1, R0 & subf3 R1, *+AR0(1), R0 & subf3 *+AR0(1), R1, R0 & subf3 *+AR0(1), R0 & subf3 *+AR0(1), *+AR1(1), R0 & .ifdef TEST_C4X & subf3 *+AR0(5), R1, R0 & subf3 *+AR0(5), R0 & subf3 *+AR0(5), *+AR1(5), R0 & .endif
- subf_stf_Q: & subf R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| subf R0, *+AR0(1), R0 & subf3_stf_Q: & subf3 R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| subf3 R0, *+AR0(1), R0
- subi_A: & subi AR1, AR0 & subi AR0 & subi @start, AR0 & subi *+AR0(5), AR0 & subi -5, AR0
- subi_T: & subi AR2, AR1, AR0 & subi AR1, AR0 & subi AR1, *+AR0(1), AR0 & subi *+AR0(1), AR1, AR0 & subi *+AR0(1), AR0 & subi *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & subi 5, AR1, AR0 & subi 5, AR0 & subi *+AR0(5), AR1, AR0 & subi *+AR0(5), AR0 & subi 5, *+AR0(5), AR0 & subi *+AR0(5), *+AR1(5), AR0 & .endif & subi3_T: & subi3 AR2, AR1, AR0 & subi3 AR1, AR0 & subi3 AR1, *+AR0(1), AR0 & subi3 *+AR0(1), AR1, AR0 & subi3 *+AR0(1), AR0 & subi3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & subi3 -5, AR1, AR0 & subi3 -5, AR0 & subi3 *+AR0(5), AR1, AR0 & subi3 *+AR0(5), AR0 & subi3 -5, *+AR0(5), AR0 & subi3 *+AR0(5), *+AR1(5), AR0 & .endif
- subi_sti_Q: & subi R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| subi R0, *+AR0(1), R0 & subi3_sti_Q: & subi3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| subi3 R0, *+AR0(1), R0
- subrb_A: & subrb AR1, AR0 & subrb AR0 & subrb @start, AR0 & subrb *+AR0(5), AR0 & subrb -5, AR0
- subrf_B: & subrf R1, R0 & subrf R0 & subrf @start, R0 & subrf *+AR0(5), R0 & subrf 3.5, R0
- subri_A: & subri AR1, AR0 & subri AR0 & subri @start, AR0 & subri *+AR0(5), AR0 & subri -5, AR0
+ .endif
+ .ifdef TEST_C3X & stf_B7: & stf R0, @start & stf R0, *+AR0(5) & .endif
+ .ifdef TEST_C3X & stf_LS: & stf R0, *+AR0(1) &|| stf R1, *+AR1(1) & stf2 R0, *+AR0(1) &|| stf1 R1, *+AR1(1) & stf1 R1, *+AR1(1) &|| stf2 R0, *+AR0(1) & .endif & .ifdef TEST_ENH & stf_LS_enh: & stf R0, R0 &|| stf R1, *+AR1(1) & stf R0 &|| stf R1, *+AR1(1) & stf2 R0, R0 &|| stf1 R1, *+AR1(1) & stf2 R0 &|| stf1 R1, *+AR1(1) & stf1 R1, *+AR1(1) &|| stf2 R0, R0 & stf1 R1, *+AR1(1) &|| stf2 R0 & .endif
+ .ifdef TEST_C3X & stfi_B7: & stfi R0, @start & stfi R0, *+AR0(5) & .endif
+ .ifdef TEST_C3X & sti_A7: & sti AR0, @start & sti AR0, *+AR0(5) & .endif
+ .ifdef TEST_C3X & sti_LS: & sti R0, *+AR0(1) &|| sti R1, *+AR1(1) & sti2 R0, *+AR0(1) &|| sti1 R1, *+AR1(1) & sti1 R1, *+AR1(1) &|| sti2 R0, *+AR0(1) & .endif & .ifdef TEST_ENH & sti_LS_enh: & sti R0, R0 &|| sti R1, *+AR1(1) & sti R0 &|| sti R1, *+AR1(1) & sti2 R0, R0 &|| sti1 R1, *+AR1(1) & sti2 R0 &|| sti1 R1, *+AR1(1) & sti1 R1, *+AR1(1) &|| sti2 R0, R0 & sti1 R1, *+AR1(1) &|| sti2 R0 & .endif
+ .ifdef TEST_C3X & stii_A7: & stii AR0, @start & stii AR0, *+AR0(5) & .endif
+ .ifdef TEST_C3X & subb_A: & subb AR1, AR0 & subb AR0 & subb @start, AR0 & subb *+AR0(5), AR0 & subb -5, AR0 & .endif
+ .ifdef TEST_C3X & subb_T: & subb AR2, AR1, AR0 & subb AR1, AR0 & subb AR1, *+AR0(1), AR0 & subb *+AR0(1), AR1, AR0 & subb *+AR0(1), AR0 & subb *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & subb_T_sc: & subb -5, AR1, AR0 & subb -5, AR0 & subb *+AR0(5), AR1, AR0 & subb *+AR0(5), AR0 & subb -5, *+AR0(5), AR0 & subb *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & subb3_T: & subb3 AR2, AR1, AR0 & subb3 AR1, AR0 & subb3 AR1, *+AR0(1), AR0 & subb3 *+AR0(1), AR1, AR0 & subb3 *+AR0(1), AR0 & subb3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & subb3_T_sc: & subb3 -5, AR1, AR0 & subb3 -5, AR0 & subb3 *+AR0(5), AR1, AR0 & subb3 *+AR0(5), AR0 & subb3 -5, *+AR0(5), AR0 & subb3 *+AR0(5), *+AR1(5), AR0 & .endif
+ .ifdef TEST_C3X & subc_A: & subc AR1, AR0 & subc AR0 & subc @start, AR0 & subc *+AR0(5), AR0 & subc -5, AR0 & .endif
+ .ifdef TEST_C3X & subf_B: & subf R1, R0 & subf R0 & subf @start, R0 & subf *+AR0(5), R0 & subf 3.5, R0 & .endif
+ .ifdef TEST_C3X & subf_S: & subf R2, R1, R0 & subf R1, R0 & subf R1, *+AR0(1), R0 & subf *+AR0(1), R1, R0 & subf *+AR0(1), R0 & subf *+AR0(1), *+AR1(1), R0 & .endif & .ifdef TEST_C4X & subf_S_c4x: & subf *+AR0(5), R1, R0 & subf *+AR0(5), R0 & subf *+AR0(5), *+AR1(5), R0 & .endif & .ifdef TEST_C3X & subf3_S: & subf3 R2, R1, R0 & subf3 R1, R0 & subf3 R1, *+AR0(1), R0 & subf3 *+AR0(1), R1, R0 & subf3 *+AR0(1), R0 & subf3 *+AR0(1), *+AR1(1), R0 & .endif & .ifdef TEST_C4X & subf3_S_c4x: & subf3 *+AR0(5), R1, R0 & subf3 *+AR0(5), R0 & subf3 *+AR0(5), *+AR1(5), R0 & .endif
+ .ifdef TEST_C3X & subf_stf_Q: & subf R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| subf R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subf_stf_Q_enh: & subf R0, R0, R0 &|| stf R1, *+AR1(1) & subf R0, R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| subf R0, R0, R0 & stf R1, *+AR1(1) &|| subf R0, R0 & .endif & .ifdef TEST_C3X & subf3_stf_Q: & subf3 R0, *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| subf3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subf3_stf_Q_enh: & subf3 R0, R0, R0 &|| stf R1, *+AR1(1) & subf3 R0, R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| subf3 R0, R0, R0 & stf R1, *+AR1(1) &|| subf3 R0, R0 & .endif
+ .ifdef TEST_C3X & subi_A: & subi AR1, AR0 & subi AR0 & subi @start, AR0 & subi *+AR0(5), AR0 & subi -5, AR0 & .endif
+ .ifdef TEST_C3X & subi_T: & subi AR2, AR1, AR0 & subi AR1, AR0 & subi AR1, *+AR0(1), AR0 & subi *+AR0(1), AR1, AR0 & subi *+AR0(1), AR0 & subi *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & subi_T_sc: & subi -5, AR1, AR0 & subi -5, AR0 & subi *+AR0(5), AR1, AR0 & subi *+AR0(5), AR0 & subi -5, *+AR0(5), AR0 & subi *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & subi3_T: & subi3 AR2, AR1, AR0 & subi3 AR1, AR0 & subi3 AR1, *+AR0(1), AR0 & subi3 *+AR0(1), AR1, AR0 & subi3 *+AR0(1), AR0 & subi3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & subi3_T_sc: & subi3 -5, AR1, AR0 & subi3 -5, AR0 & subi3 *+AR0(5), AR1, AR0 & subi3 *+AR0(5), AR0 & subi3 -5, *+AR0(5), AR0 & subi3 *+AR0(5), *+AR1(5), AR0 & .endif
+ .ifdef TEST_C3X & subi_sti_Q: & subi R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| subi R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subi_sti_Q_enh: & subi R0, R0, R0 &|| sti R1, *+AR1(1) & subi R0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| subi R0, R0, R0 & sti R1, *+AR1(1) &|| subi R0, R0 & .endif & .ifdef TEST_C3X & subi3_sti_Q: & subi3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| subi3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & subi3_sti_Q_enh: & subi3 R0, R0, R0 &|| sti R1, *+AR1(1) & subi3 R0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| subi3 R0, R0, R0 & sti R1, *+AR1(1) &|| subi3 R0, R0 & .endif
+ .ifdef TEST_C3X & subrb_A: & subrb AR1, AR0 & subrb AR0 & subrb @start, AR0 & subrb *+AR0(5), AR0 & subrb -5, AR0 & .endif
+ .ifdef TEST_C3X & subrf_B: & subrf R1, R0 & subrf R0 & subrf @start, R0 & subrf *+AR0(5), R0 & subrf 3.5, R0 & .endif
+ .ifdef TEST_C3X & subri_A: & subri AR1, AR0 & subri AR0 & subri @start, AR0 & subri *+AR0(5), AR0 & subri -5, AR0 & .endif
+ .ifdef TEST_C3X
swi_Z: swi
trap_Z: trapC 10
trap 10
- tstb_AU: & tstb AR1, AR0 & tstb AR0 & tstb @start, AR0 & tstb *+AR0(5), AR0 & tstb 5, AR0
- tstb_T2C: & tstb AR2, AR1 & tstb AR1, *+AR0(1) & tstb *+AR0(1), AR1 & tstb *+AR1(1), *+AR0(1) & .ifdef TEST_C4X & tstb 5, AR1 & tstb AR1, -5 & tstb *+AR0(5), AR1 & tstb AR1, *+AR0(5) & tstb 5, *+AR0(5) & tstb *+AR0(5), -5 & tstb *+AR0(5), *+AR1(5) & .endif & tstb3_T2C: & tstb3 AR2, AR1 & tstb3 AR1, *+AR0(1) & tstb3 *+AR0(1), AR1 & tstb3 *+AR1(1), *+AR0(1) & .ifdef TEST_C4X & tstb3 -5, AR1 & tstb3 AR1, -5 & tstb3 *+AR0(5), AR1 & tstb3 AR1, *+AR0(5) & tstb3 -5, *+AR0(5) & tstb3 *+AR0(5), -5 & tstb3 *+AR0(5), *+AR1(5) & .endif
- xor_AU: & xor AR1, AR0 & xor AR0 & xor @start, AR0 & xor *+AR0(5), AR0 & xor 5, AR0
- xor_TC: & xor AR2, AR1, AR0 & xor AR1, AR0 & xor AR1, *+AR0(1), AR0 & xor *+AR0(1), AR1, AR0 & xor *+AR0(1), AR0 & xor *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & xor 5, AR1, AR0 & xor 5, AR0 & xor AR1, -5, AR0 & xor *+AR0(5), AR1, AR0 & xor *+AR0(5), AR0 & xor AR1, *+AR0(5), AR0 & xor 5, *+AR0(5), AR0 & xor *+AR0(5), -5, AR0 & xor *+AR0(5), *+AR1(5), AR0 & .endif & xor3_TC: & xor3 AR2, AR1, AR0 & xor3 AR1, AR0 & xor3 AR1, *+AR0(1), AR0 & xor3 *+AR0(1), AR1, AR0 & xor3 *+AR0(1), AR0 & xor3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & xor3 -5, AR1, AR0 & xor3 -5, AR0 & xor3 AR1, -5, AR0 & xor3 *+AR0(5), AR1, AR0 & xor3 *+AR0(5), AR0 & xor3 AR1, *+AR0(5), AR0 & xor3 -5, *+AR0(5), AR0 & xor3 *+AR0(5), -5, AR0 & xor3 *+AR0(5), *+AR1(5), AR0 & .endif
- xor_sti_QC: & xor *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & xor *+AR0(1), R0 &|| sti R1, *+AR1(1) & xor R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| xor *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| xor *+AR0(1), R0 & sti R1, *+AR1(1) &|| xor R0, *+AR0(1), R0 & xor3_sti_QC: & xor3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & xor3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & xor3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| xor3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| xor3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| xor3 R0, *+AR0(1), R0
-
+ .endif
+ .ifdef TEST_C3X & tstb_AU: & tstb AR1, AR0 & tstb AR0 & tstb @start, AR0 & tstb *+AR0(5), AR0 & tstb 5, AR0 & .endif
+ .ifdef TEST_C3X & tstb_T2C: & tstb AR2, AR1 & tstb AR1, *+AR0(1) & tstb *+AR0(1), AR1 & tstb *+AR1(1), *+AR0(1) & .endif & .ifdef TEST_C4X & tstb_T2C_c4x: & tstb -5, AR1 & tstb AR1, -5 & tstb *+AR0(5), AR1 & tstb AR1, *+AR0(5) & tstb -5, *+AR0(5) & tstb *+AR0(5), -5 & tstb *+AR0(5), *+AR1(5) & .endif & .ifdef TEST_C3X & tstb3_T2C: & tstb3 AR2, AR1 & tstb3 AR1, *+AR0(1) & tstb3 *+AR0(1), AR1 & tstb3 *+AR1(1), *+AR0(1) & .endif & .ifdef TEST_C4X & tstb3_T2C_c4x: & tstb3 -5, AR1 & tstb3 AR1, -5 & tstb3 *+AR0(5), AR1 & tstb3 AR1, *+AR0(5) & tstb3 -5, *+AR0(5) & tstb3 *+AR0(5), -5 & tstb3 *+AR0(5), *+AR1(5) & .endif
+ .ifdef TEST_C3X & xor_AU: & xor AR1, AR0 & xor AR0 & xor @start, AR0 & xor *+AR0(5), AR0 & xor 5, AR0 & .endif
+ .ifdef TEST_C3X & xor_TC: & xor AR2, AR1, AR0 & xor AR1, AR0 & xor AR1, *+AR0(1), AR0 & xor *+AR0(1), AR1, AR0 & xor *+AR0(1), AR0 & xor *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & xor_TC_c4x: & xor -5, AR1, AR0 & xor -5, AR0 & xor AR1, -5, AR0 & xor *+AR0(5), AR1, AR0 & xor *+AR0(5), AR0 & xor AR1, *+AR0(5), AR0 & xor -5, *+AR0(5), AR0 & xor *+AR0(5), -5, AR0 & xor *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C3X & xor3_TC: & xor3 AR2, AR1, AR0 & xor3 AR1, AR0 & xor3 AR1, *+AR0(1), AR0 & xor3 *+AR0(1), AR1, AR0 & xor3 *+AR0(1), AR0 & xor3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & xor3_TC_c4x: & xor3 -5, AR1, AR0 & xor3 -5, AR0 & xor3 AR1, -5, AR0 & xor3 *+AR0(5), AR1, AR0 & xor3 *+AR0(5), AR0 & xor3 AR1, *+AR0(5), AR0 & xor3 -5, *+AR0(5), AR0 & xor3 *+AR0(5), -5, AR0 & xor3 *+AR0(5), *+AR1(5), AR0 & .endif
+ .ifdef TEST_C3X & xor_sti_QC: & xor *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & xor *+AR0(1), R0 &|| sti R1, *+AR1(1) & xor R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| xor *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| xor *+AR0(1), R0 & sti R1, *+AR1(1) &|| xor R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & xor_sti_QC_enh: & xor AR0, R1, R0 &|| sti R1, *+AR1(1) & xor R2, R1, R0 &|| sti R1, *+AR1(1) & xor R1, R0 &|| sti R1, *+AR1(1) & xor R0 &|| sti R1, *+AR1(1) & xor R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| xor AR0, R1, R0 & sti R1, *+AR1(1) &|| xor R2, R1, R0 & sti R1, *+AR1(1) &|| xor R1, R0 & sti R1, *+AR1(1) &|| xor R0 & sti R1, *+AR1(1) &|| xor R0, AR0, R0 & .endif & .ifdef TEST_C3X & xor3_sti_QC: & xor3 *+AR0(1), R1, R0 &|| sti R1, *+AR1(1) & xor3 *+AR0(1), R0 &|| sti R1, *+AR1(1) & xor3 R0, *+AR0(1), R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| xor3 *+AR0(1), R1, R0 & sti R1, *+AR1(1) &|| xor3 *+AR0(1), R0 & sti R1, *+AR1(1) &|| xor3 R0, *+AR0(1), R0 & .endif & .ifdef TEST_ENH & xor3_sti_QC_enh: & xor3 AR0, R1, R0 &|| sti R1, *+AR1(1) & xor3 R2, R1, R0 &|| sti R1, *+AR1(1) & xor3 R1, R0 &|| sti R1, *+AR1(1) & xor3 R0 &|| sti R1, *+AR1(1) & xor3 R0, AR0, R0 &|| sti R1, *+AR1(1) & sti R1, *+AR1(1) &|| xor3 AR0, R1, R0 & sti R1, *+AR1(1) &|| xor3 R2, R1, R0 & sti R1, *+AR1(1) &|| xor3 R1, R0 & sti R1, *+AR1(1) &|| xor3 R0 & sti R1, *+AR1(1) &|| xor3 R0, AR0, R0 & .endif
+
+ ;;------------------------------------
+ ;; C4X INSNS
+ ;;------------------------------------
.ifdef TEST_C4X
- bCaf_J: & bCaf R0 & bCaf start & baf_J: & baf R0 & baf start
- bCat_J: & bCat R0 & bCat start & bat_J: & bat R0 & bat start
- frieee_B6: & frieee @start, R0 & frieee *+AR0(5), R0
- frieee_stf_P: & frieee *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| frieee *+AR0(1), R0
+ .ifdef TEST_C4X & bCaf_J: & bCaf R0 & bCaf start & baf_J: & baf R0 & baf start & .endif
+ .ifdef TEST_C4X & bCat_J: & bCat R0 & bCat start & bat_J: & bat R0 & bat start & .endif
+ .ifdef TEST_C4X & frieee_B6: & frieee @start, R0 & frieee *+AR0(5), R0 & .endif
+ .ifdef TEST_C4X & frieee_stf_P: & frieee *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| frieee *+AR0(1), R0 & .endif & .ifdef TEST_ENH & frieee_stf_P_enh: & frieee R0, R0 &|| stf R1, *+AR1(1) & frieee R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| frieee R0, R0 & stf R1, *+AR1(1) &|| frieee R0 & .endif
+ .ifdef TEST_C4X
laj_I: laj start
laj_JS: lajc R0
lajc start
lat_Z: latC 10
- lb0_A: & lb0 AR1, AR0 & lb0 AR0 & lb0 @start, AR0 & lb0 *+AR0(5), AR0 & lb0 -5, AR0
- lb1_A: & lb1 AR1, AR0 & lb1 AR0 & lb1 @start, AR0 & lb1 *+AR0(5), AR0 & lb1 -5, AR0
- lb2_A: & lb2 AR1, AR0 & lb2 AR0 & lb2 @start, AR0 & lb2 *+AR0(5), AR0 & lb2 -5, AR0
- lb3_A: & lb3 AR1, AR0 & lb3 AR0 & lb3 @start, AR0 & lb3 *+AR0(5), AR0 & lb3 -5, AR0
- lbu0_AU: & lbu0 AR1, AR0 & lbu0 AR0 & lbu0 @start, AR0 & lbu0 *+AR0(5), AR0 & lbu0 5, AR0
- lbu1_AU: & lbu1 AR1, AR0 & lbu1 AR0 & lbu1 @start, AR0 & lbu1 *+AR0(5), AR0 & lbu1 5, AR0
- lbu2_AU: & lbu2 AR1, AR0 & lbu2 AR0 & lbu2 @start, AR0 & lbu2 *+AR0(5), AR0 & lbu2 5, AR0
- lbu3_AU: & lbu3 AR1, AR0 & lbu3 AR0 & lbu3 @start, AR0 & lbu3 *+AR0(5), AR0 & lbu3 5, AR0
- lda_AY: & lda AR1, AR0 & lda @start, AR0 & lda *+AR0(5), AR0 & lda -5, AR0
+ .endif
+ .ifdef TEST_C4X & lb0_A: & lb0 AR1, AR0 & lb0 AR0 & lb0 @start, AR0 & lb0 *+AR0(5), AR0 & lb0 -5, AR0 & .endif
+ .ifdef TEST_C4X & lb1_A: & lb1 AR1, AR0 & lb1 AR0 & lb1 @start, AR0 & lb1 *+AR0(5), AR0 & lb1 -5, AR0 & .endif
+ .ifdef TEST_C4X & lb2_A: & lb2 AR1, AR0 & lb2 AR0 & lb2 @start, AR0 & lb2 *+AR0(5), AR0 & lb2 -5, AR0 & .endif
+ .ifdef TEST_C4X & lb3_A: & lb3 AR1, AR0 & lb3 AR0 & lb3 @start, AR0 & lb3 *+AR0(5), AR0 & lb3 -5, AR0 & .endif
+ .ifdef TEST_C4X & lbu0_AU: & lbu0 AR1, AR0 & lbu0 AR0 & lbu0 @start, AR0 & lbu0 *+AR0(5), AR0 & lbu0 5, AR0 & .endif
+ .ifdef TEST_C4X & lbu1_AU: & lbu1 AR1, AR0 & lbu1 AR0 & lbu1 @start, AR0 & lbu1 *+AR0(5), AR0 & lbu1 5, AR0 & .endif
+ .ifdef TEST_C4X & lbu2_AU: & lbu2 AR1, AR0 & lbu2 AR0 & lbu2 @start, AR0 & lbu2 *+AR0(5), AR0 & lbu2 5, AR0 & .endif
+ .ifdef TEST_C4X & lbu3_AU: & lbu3 AR1, AR0 & lbu3 AR0 & lbu3 @start, AR0 & lbu3 *+AR0(5), AR0 & lbu3 5, AR0 & .endif
+ .ifdef TEST_C4X & lda_AY: & lda AR1, AR0 & lda @start, AR0 & lda *+AR0(5), AR0 & lda -5, AR0 & .endif
+ .ifdef TEST_C4X
ldep_Z: ldep IVTP, AR0
ldhi_Z: ldhi 35, R0
ldhi start, R0
ldpe_Z: ldpe AR0, IVTP
ldpk_Z: ldpk start
- lh0_A: & lh0 AR1, AR0 & lh0 AR0 & lh0 @start, AR0 & lh0 *+AR0(5), AR0 & lh0 -5, AR0
- lh1_A: & lh1 AR1, AR0 & lh1 AR0 & lh1 @start, AR0 & lh1 *+AR0(5), AR0 & lh1 -5, AR0
- lhu0_AU: & lhu0 AR1, AR0 & lhu0 AR0 & lhu0 @start, AR0 & lhu0 *+AR0(5), AR0 & lhu0 5, AR0
- lhu1_AU: & lhu1 AR1, AR0 & lhu1 AR0 & lhu1 @start, AR0 & lhu1 *+AR0(5), AR0 & lhu1 5, AR0
- lwl0_A: & lwl0 AR1, AR0 & lwl0 AR0 & lwl0 @start, AR0 & lwl0 *+AR0(5), AR0 & lwl0 -5, AR0
- lwl1_A: & lwl1 AR1, AR0 & lwl1 AR0 & lwl1 @start, AR0 & lwl1 *+AR0(5), AR0 & lwl1 -5, AR0
- lwl2_A: & lwl2 AR1, AR0 & lwl2 AR0 & lwl2 @start, AR0 & lwl2 *+AR0(5), AR0 & lwl2 -5, AR0
- lwl3_A: & lwl3 AR1, AR0 & lwl3 AR0 & lwl3 @start, AR0 & lwl3 *+AR0(5), AR0 & lwl3 -5, AR0
- lwr0_A: & lwr0 AR1, AR0 & lwr0 AR0 & lwr0 @start, AR0 & lwr0 *+AR0(5), AR0 & lwr0 -5, AR0
- lwr1_A: & lwr1 AR1, AR0 & lwr1 AR0 & lwr1 @start, AR0 & lwr1 *+AR0(5), AR0 & lwr1 -5, AR0
- lwr2_A: & lwr2 AR1, AR0 & lwr2 AR0 & lwr2 @start, AR0 & lwr2 *+AR0(5), AR0 & lwr2 -5, AR0
- lwr3_A: & lwr3 AR1, AR0 & lwr3 AR0 & lwr3 @start, AR0 & lwr3 *+AR0(5), AR0 & lwr3 -5, AR0
- mb0_A: & mb0 AR1, AR0 & mb0 AR0 & mb0 @start, AR0 & mb0 *+AR0(5), AR0 & mb0 -5, AR0
- mb1_A: & mb1 AR1, AR0 & mb1 AR0 & mb1 @start, AR0 & mb1 *+AR0(5), AR0 & mb1 -5, AR0
- mb2_A: & mb2 AR1, AR0 & mb2 AR0 & mb2 @start, AR0 & mb2 *+AR0(5), AR0 & mb2 -5, AR0
- mb3_A: & mb3 AR1, AR0 & mb3 AR0 & mb3 @start, AR0 & mb3 *+AR0(5), AR0 & mb3 -5, AR0
- mh0_A: & mh0 AR1, AR0 & mh0 AR0 & mh0 @start, AR0 & mh0 *+AR0(5), AR0 & mh0 -5, AR0
- mh1_A: & mh1 AR1, AR0 & mh1 AR0 & mh1 @start, AR0 & mh1 *+AR0(5), AR0 & mh1 -5, AR0
- mh2_A: & mh2 AR1, AR0 & mh2 AR0 & mh2 @start, AR0 & mh2 *+AR0(5), AR0 & mh2 -5, AR0
- mh3_A: & mh3 AR1, AR0 & mh3 AR0 & mh3 @start, AR0 & mh3 *+AR0(5), AR0 & mh3 -5, AR0
- mpyshi_A: & mpyshi AR1, AR0 & mpyshi AR0 & mpyshi @start, AR0 & mpyshi *+AR0(5), AR0 & mpyshi -5, AR0
- mpyshi_TC: & mpyshi AR2, AR1, AR0 & mpyshi AR1, AR0 & mpyshi AR1, *+AR0(1), AR0 & mpyshi *+AR0(1), AR1, AR0 & mpyshi *+AR0(1), AR0 & mpyshi *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & mpyshi 5, AR1, AR0 & mpyshi 5, AR0 & mpyshi AR1, -5, AR0 & mpyshi *+AR0(5), AR1, AR0 & mpyshi *+AR0(5), AR0 & mpyshi AR1, *+AR0(5), AR0 & mpyshi 5, *+AR0(5), AR0 & mpyshi *+AR0(5), -5, AR0 & mpyshi *+AR0(5), *+AR1(5), AR0 & .endif & mpyshi3_TC: & mpyshi3 AR2, AR1, AR0 & mpyshi3 AR1, AR0 & mpyshi3 AR1, *+AR0(1), AR0 & mpyshi3 *+AR0(1), AR1, AR0 & mpyshi3 *+AR0(1), AR0 & mpyshi3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & mpyshi3 -5, AR1, AR0 & mpyshi3 -5, AR0 & mpyshi3 AR1, -5, AR0 & mpyshi3 *+AR0(5), AR1, AR0 & mpyshi3 *+AR0(5), AR0 & mpyshi3 AR1, *+AR0(5), AR0 & mpyshi3 -5, *+AR0(5), AR0 & mpyshi3 *+AR0(5), -5, AR0 & mpyshi3 *+AR0(5), *+AR1(5), AR0 & .endif
- mpyuhi_A: & mpyuhi AR1, AR0 & mpyuhi AR0 & mpyuhi @start, AR0 & mpyuhi *+AR0(5), AR0 & mpyuhi -5, AR0
- mpyuhi_TC: & mpyuhi AR2, AR1, AR0 & mpyuhi AR1, AR0 & mpyuhi AR1, *+AR0(1), AR0 & mpyuhi *+AR0(1), AR1, AR0 & mpyuhi *+AR0(1), AR0 & mpyuhi *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & mpyuhi 5, AR1, AR0 & mpyuhi 5, AR0 & mpyuhi AR1, -5, AR0 & mpyuhi *+AR0(5), AR1, AR0 & mpyuhi *+AR0(5), AR0 & mpyuhi AR1, *+AR0(5), AR0 & mpyuhi 5, *+AR0(5), AR0 & mpyuhi *+AR0(5), -5, AR0 & mpyuhi *+AR0(5), *+AR1(5), AR0 & .endif & mpyuhi3_TC: & mpyuhi3 AR2, AR1, AR0 & mpyuhi3 AR1, AR0 & mpyuhi3 AR1, *+AR0(1), AR0 & mpyuhi3 *+AR0(1), AR1, AR0 & mpyuhi3 *+AR0(1), AR0 & mpyuhi3 *+AR1(1), *+AR0(1), AR0 & .ifdef TEST_C4X & mpyuhi3 -5, AR1, AR0 & mpyuhi3 -5, AR0 & mpyuhi3 AR1, -5, AR0 & mpyuhi3 *+AR0(5), AR1, AR0 & mpyuhi3 *+AR0(5), AR0 & mpyuhi3 AR1, *+AR0(5), AR0 & mpyuhi3 -5, *+AR0(5), AR0 & mpyuhi3 *+AR0(5), -5, AR0 & mpyuhi3 *+AR0(5), *+AR1(5), AR0 & .endif
- rcpf_BA: & rcpf AR1, R0 & rcpf R0 & rcpf @start, R0 & rcpf *+AR0(5), R0 & rcpf 3.5, R0
+ .endif
+ .ifdef TEST_C4X & lh0_A: & lh0 AR1, AR0 & lh0 AR0 & lh0 @start, AR0 & lh0 *+AR0(5), AR0 & lh0 -5, AR0 & .endif
+ .ifdef TEST_C4X & lh1_A: & lh1 AR1, AR0 & lh1 AR0 & lh1 @start, AR0 & lh1 *+AR0(5), AR0 & lh1 -5, AR0 & .endif
+ .ifdef TEST_C4X & lhu0_AU: & lhu0 AR1, AR0 & lhu0 AR0 & lhu0 @start, AR0 & lhu0 *+AR0(5), AR0 & lhu0 5, AR0 & .endif
+ .ifdef TEST_C4X & lhu1_AU: & lhu1 AR1, AR0 & lhu1 AR0 & lhu1 @start, AR0 & lhu1 *+AR0(5), AR0 & lhu1 5, AR0 & .endif
+ .ifdef TEST_C4X & lwl0_A: & lwl0 AR1, AR0 & lwl0 AR0 & lwl0 @start, AR0 & lwl0 *+AR0(5), AR0 & lwl0 -5, AR0 & .endif
+ .ifdef TEST_C4X & lwl1_A: & lwl1 AR1, AR0 & lwl1 AR0 & lwl1 @start, AR0 & lwl1 *+AR0(5), AR0 & lwl1 -5, AR0 & .endif
+ .ifdef TEST_C4X & lwl2_A: & lwl2 AR1, AR0 & lwl2 AR0 & lwl2 @start, AR0 & lwl2 *+AR0(5), AR0 & lwl2 -5, AR0 & .endif
+ .ifdef TEST_C4X & lwl3_A: & lwl3 AR1, AR0 & lwl3 AR0 & lwl3 @start, AR0 & lwl3 *+AR0(5), AR0 & lwl3 -5, AR0 & .endif
+ .ifdef TEST_C4X & lwr0_A: & lwr0 AR1, AR0 & lwr0 AR0 & lwr0 @start, AR0 & lwr0 *+AR0(5), AR0 & lwr0 -5, AR0 & .endif
+ .ifdef TEST_C4X & lwr1_A: & lwr1 AR1, AR0 & lwr1 AR0 & lwr1 @start, AR0 & lwr1 *+AR0(5), AR0 & lwr1 -5, AR0 & .endif
+ .ifdef TEST_C4X & lwr2_A: & lwr2 AR1, AR0 & lwr2 AR0 & lwr2 @start, AR0 & lwr2 *+AR0(5), AR0 & lwr2 -5, AR0 & .endif
+ .ifdef TEST_C4X & lwr3_A: & lwr3 AR1, AR0 & lwr3 AR0 & lwr3 @start, AR0 & lwr3 *+AR0(5), AR0 & lwr3 -5, AR0 & .endif
+ .ifdef TEST_C4X & mb0_A: & mb0 AR1, AR0 & mb0 AR0 & mb0 @start, AR0 & mb0 *+AR0(5), AR0 & mb0 -5, AR0 & .endif
+ .ifdef TEST_C4X & mb1_A: & mb1 AR1, AR0 & mb1 AR0 & mb1 @start, AR0 & mb1 *+AR0(5), AR0 & mb1 -5, AR0 & .endif
+ .ifdef TEST_C4X & mb2_A: & mb2 AR1, AR0 & mb2 AR0 & mb2 @start, AR0 & mb2 *+AR0(5), AR0 & mb2 -5, AR0 & .endif
+ .ifdef TEST_C4X & mb3_A: & mb3 AR1, AR0 & mb3 AR0 & mb3 @start, AR0 & mb3 *+AR0(5), AR0 & mb3 -5, AR0 & .endif
+ .ifdef TEST_C4X & mh0_A: & mh0 AR1, AR0 & mh0 AR0 & mh0 @start, AR0 & mh0 *+AR0(5), AR0 & mh0 -5, AR0 & .endif
+ .ifdef TEST_C4X & mh1_A: & mh1 AR1, AR0 & mh1 AR0 & mh1 @start, AR0 & mh1 *+AR0(5), AR0 & mh1 -5, AR0 & .endif
+ .ifdef TEST_C4X & mh2_A: & mh2 AR1, AR0 & mh2 AR0 & mh2 @start, AR0 & mh2 *+AR0(5), AR0 & mh2 -5, AR0 & .endif
+ .ifdef TEST_C4X & mh3_A: & mh3 AR1, AR0 & mh3 AR0 & mh3 @start, AR0 & mh3 *+AR0(5), AR0 & mh3 -5, AR0 & .endif
+ .ifdef TEST_C4X & mpyshi_A: & mpyshi AR1, AR0 & mpyshi AR0 & mpyshi @start, AR0 & mpyshi *+AR0(5), AR0 & mpyshi -5, AR0 & .endif
+ .ifdef TEST_C4X & mpyshi_TC: & mpyshi AR2, AR1, AR0 & mpyshi AR1, AR0 & mpyshi AR1, *+AR0(1), AR0 & mpyshi *+AR0(1), AR1, AR0 & mpyshi *+AR0(1), AR0 & mpyshi *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & mpyshi_TC_c4x: & mpyshi -5, AR1, AR0 & mpyshi -5, AR0 & mpyshi AR1, -5, AR0 & mpyshi *+AR0(5), AR1, AR0 & mpyshi *+AR0(5), AR0 & mpyshi AR1, *+AR0(5), AR0 & mpyshi -5, *+AR0(5), AR0 & mpyshi *+AR0(5), -5, AR0 & mpyshi *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C4X & mpyshi3_TC: & mpyshi3 AR2, AR1, AR0 & mpyshi3 AR1, AR0 & mpyshi3 AR1, *+AR0(1), AR0 & mpyshi3 *+AR0(1), AR1, AR0 & mpyshi3 *+AR0(1), AR0 & mpyshi3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & mpyshi3_TC_c4x: & mpyshi3 -5, AR1, AR0 & mpyshi3 -5, AR0 & mpyshi3 AR1, -5, AR0 & mpyshi3 *+AR0(5), AR1, AR0 & mpyshi3 *+AR0(5), AR0 & mpyshi3 AR1, *+AR0(5), AR0 & mpyshi3 -5, *+AR0(5), AR0 & mpyshi3 *+AR0(5), -5, AR0 & mpyshi3 *+AR0(5), *+AR1(5), AR0 & .endif
+ .ifdef TEST_C4X & mpyuhi_A: & mpyuhi AR1, AR0 & mpyuhi AR0 & mpyuhi @start, AR0 & mpyuhi *+AR0(5), AR0 & mpyuhi -5, AR0 & .endif
+ .ifdef TEST_C4X & mpyuhi_TC: & mpyuhi AR2, AR1, AR0 & mpyuhi AR1, AR0 & mpyuhi AR1, *+AR0(1), AR0 & mpyuhi *+AR0(1), AR1, AR0 & mpyuhi *+AR0(1), AR0 & mpyuhi *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & mpyuhi_TC_c4x: & mpyuhi -5, AR1, AR0 & mpyuhi -5, AR0 & mpyuhi AR1, -5, AR0 & mpyuhi *+AR0(5), AR1, AR0 & mpyuhi *+AR0(5), AR0 & mpyuhi AR1, *+AR0(5), AR0 & mpyuhi -5, *+AR0(5), AR0 & mpyuhi *+AR0(5), -5, AR0 & mpyuhi *+AR0(5), *+AR1(5), AR0 & .endif & .ifdef TEST_C4X & mpyuhi3_TC: & mpyuhi3 AR2, AR1, AR0 & mpyuhi3 AR1, AR0 & mpyuhi3 AR1, *+AR0(1), AR0 & mpyuhi3 *+AR0(1), AR1, AR0 & mpyuhi3 *+AR0(1), AR0 & mpyuhi3 *+AR1(1), *+AR0(1), AR0 & .endif & .ifdef TEST_C4X & mpyuhi3_TC_c4x: & mpyuhi3 -5, AR1, AR0 & mpyuhi3 -5, AR0 & mpyuhi3 AR1, -5, AR0 & mpyuhi3 *+AR0(5), AR1, AR0 & mpyuhi3 *+AR0(5), AR0 & mpyuhi3 AR1, *+AR0(5), AR0 & mpyuhi3 -5, *+AR0(5), AR0 & mpyuhi3 *+AR0(5), -5, AR0 & mpyuhi3 *+AR0(5), *+AR1(5), AR0 & .endif
+ .ifdef TEST_C4X & rcpf_BA: & rcpf AR1, R0 & rcpf R0 & rcpf @start, R0 & rcpf *+AR0(5), R0 & rcpf 3.5, R0 & .endif
+ .ifdef TEST_C4X
retid_Z: retiCd
retid
rptb2_I2: rptb AR0
rptbd_I2: rptbd start
rptbd AR0
- rsqrf_B: & rsqrf R1, R0 & rsqrf R0 & rsqrf @start, R0 & rsqrf *+AR0(5), R0 & rsqrf 3.5, R0
- sigi_A6: & sigi @start, AR0 & sigi *+AR0(5), AR0
+ .endif
+ .ifdef TEST_C4X & rsqrf_B: & rsqrf R1, R0 & rsqrf R0 & rsqrf @start, R0 & rsqrf *+AR0(5), R0 & rsqrf 3.5, R0 & .endif
+ .ifdef TEST_C4X & sigi_A6: & sigi @start, AR0 & sigi *+AR0(5), AR0 & .endif
+ .ifdef TEST_C4X
sti2_A7: sti -5, @start
sti -5, *+AR0(5)
stik_Z: stik -5, @start
stik -5, *+AR0(5)
- toieee_B: & toieee R1, R0 & toieee R0 & toieee @start, R0 & toieee *+AR0(5), R0 & toieee 3.5, R0
- toieee_stf_P: & toieee *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| toieee *+AR0(1), R0
+ .endif
+ .ifdef TEST_C4X & toieee_B: & toieee R1, R0 & toieee R0 & toieee @start, R0 & toieee *+AR0(5), R0 & toieee 3.5, R0 & .endif
+ .ifdef TEST_C4X & toieee_stf_P: & toieee *+AR0(1), R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| toieee *+AR0(1), R0 & .endif & .ifdef TEST_ENH & toieee_stf_P_enh: & toieee R0, R0 &|| stf R1, *+AR1(1) & toieee R0 &|| stf R1, *+AR1(1) & stf R1, *+AR1(1) &|| toieee R0, R0 & stf R1, *+AR1(1) &|| toieee R0 & .endif
.endif
.end
16e: 83000001.*
16f: 83020001.*
-00000170 <addf3_mpyf3_M>:
+00000170 <addf3_mpyf_M>:
170: 80080100.*
171: 80100100.*
172: 81000001.*
188: 83000001.*
189: 83020001.*
-0000018a <addf3_mpyf_M>:
+0000018a <addf3_mpyf3_M>:
18a: 80080100.*
18b: 80100100.*
18c: 81000001.*
1e2: 87000001.*
1e3: 87020001.*
-000001e4 <subf3_mpyf3_M>:
+000001e4 <subf3_mpyf_M>:
1e4: 84080100.*
1e5: 84100100.*
1e6: 85000001.*
1fc: 87000001.*
1fd: 87020001.*
-000001fe <subf3_mpyf_M>:
+000001fe <subf3_mpyf3_M>:
1fe: 84080100.*
1ff: 84100100.*
200: 85000001.*
25b: 8b000001.*
25c: 8b020001.*
-0000025d <addi3_mpyi3_M>:
+0000025d <addi3_mpyi_M>:
25d: 88080100.*
25e: 88100100.*
25f: 89000001.*
275: 8b000001.*
276: 8b020001.*
-00000277 <addi3_mpyi_M>:
+00000277 <addi3_mpyi3_M>:
277: 88080100.*
278: 88100100.*
279: 89000001.*
2cf: 8f000001.*
2d0: 8f020001.*
-000002d1 <subi3_mpyi3_M>:
+000002d1 <subi3_mpyi_M>:
2d1: 8c080100.*
2d2: 8c100100.*
2d3: 8d000001.*
2e9: 8f000001.*
2ea: 8f020001.*
-000002eb <subi3_mpyi_M>:
+000002eb <subi3_mpyi3_M>:
2eb: 8c080100.*
2ec: 8c100100.*
2ed: 8d000001.*
-#as: -m40 --defsym TEST_C4X=1
+#as: -m40 --defsym TEST_C4X=1 --defsym TEST_C3X=1
#objdump: -d -z
#name: c4x opcodes
#source: opcodes.s
16: 20480900.*
17: 01480001.*
18: 20680001.*
- 19: 30080905.*
- 1a: 01680005.*
+
+00000019 <addc_TC_c4x>:
+ 19: 300809fb.*
+ 1a: 0168fffb.*
1b: 300809fb.*
1c: 30280928.*
1d: 01480005.*
1e: 30280928.*
- 1f: 30482805.*
+ 1f: 304828fb.*
20: 304828fb.*
21: 30682928.*
25: 20480900.*
26: 20480800.*
27: 20680001.*
+
+00000028 <addc3_TC_c4x>:
28: 300809fb.*
29: 300808fb.*
2a: 300809fb.*
39: 20c00100.*
3a: 01c00001.*
3b: 20e00100.*
+
+0000003c <addf_SC_c4x>:
3c: 30a00128.*
3d: 01c00005.*
3e: 30a00128.*
43: 20c00100.*
44: 20c00000.*
45: 20e00100.*
+
+00000046 <addf3_SC_c4x>:
46: 30a00128.*
47: 30a00028.*
48: 30a00128.*
5e: 21480900.*
5f: 02480001.*
60: 21680001.*
- 61: 31080905.*
- 62: 02680005.*
+
+00000061 <addi_TC_c4x>:
+ 61: 310809fb.*
+ 62: 0268fffb.*
63: 310809fb.*
64: 31280928.*
65: 02480005.*
66: 31280928.*
- 67: 31482805.*
+ 67: 314828fb.*
68: 314828fb.*
69: 31682928.*
6d: 21480900.*
6e: 21480800.*
6f: 21680001.*
+
+00000070 <addi3_TC_c4x>:
70: 310809fb.*
71: 310808fb.*
72: 310809fb.*
8d: 21c80900.*
8e: 02c80001.*
8f: 21e80001.*
- 90: 31880905.*
- 91: 02e80005.*
+
+00000090 <and_TC_c4x>:
+ 90: 318809fb.*
+ 91: 318808fb.*
92: 318809fb.*
93: 31a80928.*
94: 02c80005.*
95: 31a80928.*
- 96: 31c82805.*
+ 96: 31c828fb.*
97: 31c828fb.*
98: 31e82928.*
9c: 21c80900.*
9d: 21c80800.*
9e: 21e80001.*
+
+0000009f <and3_TC_c4x>:
9f: 318809fb.*
a0: 318808fb.*
a1: 318809fb.*
bc: 22480900.*
bd: 03480001.*
be: 22680001.*
- bf: 32080905.*
- c0: 03680005.*
+
+000000bf <andn_T_sc>:
+ bf: 320809fb.*
+ c0: 320808fb.*
c1: 32280928.*
c2: 03480005.*
- c3: 32482805.*
+ c3: 324828fb.*
c4: 32682928.*
000000c5 <andn3_T>:
c8: 22480900.*
c9: 22480800.*
ca: 22680001.*
+
+000000cb <andn3_T_sc>:
cb: 320809fb.*
cc: 320808fb.*
cd: 32280928.*
d9: 22c80900.*
da: 03c80001.*
db: 22e80001.*
- dc: 32880905.*
- dd: 03e80005.*
+
+000000dc <ash_T_sc>:
+ dc: 328809fb.*
+ dd: 03e8fffb.*
de: 32a80928.*
df: 03c80005.*
- e0: 32c82805.*
+ e0: 32c828fb.*
e1: 32e82928.*
000000e2 <ash3_T>:
e5: 22c80900.*
e6: 22c80800.*
e7: 22e80001.*
+
+000000e8 <ash3_T_sc>:
e8: 328809fb.*
e9: 328808fb.*
ea: 32a80928.*
105: 23200001.*
106: 04410001.*
107: 23600100.*
+
+00000108 <cmpf_S2_c4x>:
108: 04410005.*
109: 33602928.*
10b: 23200001.*
10c: 23400100.*
10d: 23600100.*
+
+0000010e <cmpf3_S2_c4x>:
10e: 33200128.*
10f: 33602928.*
116: 23a00009.*
117: 04c90001.*
118: 23e00001.*
+
+00000119 <cmpi_T2_c4x>:
119: 04e9fffb.*
11a: 04c90005.*
11b: 33c028fb.*
11e: 23a00009.*
11f: 23c00900.*
120: 23e00001.*
+
+00000121 <cmpi3_T2_c4x>:
121: 338009fb.*
122: 33a00928.*
123: 33c028fb.*
173: 24480900.*
174: 09c80001.*
175: 24680001.*
- 176: 34080905.*
- 177: 09e80005.*
+
+00000176 <lsh_T_sc>:
+ 176: 340809fb.*
+ 177: 09e8fffb.*
178: 34280928.*
179: 09c80005.*
- 17a: 34482805.*
+ 17a: 344828fb.*
17b: 34682928.*
0000017c <lsh3_T>:
17f: 24480900.*
180: 24480800.*
181: 24680001.*
+
+00000182 <lsh3_T_sc>:
182: 340809fb.*
183: 340808fb.*
184: 34280928.*
194: 24c00100.*
195: 0a400001.*
196: 24e00100.*
+
+00000197 <mpyf_SC_c4x>:
197: 34a00128.*
198: 0a400005.*
199: 34a00128.*
19e: 24c00100.*
19f: 24c00000.*
1a0: 24e00100.*
+
+000001a1 <mpyf3_SC_c4x>:
1a1: 34a00128.*
1a2: 34a00028.*
1a3: 34a00128.*
1e4: 83000001.*
1e5: 83020001.*
-000001e6 <addf3_mpyf3_M>:
+000001e6 <addf3_mpyf_M>:
1e6: 80080100.*
1e7: 80100100.*
1e8: 81000001.*
1fe: 83000001.*
1ff: 83020001.*
-00000200 <addf3_mpyf_M>:
+00000200 <addf3_mpyf3_M>:
200: 80080100.*
201: 80100100.*
202: 81000001.*
258: 87000001.*
259: 87020001.*
-0000025a <subf3_mpyf3_M>:
+0000025a <subf3_mpyf_M>:
25a: 84080100.*
25b: 84100100.*
25c: 85000001.*
272: 87000001.*
273: 87020001.*
-00000274 <subf3_mpyf_M>:
+00000274 <subf3_mpyf3_M>:
274: 84080100.*
275: 84100100.*
276: 85000001.*
289: 25480900.*
28a: 0ac80001.*
28b: 25680001.*
- 28c: 35080905.*
- 28d: 0ae80005.*
+
+0000028c <mpyi_TC_c4x>:
+ 28c: 350809fb.*
+ 28d: 0ae8fffb.*
28e: 350809fb.*
28f: 35280928.*
290: 0ac80005.*
291: 35280928.*
- 292: 35482805.*
+ 292: 354828fb.*
293: 354828fb.*
294: 35682928.*
298: 25480900.*
299: 25480800.*
29a: 25680001.*
+
+0000029b <mpyi3_TC_c4x>:
29b: 350809fb.*
29c: 350808fb.*
29d: 350809fb.*
2e3: 8b000001.*
2e4: 8b020001.*
-000002e5 <addi3_mpyi3_M>:
+000002e5 <addi3_mpyi_M>:
2e5: 88080100.*
2e6: 88100100.*
2e7: 89000001.*
2fd: 8b000001.*
2fe: 8b020001.*
-000002ff <addi3_mpyi_M>:
+000002ff <addi3_mpyi3_M>:
2ff: 88080100.*
300: 88100100.*
301: 89000001.*
357: 8f000001.*
358: 8f020001.*
-00000359 <subi3_mpyi3_M>:
+00000359 <subi3_mpyi_M>:
359: 8c080100.*
35a: 8c100100.*
35b: 8d000001.*
371: 8f000001.*
372: 8f020001.*
-00000373 <subi3_mpyi_M>:
+00000373 <subi3_mpyi3_M>:
373: 8c080100.*
374: 8c100100.*
375: 8d000001.*
3aa: 25c80900.*
3ab: 10480001.*
3ac: 25e80001.*
- 3ad: 35880905.*
- 3ae: 10680005.*
+
+000003ad <or_TC_c4x>:
+ 3ad: 358809fb.*
+ 3ae: 358808fb.*
3af: 358809fb.*
3b0: 35a80928.*
3b1: 10480005.*
3b2: 35a80928.*
- 3b3: 35c82805.*
+ 3b3: 35c828fb.*
3b4: 35c828fb.*
3b5: 35e82928.*
3b9: 25c80900.*
3ba: 25c80800.*
3bb: 25e80001.*
+
+000003bc <or3_TC_c4x>:
3bc: 358809fb.*
3bd: 358808fb.*
3be: 358809fb.*
3fe: 26480900.*
3ff: 16c80001.*
400: 26680001.*
- 401: 36080905.*
- 402: 16e80005.*
+
+00000401 <subb_T_sc>:
+ 401: 360809fb.*
+ 402: 16e8fffb.*
403: 36280928.*
404: 16c80005.*
- 405: 36482805.*
+ 405: 364828fb.*
406: 36682928.*
00000407 <subb3_T>:
40a: 26480900.*
40b: 26480800.*
40c: 26680001.*
+
+0000040d <subb3_T_sc>:
40d: 360809fb.*
40e: 360808fb.*
40f: 36280928.*
420: 26c00100.*
421: 17c00001.*
422: 26e00100.*
+
+00000423 <subf_S_c4x>:
423: 36a00128.*
424: 17c00005.*
425: 36e02928.*
429: 26c00100.*
42a: 26c00000.*
42b: 26e00100.*
+
+0000042c <subf3_S_c4x>:
42c: 36a00128.*
42d: 36a00028.*
42e: 36e02928.*
43b: 27480900.*
43c: 18480001.*
43d: 27680001.*
- 43e: 37080905.*
- 43f: 18680005.*
+
+0000043e <subi_T_sc>:
+ 43e: 370809fb.*
+ 43f: 1868fffb.*
440: 37280928.*
441: 18480005.*
- 442: 37482805.*
+ 442: 374828fb.*
443: 37682928.*
00000444 <subi3_T>:
447: 27480900.*
448: 27480800.*
449: 27680001.*
+
+0000044a <subi3_T_sc>:
44a: 370809fb.*
44b: 370808fb.*
44c: 37280928.*
46c: 27a00009.*
46d: 1a490001.*
46e: 27e00001.*
- 46f: 1a690005.*
+
+0000046f <tstb_T2C_c4x>:
+ 46f: 378009fb.*
470: 378009fb.*
471: 1a490005.*
472: 37a00928.*
- 473: 37c02805.*
+ 473: 37c028fb.*
474: 37c028fb.*
475: 37e02928.*
477: 27a00009.*
478: 27c00900.*
479: 27e00001.*
+
+0000047a <tstb3_T2C_c4x>:
47a: 378009fb.*
47b: 378009fb.*
47c: 37a00928.*
489: 28480900.*
48a: 1ac80001.*
48b: 28680001.*
- 48c: 38080905.*
- 48d: 1ae80005.*
+
+0000048c <xor_TC_c4x>:
+ 48c: 380809fb.*
+ 48d: 380808fb.*
48e: 380809fb.*
48f: 38280928.*
490: 1ac80005.*
491: 38280928.*
- 492: 38482805.*
+ 492: 384828fb.*
493: 384828fb.*
494: 38682928.*
498: 28480900.*
499: 28480800.*
49a: 28680001.*
+
+0000049b <xor3_TC_c4x>:
49b: 380809fb.*
49c: 380808fb.*
49d: 380809fb.*
55d: 28c80900.*
55e: 1dc80001.*
55f: 28e80001.*
- 560: 38880905.*
- 561: 1de80005.*
+
+00000560 <mpyshi_TC_c4x>:
+ 560: 388809fb.*
+ 561: 1de8fffb.*
562: 388809fb.*
563: 38a80928.*
564: 1dc80005.*
565: 38a80928.*
- 566: 38c82805.*
+ 566: 38c828fb.*
567: 38c828fb.*
568: 38e82928.*
56c: 28c80900.*
56d: 28c80800.*
56e: 28e80001.*
+
+0000056f <mpyshi3_TC_c4x>:
56f: 388809fb.*
570: 388808fb.*
571: 388809fb.*
580: 29480900.*
581: 1e480001.*
582: 29680001.*
- 583: 39080905.*
- 584: 1e680005.*
+
+00000583 <mpyuhi_TC_c4x>:
+ 583: 390809fb.*
+ 584: 1e68fffb.*
585: 390809fb.*
586: 39280928.*
587: 1e480005.*
588: 39280928.*
- 589: 39482805.*
+ 589: 394828fb.*
58a: 394828fb.*
58b: 39682928.*
58f: 29480900.*
590: 29480800.*
591: 29680001.*
+
+00000592 <mpyuhi3_TC_c4x>:
592: 390809fb.*
593: 390808fb.*
594: 390809fb.*
--- /dev/null
+#as: -m30 -menhanced -midle2 -mlowpower --defsym TEST_ENH=1 --defsym TEST_IDLE2=1 --defsym TEST_LPWR=1
+#objdump: -d -z
+#name: c3x/c4x new opcodes
+#source: opcodes.s
+
+.*: +file format .*c4x.*
+
+Disassembly of section .text:
+
+00000000 <absf_stf_P_enh>:
+ 0: c80101e0.*
+ 1: c80101e0.*
+ 2: c80101e0.*
+ 3: c80101e0.*
+
+00000004 <absi_sti_P_enh>:
+ 4: ca0101e0.*
+ 5: ca0101e0.*
+ 6: ca0101e0.*
+ 7: ca0101e0.*
+
+00000008 <addf_stf_QC_enh>:
+ 8: cc0901e8.*
+ 9: cc0901e2.*
+ a: cc0101e1.*
+ b: cc0101e0.*
+ c: cc0101e8.*
+ d: cc0901e8.*
+ e: cc0901e2.*
+ f: cc0101e1.*
+ 10: cc0101e0.*
+ 11: cc0101e8.*
+
+00000012 <addf3_stf_QC_enh>:
+ 12: cc0901e8.*
+ 13: cc0901e2.*
+ 14: cc0101e1.*
+ 15: cc0101e0.*
+ 16: cc0101e8.*
+ 17: cc0901e8.*
+ 18: cc0901e2.*
+ 19: cc0101e1.*
+ 1a: cc0101e0.*
+ 1b: cc0101e8.*
+
+0000001c <addi_sti_QC_enh>:
+ 1c: ce0901e8.*
+ 1d: ce0901e2.*
+ 1e: ce0101e1.*
+ 1f: ce0101e0.*
+ 20: ce0101e8.*
+ 21: ce0901e8.*
+ 22: ce0901e2.*
+ 23: ce0101e1.*
+ 24: ce0101e0.*
+ 25: ce0101e8.*
+
+00000026 <addi3_sti_QC_enh>:
+ 26: ce0901e8.*
+ 27: ce0901e2.*
+ 28: ce0101e1.*
+ 29: ce0101e0.*
+ 2a: ce0101e8.*
+ 2b: ce0901e8.*
+ 2c: ce0901e2.*
+ 2d: ce0101e1.*
+ 2e: ce0101e0.*
+ 2f: ce0101e8.*
+
+00000030 <and_sti_QC_enh>:
+ 30: d00901e8.*
+ 31: d00901e2.*
+ 32: d00101e1.*
+ 33: d00101e0.*
+ 34: d00101e8.*
+ 35: d00901e8.*
+ 36: d00901e2.*
+ 37: d00101e1.*
+ 38: d00101e0.*
+ 39: d00101e8.*
+
+0000003a <and3_sti_QC_enh>:
+ 3a: d00901e8.*
+ 3b: d00901e2.*
+ 3c: d00101e1.*
+ 3d: d00101e0.*
+ 3e: d00101e8.*
+ 3f: d00901e8.*
+ 40: d00901e2.*
+ 41: d00101e1.*
+ 42: d00101e0.*
+ 43: d00101e8.*
+
+00000044 <ash_sti_Q_enh>:
+ 44: d20101e0.*
+ 45: d20101e0.*
+ 46: d20101e0.*
+ 47: d20101e0.*
+
+00000048 <ash3_sti_Q_enh>:
+ 48: d20101e0.*
+ 49: d20101e0.*
+ 4a: d20101e0.*
+ 4b: d20101e0.*
+
+0000004c <fix_sti_P_enh>:
+ 4c: d40101e0.*
+ 4d: d40101e0.*
+ 4e: d40101e0.*
+ 4f: d40101e0.*
+
+00000050 <float_stf_P_enh>:
+ 50: d60101e0.*
+ 51: d60101e0.*
+ 52: d60101e0.*
+ 53: d60101e0.*
+
+00000054 <idle2_Z>:
+ 54: 06000001.*
+
+00000055 <ldf_LL_enh>:
+ 55: c40801e0.*
+ 56: c40801e0.*
+ 57: c40801e0.*
+ 58: c40801e0.*
+ 59: c40801e0.*
+ 5a: c40801e0.*
+
+0000005b <ldf_stf_P_enh>:
+ 5b: d80101e0.*
+ 5c: d80101e0.*
+ 5d: d80101e0.*
+ 5e: d80101e0.*
+
+0000005f <ldi_LL_enh>:
+ 5f: c60801e0.*
+ 60: c60801e0.*
+ 61: c60801e0.*
+ 62: c60801e0.*
+ 63: c60801e0.*
+ 64: c60801e0.*
+
+00000065 <ldi_sti_P_enh>:
+ 65: da0101e0.*
+ 66: da0101e0.*
+ 67: da0101e0.*
+ 68: da0101e0.*
+
+00000069 <lopower_Z>:
+ 69: 10800001.*
+
+0000006a <lsh_sti_Q_enh>:
+ 6a: dc0101e0.*
+ 6b: dc0101e0.*
+ 6c: dc0101e0.*
+ 6d: dc0101e0.*
+
+0000006e <lsh3_sti_Q_enh>:
+ 6e: dc0101e0.*
+ 6f: dc0101e0.*
+ 70: dc0101e0.*
+ 71: dc0101e0.*
+
+00000072 <maxspeed_Z>:
+ 72: 10800000.*
+
+00000073 <mpyf_addf_M_enh>:
+ 73: 8012e0e0.*
+ 74: 8012e0e0.*
+ 75: 8012e0e0.*
+ 76: 8012e0e0.*
+ 77: 8012e0e0.*
+ 78: 8012e0e0.*
+ 79: 8012e8e8.*
+ 7a: 8100e8e8.*
+ 7b: 8100e8e8.*
+ 7c: 820ae9e8.*
+ 7d: 830be8e8.*
+ 7e: 8300e8e8.*
+
+0000007f <mpyf3_addf_M_enh>:
+ 7f: 8012e0e0.*
+ 80: 8012e0e0.*
+ 81: 8012e0e0.*
+ 82: 8012e0e0.*
+ 83: 8012e0e0.*
+ 84: 8012e0e0.*
+ 85: 8012e8e8.*
+ 86: 8100e8e8.*
+ 87: 8100e8e8.*
+ 88: 820ae9e8.*
+ 89: 830be8e8.*
+ 8a: 8300e8e8.*
+
+0000008b <mpyf_addf3_M_enh>:
+ 8b: 8012e0e0.*
+ 8c: 8012e0e0.*
+ 8d: 8012e0e0.*
+ 8e: 8012e0e0.*
+ 8f: 8012e0e0.*
+ 90: 8012e0e0.*
+ 91: 8012e8e8.*
+ 92: 8100e8e8.*
+ 93: 8100e8e8.*
+ 94: 820ae9e8.*
+ 95: 830be8e8.*
+ 96: 8300e8e8.*
+
+00000097 <mpyf3_addf3_M_enh>:
+ 97: 8012e0e0.*
+ 98: 8012e0e0.*
+ 99: 8012e0e0.*
+ 9a: 8012e0e0.*
+ 9b: 8012e0e0.*
+ 9c: 8012e0e0.*
+ 9d: 8012e8e8.*
+ 9e: 8100e8e8.*
+ 9f: 8100e8e8.*
+ a0: 820ae9e8.*
+ a1: 830be8e8.*
+ a2: 8300e8e8.*
+
+000000a3 <addf_mpyf_M_enh>:
+ a3: 8012e0e0.*
+ a4: 8012e0e0.*
+ a5: 8012e0e0.*
+ a6: 8012e0e0.*
+ a7: 8012e0e0.*
+ a8: 8012e0e0.*
+ a9: 8012e8e8.*
+ aa: 8100e8e8.*
+ ab: 8100e8e8.*
+ ac: 820ae9e8.*
+ ad: 830be8e8.*
+ ae: 8300e8e8.*
+
+000000af <addf3_mpyf_M_enh>:
+ af: 8012e0e0.*
+ b0: 8012e0e0.*
+ b1: 8012e0e0.*
+ b2: 8012e0e0.*
+ b3: 8012e0e0.*
+ b4: 8012e0e0.*
+ b5: 8012e8e8.*
+ b6: 8100e8e8.*
+ b7: 8100e8e8.*
+ b8: 820ae9e8.*
+ b9: 830be8e8.*
+ ba: 8300e8e8.*
+
+000000bb <addf_mpyf3_M_enh>:
+ bb: 8012e0e0.*
+ bc: 8012e0e0.*
+ bd: 8012e0e0.*
+ be: 8012e0e0.*
+ bf: 8012e0e0.*
+ c0: 8012e0e0.*
+ c1: 8012e8e8.*
+ c2: 8100e8e8.*
+ c3: 8100e8e8.*
+ c4: 820ae9e8.*
+ c5: 830be8e8.*
+ c6: 8300e8e8.*
+
+000000c7 <addf3_mpyf3_M_enh>:
+ c7: 8012e0e0.*
+ c8: 8012e0e0.*
+ c9: 8012e0e0.*
+ ca: 8012e0e0.*
+ cb: 8012e0e0.*
+ cc: 8012e0e0.*
+ cd: 8012e8e8.*
+ ce: 8100e8e8.*
+ cf: 8100e8e8.*
+ d0: 820ae9e8.*
+ d1: 830be8e8.*
+ d2: 8300e8e8.*
+
+000000d3 <mpyf_stf_QC_enh>:
+ d3: de0901e8.*
+ d4: de0901e2.*
+ d5: de0101e1.*
+ d6: de0101e0.*
+ d7: de0101e8.*
+ d8: de0901e8.*
+ d9: de0901e2.*
+ da: de0101e1.*
+ db: de0101e0.*
+ dc: de0101e8.*
+
+000000dd <mpyf3_stf_QC_enh>:
+ dd: de0901e8.*
+ de: de0901e2.*
+ df: de0101e1.*
+ e0: de0101e0.*
+ e1: de0101e8.*
+ e2: de0901e8.*
+ e3: de0901e2.*
+ e4: de0101e1.*
+ e5: de0101e0.*
+ e6: de0101e8.*
+
+000000e7 <mpyf_subf_M_enh>:
+ e7: 8412e0e0.*
+ e8: 8412e0e0.*
+ e9: 8412e0e0.*
+ ea: 8412e0e0.*
+ eb: 8412e0e0.*
+ ec: 8412e0e0.*
+ ed: 8412e8e8.*
+ ee: 8500e8e8.*
+ ef: 8500e8e8.*
+ f0: 860ae9e8.*
+ f1: 870be8e8.*
+ f2: 8700e8e8.*
+
+000000f3 <mpyf3_subf_M_enh>:
+ f3: 8412e0e0.*
+ f4: 8412e0e0.*
+ f5: 8412e0e0.*
+ f6: 8412e0e0.*
+ f7: 8412e0e0.*
+ f8: 8412e0e0.*
+ f9: 8412e8e8.*
+ fa: 8500e8e8.*
+ fb: 8500e8e8.*
+ fc: 860ae9e8.*
+ fd: 870be8e8.*
+ fe: 8700e8e8.*
+
+000000ff <mpyf_subf3_M_enh>:
+ ff: 8412e0e0.*
+ 100: 8412e0e0.*
+ 101: 8412e0e0.*
+ 102: 8412e0e0.*
+ 103: 8412e0e0.*
+ 104: 8412e0e0.*
+ 105: 8412e8e8.*
+ 106: 8500e8e8.*
+ 107: 8500e8e8.*
+ 108: 860ae9e8.*
+ 109: 870be8e8.*
+ 10a: 8700e8e8.*
+
+0000010b <mpyf3_subf3_M_enh>:
+ 10b: 8412e0e0.*
+ 10c: 8412e0e0.*
+ 10d: 8412e0e0.*
+ 10e: 8412e0e0.*
+ 10f: 8412e0e0.*
+ 110: 8412e0e0.*
+ 111: 8412e8e8.*
+ 112: 8500e8e8.*
+ 113: 8500e8e8.*
+ 114: 860ae9e8.*
+ 115: 870be8e8.*
+ 116: 8700e8e8.*
+
+00000117 <subf_mpyf_M_enh>:
+ 117: 8412e0e0.*
+ 118: 8412e0e0.*
+ 119: 8412e0e0.*
+ 11a: 8412e0e0.*
+ 11b: 8412e0e0.*
+ 11c: 8412e0e0.*
+ 11d: 8412e8e8.*
+ 11e: 8500e8e8.*
+ 11f: 8500e8e8.*
+ 120: 860ae9e8.*
+ 121: 870be8e8.*
+ 122: 8700e8e8.*
+
+00000123 <subf3_mpyf_M_enh>:
+ 123: 8412e0e0.*
+ 124: 8412e0e0.*
+ 125: 8412e0e0.*
+ 126: 8412e0e0.*
+ 127: 8412e0e0.*
+ 128: 8412e0e0.*
+ 129: 8412e8e8.*
+ 12a: 8500e8e8.*
+ 12b: 8500e8e8.*
+ 12c: 860ae9e8.*
+ 12d: 870be8e8.*
+ 12e: 8700e8e8.*
+
+0000012f <subf_mpyf3_M_enh>:
+ 12f: 8412e0e0.*
+ 130: 8412e0e0.*
+ 131: 8412e0e0.*
+ 132: 8412e0e0.*
+ 133: 8412e0e0.*
+ 134: 8412e0e0.*
+ 135: 8412e8e8.*
+ 136: 8500e8e8.*
+ 137: 8500e8e8.*
+ 138: 860ae9e8.*
+ 139: 870be8e8.*
+ 13a: 8700e8e8.*
+
+0000013b <subf3_mpyf3_M_enh>:
+ 13b: 8412e0e0.*
+ 13c: 8412e0e0.*
+ 13d: 8412e0e0.*
+ 13e: 8412e0e0.*
+ 13f: 8412e0e0.*
+ 140: 8412e0e0.*
+ 141: 8412e8e8.*
+ 142: 8500e8e8.*
+ 143: 8500e8e8.*
+ 144: 860ae9e8.*
+ 145: 870be8e8.*
+ 146: 8700e8e8.*
+
+00000147 <mpyi_addi_M_enh>:
+ 147: 8812e0e0.*
+ 148: 8812e0e0.*
+ 149: 8812e0e0.*
+ 14a: 8812e0e0.*
+ 14b: 8812e0e0.*
+ 14c: 8812e0e0.*
+ 14d: 8812e8e8.*
+ 14e: 8900e8e8.*
+ 14f: 8900e8e8.*
+ 150: 8a0ae9e8.*
+ 151: 8b0be8e8.*
+ 152: 8b00e8e8.*
+
+00000153 <mpyi3_addi_M_enh>:
+ 153: 8812e0e0.*
+ 154: 8812e0e0.*
+ 155: 8812e0e0.*
+ 156: 8812e0e0.*
+ 157: 8812e0e0.*
+ 158: 8812e0e0.*
+ 159: 8812e8e8.*
+ 15a: 8900e8e8.*
+ 15b: 8900e8e8.*
+ 15c: 8a0ae9e8.*
+ 15d: 8b0be8e8.*
+ 15e: 8b00e8e8.*
+
+0000015f <mpyi_addi3_M_enh>:
+ 15f: 8812e0e0.*
+ 160: 8812e0e0.*
+ 161: 8812e0e0.*
+ 162: 8812e0e0.*
+ 163: 8812e0e0.*
+ 164: 8812e0e0.*
+ 165: 8812e8e8.*
+ 166: 8900e8e8.*
+ 167: 8900e8e8.*
+ 168: 8a0ae9e8.*
+ 169: 8b0be8e8.*
+ 16a: 8b00e8e8.*
+
+0000016b <mpyi3_addi3_M_enh>:
+ 16b: 8812e0e0.*
+ 16c: 8812e0e0.*
+ 16d: 8812e0e0.*
+ 16e: 8812e0e0.*
+ 16f: 8812e0e0.*
+ 170: 8812e0e0.*
+ 171: 8812e8e8.*
+ 172: 8900e8e8.*
+ 173: 8900e8e8.*
+ 174: 8a0ae9e8.*
+ 175: 8b0be8e8.*
+ 176: 8b00e8e8.*
+
+00000177 <addi_mpyi_M_enh>:
+ 177: 8812e0e0.*
+ 178: 8812e0e0.*
+ 179: 8812e0e0.*
+ 17a: 8812e0e0.*
+ 17b: 8812e0e0.*
+ 17c: 8812e0e0.*
+ 17d: 8812e8e8.*
+ 17e: 8900e8e8.*
+ 17f: 8900e8e8.*
+ 180: 8a0ae9e8.*
+ 181: 8b0be8e8.*
+ 182: 8b00e8e8.*
+
+00000183 <addi3_mpyi_M_enh>:
+ 183: 8812e0e0.*
+ 184: 8812e0e0.*
+ 185: 8812e0e0.*
+ 186: 8812e0e0.*
+ 187: 8812e0e0.*
+ 188: 8812e0e0.*
+ 189: 8812e8e8.*
+ 18a: 8900e8e8.*
+ 18b: 8900e8e8.*
+ 18c: 8a0ae9e8.*
+ 18d: 8b0be8e8.*
+ 18e: 8b00e8e8.*
+
+0000018f <addi_mpyi3_M_enh>:
+ 18f: 8812e0e0.*
+ 190: 8812e0e0.*
+ 191: 8812e0e0.*
+ 192: 8812e0e0.*
+ 193: 8812e0e0.*
+ 194: 8812e0e0.*
+ 195: 8812e8e8.*
+ 196: 8900e8e8.*
+ 197: 8900e8e8.*
+ 198: 8a0ae9e8.*
+ 199: 8b0be8e8.*
+ 19a: 8b00e8e8.*
+
+0000019b <addi3_mpyi3_M_enh>:
+ 19b: 8812e0e0.*
+ 19c: 8812e0e0.*
+ 19d: 8812e0e0.*
+ 19e: 8812e0e0.*
+ 19f: 8812e0e0.*
+ 1a0: 8812e0e0.*
+ 1a1: 8812e8e8.*
+ 1a2: 8900e8e8.*
+ 1a3: 8900e8e8.*
+ 1a4: 8a0ae9e8.*
+ 1a5: 8b0be8e8.*
+ 1a6: 8b00e8e8.*
+
+000001a7 <mpyi_sti_QC_enh>:
+ 1a7: e00901e8.*
+ 1a8: e00901e2.*
+ 1a9: e00101e1.*
+ 1aa: e00101e0.*
+ 1ab: e00101e8.*
+ 1ac: e00901e8.*
+ 1ad: e00901e2.*
+ 1ae: e00101e1.*
+ 1af: e00101e0.*
+ 1b0: e00101e8.*
+
+000001b1 <mpyi3_sti_QC_enh>:
+ 1b1: e00901e8.*
+ 1b2: e00901e2.*
+ 1b3: e00101e1.*
+ 1b4: e00101e0.*
+ 1b5: e00101e8.*
+ 1b6: e00901e8.*
+ 1b7: e00901e2.*
+ 1b8: e00101e1.*
+ 1b9: e00101e0.*
+ 1ba: e00101e8.*
+
+000001bb <mpyi_subi_M_enh>:
+ 1bb: 8c12e0e0.*
+ 1bc: 8c12e0e0.*
+ 1bd: 8c12e0e0.*
+ 1be: 8c12e0e0.*
+ 1bf: 8c12e0e0.*
+ 1c0: 8c12e0e0.*
+ 1c1: 8c12e8e8.*
+ 1c2: 8d00e8e8.*
+ 1c3: 8d00e8e8.*
+ 1c4: 8e0ae9e8.*
+ 1c5: 8f0be8e8.*
+ 1c6: 8f00e8e8.*
+
+000001c7 <mpyi3_subi_M_enh>:
+ 1c7: 8c12e0e0.*
+ 1c8: 8c12e0e0.*
+ 1c9: 8c12e0e0.*
+ 1ca: 8c12e0e0.*
+ 1cb: 8c12e0e0.*
+ 1cc: 8c12e0e0.*
+ 1cd: 8c12e8e8.*
+ 1ce: 8d00e8e8.*
+ 1cf: 8d00e8e8.*
+ 1d0: 8e0ae9e8.*
+ 1d1: 8f0be8e8.*
+ 1d2: 8f00e8e8.*
+
+000001d3 <mpyi_subi3_M_enh>:
+ 1d3: 8c12e0e0.*
+ 1d4: 8c12e0e0.*
+ 1d5: 8c12e0e0.*
+ 1d6: 8c12e0e0.*
+ 1d7: 8c12e0e0.*
+ 1d8: 8c12e0e0.*
+ 1d9: 8c12e8e8.*
+ 1da: 8d00e8e8.*
+ 1db: 8d00e8e8.*
+ 1dc: 8e0ae9e8.*
+ 1dd: 8f0be8e8.*
+ 1de: 8f00e8e8.*
+
+000001df <mpyi3_subi3_M_enh>:
+ 1df: 8c12e0e0.*
+ 1e0: 8c12e0e0.*
+ 1e1: 8c12e0e0.*
+ 1e2: 8c12e0e0.*
+ 1e3: 8c12e0e0.*
+ 1e4: 8c12e0e0.*
+ 1e5: 8c12e8e8.*
+ 1e6: 8d00e8e8.*
+ 1e7: 8d00e8e8.*
+ 1e8: 8e0ae9e8.*
+ 1e9: 8f0be8e8.*
+ 1ea: 8f00e8e8.*
+
+000001eb <subi_mpyi_M_enh>:
+ 1eb: 8c12e0e0.*
+ 1ec: 8c12e0e0.*
+ 1ed: 8c12e0e0.*
+ 1ee: 8c12e0e0.*
+ 1ef: 8c12e0e0.*
+ 1f0: 8c12e0e0.*
+ 1f1: 8c12e8e8.*
+ 1f2: 8d00e8e8.*
+ 1f3: 8d00e8e8.*
+ 1f4: 8e0ae9e8.*
+ 1f5: 8f0be8e8.*
+ 1f6: 8f00e8e8.*
+
+000001f7 <subi3_mpyi_M_enh>:
+ 1f7: 8c12e0e0.*
+ 1f8: 8c12e0e0.*
+ 1f9: 8c12e0e0.*
+ 1fa: 8c12e0e0.*
+ 1fb: 8c12e0e0.*
+ 1fc: 8c12e0e0.*
+ 1fd: 8c12e8e8.*
+ 1fe: 8d00e8e8.*
+ 1ff: 8d00e8e8.*
+ 200: 8e0ae9e8.*
+ 201: 8f0be8e8.*
+ 202: 8f00e8e8.*
+
+00000203 <subi_mpyi3_M_enh>:
+ 203: 8c12e0e0.*
+ 204: 8c12e0e0.*
+ 205: 8c12e0e0.*
+ 206: 8c12e0e0.*
+ 207: 8c12e0e0.*
+ 208: 8c12e0e0.*
+ 209: 8c12e8e8.*
+ 20a: 8d00e8e8.*
+ 20b: 8d00e8e8.*
+ 20c: 8e0ae9e8.*
+ 20d: 8f0be8e8.*
+ 20e: 8f00e8e8.*
+
+0000020f <subi3_mpyi3_M_enh>:
+ 20f: 8c12e0e0.*
+ 210: 8c12e0e0.*
+ 211: 8c12e0e0.*
+ 212: 8c12e0e0.*
+ 213: 8c12e0e0.*
+ 214: 8c12e0e0.*
+ 215: 8c12e8e8.*
+ 216: 8d00e8e8.*
+ 217: 8d00e8e8.*
+ 218: 8e0ae9e8.*
+ 219: 8f0be8e8.*
+ 21a: 8f00e8e8.*
+
+0000021b <negf_stf_P_enh>:
+ 21b: e20101e0.*
+ 21c: e20101e0.*
+ 21d: e20101e0.*
+ 21e: e20101e0.*
+
+0000021f <negi_sti_P_enh>:
+ 21f: e40101e0.*
+ 220: e40101e0.*
+ 221: e40101e0.*
+ 222: e40101e0.*
+
+00000223 <not_sti_P_enh>:
+ 223: e60101e0.*
+ 224: e60101e0.*
+ 225: e60101e0.*
+ 226: e60101e0.*
+
+00000227 <or_sti_QC_enh>:
+ 227: e80901e8.*
+ 228: e80901e2.*
+ 229: e80101e1.*
+ 22a: e80101e0.*
+ 22b: e80101e8.*
+ 22c: e80901e8.*
+ 22d: e80901e2.*
+ 22e: e80101e1.*
+ 22f: e80101e0.*
+ 230: e80101e8.*
+
+00000231 <or3_sti_QC_enh>:
+ 231: e80901e8.*
+ 232: e80901e2.*
+ 233: e80101e1.*
+ 234: e80101e0.*
+ 235: e80101e8.*
+ 236: e80901e8.*
+ 237: e80901e2.*
+ 238: e80101e1.*
+ 239: e80101e0.*
+ 23a: e80101e8.*
+
+0000023b <stf_LS_enh>:
+ 23b: c00101e0.*
+ 23c: c00101e0.*
+ 23d: c00101e0.*
+ 23e: c00101e0.*
+ 23f: c00101e0.*
+ 240: c00101e0.*
+
+00000241 <sti_LS_enh>:
+ 241: c20101e0.*
+ 242: c20101e0.*
+ 243: c20101e0.*
+ 244: c20101e0.*
+ 245: c20101e0.*
+ 246: c20101e0.*
+
+00000247 <subf_stf_Q_enh>:
+ 247: ea0101e0.*
+ 248: ea0101e0.*
+ 249: ea0101e0.*
+ 24a: ea0101e0.*
+
+0000024b <subf3_stf_Q_enh>:
+ 24b: ea0101e0.*
+ 24c: ea0101e0.*
+ 24d: ea0101e0.*
+ 24e: ea0101e0.*
+
+0000024f <subi_sti_Q_enh>:
+ 24f: ec0101e0.*
+ 250: ec0101e0.*
+ 251: ec0101e0.*
+ 252: ec0101e0.*
+
+00000253 <subi3_sti_Q_enh>:
+ 253: ec0101e0.*
+ 254: ec0101e0.*
+ 255: ec0101e0.*
+ 256: ec0101e0.*
+
+00000257 <xor_sti_QC_enh>:
+ 257: ee0901e8.*
+ 258: ee0901e2.*
+ 259: ee0101e1.*
+ 25a: ee0101e0.*
+ 25b: ee0101e8.*
+ 25c: ee0901e8.*
+ 25d: ee0901e2.*
+ 25e: ee0101e1.*
+ 25f: ee0101e0.*
+ 260: ee0101e8.*
+
+00000261 <xor3_sti_QC_enh>:
+ 261: ee0901e8.*
+ 262: ee0901e2.*
+ 263: ee0101e1.*
+ 264: ee0101e0.*
+ 265: ee0101e8.*
+ 266: ee0901e8.*
+ 267: ee0901e2.*
+ 268: ee0101e1.*
+ 269: ee0101e0.*
+ 26a: ee0101e8.*
# Test float instructions
run_dump_test "opcodes_c3x"
run_dump_test "opcodes_c4x"
+ run_dump_test "opcodes_new"
# Make sure the c4x ops dont work on c3x
#gas_test_error "opcodes.s" "-m30 --defsym TEST_C4X=1" "c4x instruction usage in c3x"
+2002-11-18 Svein E. Seldal <Svein.Seldal@solidas.com>
+
+ * opcode/tic4x.h: File reordering. Added enhanced opcodes.
+
2002-11-16 Klee Dienes <kdienes@apple.com>
* opcode/m88k.h (INSTAB): Remove 'next' field.
const unsigned int c4x_num_registers = (((sizeof c4x_registers) / (sizeof c4x_registers[0])) - 1);
+struct c4x_cond
+{
+ char * name;
+ unsigned long cond;
+};
+
+typedef struct c4x_cond c4x_cond_t;
+
+/* Define conditional branch/load suffixes. Put desired form for
+ disassembler last. */
+static const c4x_cond_t c4x_conds[] =
+{
+ { "u", 0x00 },
+ { "c", 0x01 }, { "lo", 0x01 },
+ { "ls", 0x02 },
+ { "hi", 0x03 },
+ { "nc", 0x04 }, { "hs", 0x04 },
+ { "z", 0x05 }, { "eq", 0x05 },
+ { "nz", 0x06 }, { "ne", 0x06 },
+ { "n", 0x07 }, { "l", 0x07 }, { "lt", 0x07 },
+ { "le", 0x08 },
+ { "p", 0x09 }, { "gt", 0x09 },
+ { "nn", 0x0a }, { "ge", 0x0a },
+ { "nv", 0x0c },
+ { "v", 0x0d },
+ { "nuf", 0x0e },
+ { "uf", 0x0f },
+ { "nlv", 0x10 },
+ { "lv", 0x11 },
+ { "nluf", 0x12 },
+ { "luf", 0x13 },
+ { "zuf", 0x14 },
+ /* Dummy entry, not included in num_conds. This
+ lets code examine entry i+1 without checking
+ if we've run off the end of the table. */
+ { "", 0x0}
+};
+
+const unsigned int num_conds = (((sizeof c4x_conds) / (sizeof c4x_conds[0])) - 1);
+
+struct c4x_indirect
+{
+ char * name;
+ unsigned long modn;
+};
+
+typedef struct c4x_indirect c4x_indirect_t;
+
+/* Define indirect addressing modes where:
+ d displacement (signed)
+ y ir0
+ z ir1 */
+
+static const c4x_indirect_t c4x_indirects[] =
+{
+ { "*+a(d)", 0x00 },
+ { "*-a(d)", 0x01 },
+ { "*++a(d)", 0x02 },
+ { "*--a(d)", 0x03 },
+ { "*a++(d)", 0x04 },
+ { "*a--(d)", 0x05 },
+ { "*a++(d)%", 0x06 },
+ { "*a--(d)%", 0x07 },
+ { "*+a(y)", 0x08 },
+ { "*-a(y)", 0x09 },
+ { "*++a(y)", 0x0a },
+ { "*--a(y)", 0x0b },
+ { "*a++(y)", 0x0c },
+ { "*a--(y)", 0x0d },
+ { "*a++(y)%", 0x0e },
+ { "*a--(y)%", 0x0f },
+ { "*+a(z)", 0x10 },
+ { "*-a(z)", 0x11 },
+ { "*++a(z)", 0x12 },
+ { "*--a(z)", 0x13 },
+ { "*a++(z)", 0x14 },
+ { "*a--(z)", 0x15 },
+ { "*a++(z)%", 0x16 },
+ { "*a--(z)%", 0x17 },
+ { "*a", 0x18 },
+ { "*a++(y)b", 0x19 },
+ /* Dummy entry, not included in num_indirects. This
+ lets code examine entry i+1 without checking
+ if we've run off the end of the table. */
+ { "", 0x0}
+};
+
+#define C3X_MODN_MAX 0x19
+
+const unsigned int c4x_num_indirects = (((sizeof c4x_indirects) / (sizeof c4x_indirects[0])) - 1);
+
/* Instruction template. */
struct c4x_inst
{
G register (all) 8--15 [T,TC,T2,T2C] - R0, R7, R11, AR0, DP
g register (0-11) 0--7 [S,SC,S2] - R0, R7, R11
H register (0-7) 18--16 [LS,M,P,Q] - R0, R7
- I indirect (no disp) 0--7 [LL,LS,M,P,Q,QC,S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
- J indirect (no disp) 8--15 [LL,LS,M,P,Q,QC,S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
+ I indirect (no disp) 0--7 [S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
+ i indirect (enhanced) 0--7 [LL,LS,M,P,Q,QC] - *+AR0(1), R5
+ J indirect (no disp) 8--15 [LL,LS,P,Q,QC,S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)
+ j indirect (enhanced) 8--15 [M] - *+AR0(1), R5
K register 19--21 [LL,M,Q,QC] - R0, R7
L register 22--24 [LL,LS,P,Q,QC] - R0, R7
M register (R2,R3) 22--22 [M] R2, R3
#define C4X_NAME_MAX 16 /* Max number of chars in parallel name. */
/* Define the instruction level */
-#define OP_C3X 0x0 /* C30 support - supported by all */
-#define OP_C4X 0x1 /* C40 support - C40, C44 */
-#define OP_C3XE 0x2 /* Class LL,LS,M,P,Q,QC enhancements. Argument type
- I and J is enhanced in these classes - C31>=6.0,
- C32>=2.0, C33 */
-#define OP_LPWR 0x3 /* Low power support (LOPOWER, MAXSPEED) - C30>=7.0,
- LC31, C31>=5.0, C32 */
-#define OP_IDLE 0x4 /* Idle2 support (IDLE2) - C30>=7.0, LC31, C31>=5.0,
- C32, C33, C40>=5.0, C44 */
+#define OP_C3X 0x1 /* C30 support - supported by all */
+#define OP_C4X 0x2 /* C40 support - C40, C44 */
+#define OP_ENH 0x4 /* Class LL,LS,M,P,Q,QC enhancements. Argument type
+ I and J is enhanced in these classes - C31>=6.0,
+ C32>=2.0, C33 */
+#define OP_LPWR 0x8 /* Low power support (LOPOWER, MAXSPEED) - C30>=7.0,
+ LC31, C31>=5.0, C32 */
+#define OP_IDLE2 0x10 /* Idle2 support (IDLE2) - C30>=7.0, LC31, C31>=5.0,
+ C32, C33, C40>=5.0, C44 */
/* The following class definition is a classification scheme for
putting instructions with similar type of arguments together. It
Syntax: <i> src2, dst2 || <i> src1, dst1
src1 = Indirect 0,1,IR0,IR1 (J)
dst1 = Register 0-7 (K)
- src2 = Indirect 0,1,IR0,IR1 (I)
+ src2 = Indirect 0,1,IR0,IR1, ENH: Register (i)
dst2 = Register 0-7 (L)
Instr: 2/0 - LDF||LDF, LDI||LDI
Alias: i||i, i1||i2, i2||i1
*/
#define LL_CLASS_INSN(name, opcode, level) \
- { name "_" name , opcode, 0xfe000000, "I,L|J,K", level }, \
- { name "2_" name "1", opcode, 0xfe000000, "I,L|J,K", level }, \
- { name "1_" name "2", opcode, 0xfe000000, "J,K|I,L", level }
+ { name "_" name , opcode, 0xfe000000, "i;L|J,K", level }, \
+ { name "2_" name "1", opcode, 0xfe000000, "i;L|J,K", level }, \
+ { name "1_" name "2", opcode, 0xfe000000, "J,K|i;L", level }
/* LS: Store-store parallell operation
Syntax: <i> src2, dst2 || <i> src1, dst1
src1 = Register 0-7 (H)
dst1 = Indirect 0,1,IR0,IR1 (J)
src2 = Register 0-7 (L)
- dst2 = Indirect 0,1,IR0,IR1 (I)
+ dst2 = Indirect 0,1,IR0,IR1, ENH: register (i)
Instr: 2/0 - STF||STF, STI||STI
Alias: i||i, i1||i2, i2||i1.
*/
#define LS_CLASS_INSN(name, opcode, level) \
- { name "_" name , opcode, 0xfe000000, "L,I|H,J", level }, \
- { name "2_" name "1", opcode, 0xfe000000, "L,I|H,J", level }, \
- { name "1_" name "2", opcode, 0xfe000000, "H,J|L,I", level }
+ { name "_" name , opcode, 0xfe000000, "L;i|H,J", level }, \
+ { name "2_" name "1", opcode, 0xfe000000, "L;i|H,J", level }, \
+ { name "1_" name "2", opcode, 0xfe000000, "H,J|L;i", level }
/* M: General multiply and add/sub operations
Syntax: <ia> src3,src4,dst1 || <ib> src2,src1,dst2 [00] - Manual
<ia> src1,src3,dst1 || <ib> src4,src2,dst2 [03]
src1 = Register 0-7 (K)
src2 = Register 0-7 (H)
- src3 = Indirect 0,1,IR0,IR1 (J)
- src4 = Indirect 0,1,IR0,IR1 (I)
+ src3 = Indirect 0,1,IR0,IR1, ENH: register (j)
+ src4 = Indirect 0,1,IR0,IR1, ENH: register (i)
dst1 = Register 0-1 (N)
dst2 = Register 2-3 (M)
Instr: 4/0 - MPYF3||ADDF3, MPYF3||SUBF3, MPYI3||ADDI3, MPYI3||SUBI3
Alias: a||b, a3||n, a||b3, a3||b3, b||a, b3||a, b||a3, b3||a3
*/
#define M_CLASS_INSN(namea, nameb, opcode, level) \
- { namea "_" nameb, opcode|0x00000000, 0xff000000, "I,J,N|H,K;M", level }, \
- { namea "_" nameb, opcode|0x01000000, 0xff000000, "J,K;N|H,I,M", level }, \
- { namea "_" nameb, opcode|0x01000000, 0xff000000, "K,J,N|H,I,M", level }, \
- { namea "_" nameb, opcode|0x02000000, 0xff000000, "H,K;N|I,J,M", level }, \
- { namea "_" nameb, opcode|0x03000000, 0xff000000, "J,K;N|I,H;M", level }, \
- { namea "_" nameb, opcode|0x03000000, 0xff000000, "K,J,N|I,H;M", level }, \
- { namea "3_" nameb, opcode|0x00000000, 0xff000000, "I,J,N|H,K;M", level }, \
- { namea "3_" nameb, opcode|0x01000000, 0xff000000, "J,K;N|H,I,M", level }, \
- { namea "3_" nameb, opcode|0x01000000, 0xff000000, "K,J,N|H,I,M", level }, \
- { namea "3_" nameb, opcode|0x02000000, 0xff000000, "H,K;N|I,J,M", level }, \
- { namea "3_" nameb, opcode|0x03000000, 0xff000000, "J,K;N|I,H;M", level }, \
- { namea "3_" nameb, opcode|0x03000000, 0xff000000, "K,J,N|I,H;M", level }, \
- { namea "_" nameb "3", opcode|0x00000000, 0xff000000, "I,J,N|H,K;M", level }, \
- { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "J,K;N|H,I,M", level }, \
- { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "K,J,N|H,I,M", level }, \
- { namea "_" nameb "3", opcode|0x02000000, 0xff000000, "H,K;N|I,J,M", level }, \
- { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "J,K;N|I,H;M", level }, \
- { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "K,J,N|I,H;M", level }, \
- { namea "3_" nameb "3", opcode|0x00000000, 0xff000000, "I,J,N|H,K;M", level }, \
- { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "J,K;N|H,I,M", level }, \
- { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "K,J,N|H,I,M", level }, \
- { namea "3_" nameb "3", opcode|0x02000000, 0xff000000, "H,K;N|I,J,M", level }, \
- { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "J,K;N|I,H;M", level }, \
- { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "K,J,N|I,H;M", level }, \
- { nameb "_" namea, opcode|0x00000000, 0xff000000, "H,K;M|I,J,N", level }, \
- { nameb "_" namea, opcode|0x01000000, 0xff000000, "H,I,M|J,K;N", level }, \
- { nameb "_" namea, opcode|0x01000000, 0xff000000, "H,I,M|K,J,N", level }, \
- { nameb "_" namea, opcode|0x02000000, 0xff000000, "I,J,M|H,K;N", level }, \
- { nameb "_" namea, opcode|0x03000000, 0xff000000, "I,H;M|J,K;N", level }, \
- { nameb "_" namea, opcode|0x03000000, 0xff000000, "I,H;M|K,J,N", level }, \
- { nameb "3_" namea, opcode|0x00000000, 0xff000000, "H,K;M|I,J,N", level }, \
- { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H,I,M|J,K;N", level }, \
- { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H,I,M|K,J,N", level }, \
- { nameb "3_" namea, opcode|0x02000000, 0xff000000, "I,J,M|H,K;N", level }, \
- { nameb "3_" namea, opcode|0x03000000, 0xff000000, "I,H;M|J,K;N", level }, \
- { nameb "3_" namea, opcode|0x03000000, 0xff000000, "I,H;M|K,J,N", level }, \
- { nameb "_" namea "3", opcode|0x00000000, 0xff000000, "H,K;M|I,J,N", level }, \
- { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H,I,M|J,K;N", level }, \
- { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H,I,M|K,J,N", level }, \
- { nameb "_" namea "3", opcode|0x02000000, 0xff000000, "I,J,M|H,K;N", level }, \
- { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "I,H;M|J,K;N", level }, \
- { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "I,H;M|K,J,N", level }, \
- { nameb "3_" namea "3", opcode|0x00000000, 0xff000000, "H,K;M|I,J,N", level }, \
- { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H,I,M|J,K;N", level }, \
- { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H,I,M|K,J,N", level }, \
- { nameb "3_" namea "3", opcode|0x02000000, 0xff000000, "I,J,M|H,K;N", level }, \
- { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "I,H;M|J,K;N", level }, \
- { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "I,H;M|K,J,N", level }
+ { namea "_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
+ { namea "_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
+ { namea "_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
+ { namea "_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
+ { namea "_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
+ { namea "_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
+ { namea "3_" nameb, opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
+ { namea "3_" nameb, opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
+ { namea "3_" nameb, opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
+ { namea "3_" nameb, opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
+ { namea "3_" nameb, opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
+ { namea "3_" nameb, opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
+ { namea "_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
+ { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
+ { namea "_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
+ { namea "_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
+ { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
+ { namea "_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
+ { namea "3_" nameb "3", opcode|0x00000000, 0xff000000, "i;j;N|H;K;M", level }, \
+ { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "j;K;N|H;i;M", level }, \
+ { namea "3_" nameb "3", opcode|0x01000000, 0xff000000, "K;j;N|H;i;M", level }, \
+ { namea "3_" nameb "3", opcode|0x02000000, 0xff000000, "H;K;N|i;j;M", level }, \
+ { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "j;K;N|i;H;M", level }, \
+ { namea "3_" nameb "3", opcode|0x03000000, 0xff000000, "K;j;N|i;H;M", level }, \
+ { nameb "_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
+ { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
+ { nameb "_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
+ { nameb "_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
+ { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
+ { nameb "_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \
+ { nameb "3_" namea, opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
+ { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
+ { nameb "3_" namea, opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
+ { nameb "3_" namea, opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
+ { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
+ { nameb "3_" namea, opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \
+ { nameb "_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
+ { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
+ { nameb "_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
+ { nameb "_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
+ { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
+ { nameb "_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }, \
+ { nameb "3_" namea "3", opcode|0x00000000, 0xff000000, "H;K;M|i;j;N", level }, \
+ { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|j;K;N", level }, \
+ { nameb "3_" namea "3", opcode|0x01000000, 0xff000000, "H;i;M|K;j;N", level }, \
+ { nameb "3_" namea "3", opcode|0x02000000, 0xff000000, "i;j;M|H;K;N", level }, \
+ { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|j;K;N", level }, \
+ { nameb "3_" namea "3", opcode|0x03000000, 0xff000000, "i;H;M|K;j;N", level }
/* P: General 2-operand operation with parallell store
Syntax: <ia> src2, dst1 || <ib> src3, dst2
- src2 = Indirect 0,1,IR0,IR1 (I)
+ src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
dst1 = Register 0-7 (L)
src3 = Register 0-7 (H)
dst2 = Indirect 0,1,IR0,IR1 (J)
Alias: a||b, b||a
*/
#define P_CLASS_INSN(namea, nameb, opcode, level) \
- { namea "_" nameb, opcode, 0xfe000000, "I,L|H,J", level }, \
- { nameb "_" namea, opcode, 0xfe000000, "H,J|I,L", level }
+ { namea "_" nameb, opcode, 0xfe000000, "i;L|H,J", level }, \
+ { nameb "_" namea, opcode, 0xfe000000, "H,J|i;L", level }
/* Q: General 3-operand operation with parallell store
Syntax: <ia> src1, src2, dst1 || <ib> src3, dst2
src1 = Register 0-7 (K)
- src2 = Indirect 0,1,IR0,IR1 (I)
+ src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
dst1 = Register 0-7 (L)
src3 = Register 0-7 (H)
dst2 = Indirect 0,1,IR0,IR1 (J)
Alias: a||b, b||a, a3||b, b||a3
*/
#define Q_CLASS_INSN(namea, nameb, opcode, level) \
- { namea "_" nameb , opcode, 0xfe000000, "K,I,L|H,J", level }, \
- { nameb "_" namea , opcode, 0xfe000000, "H,J|K,I,L", level }, \
- { namea "3_" nameb , opcode, 0xfe000000, "K,I,L|H,J", level }, \
- { nameb "_" namea "3", opcode, 0xfe000000, "H,J|K,I,L", level }
+ { namea "_" nameb , opcode, 0xfe000000, "K,i;L|H,J", level }, \
+ { nameb "_" namea , opcode, 0xfe000000, "H,J|K,i;L", level }, \
+ { namea "3_" nameb , opcode, 0xfe000000, "K,i;L|H,J", level }, \
+ { nameb "_" namea "3", opcode, 0xfe000000, "H,J|K,i;L", level }
/* QC: General commutative 3-operand operation with parallell store
Syntax: <ia> src2, src1, dst1 || <ib> src3, dst2
<ia> src1, src2, dst1 || <ib> src3, dst2 - Manual
src1 = Register 0-7 (K)
- src2 = Indirect 0,1,IR0,IR1 (I)
+ src2 = Indirect 0,1,IR0,IR1, ENH: register (i)
dst1 = Register 0-7 (L)
src3 = Register 0-7 (H)
dst2 = Indirect 0,1,IR0,IR1 (J)
Alias: a||b, b||a, a3||b, b||a3
*/
#define QC_CLASS_INSN(namea, nameb, opcode, level) \
- { namea "_" nameb , opcode, 0xfe000000, "I,K;L|H,J", level }, \
- { namea "_" nameb , opcode, 0xfe000000, "K,I,L|H,J", level }, \
- { nameb "_" namea , opcode, 0xfe000000, "H,J|I,K;L", level }, \
- { nameb "_" namea , opcode, 0xfe000000, "H,J|K,I,L", level }, \
- { namea "3_" nameb , opcode, 0xfe000000, "I,K;L|H,J", level }, \
- { namea "3_" nameb , opcode, 0xfe000000, "K,I,L|H,J", level }, \
- { nameb "_" namea "3", opcode, 0xfe000000, "H,J|I,K;L", level }, \
- { nameb "_" namea "3", opcode, 0xfe000000, "H,J|K,I,L", level }
+ { namea "_" nameb , opcode, 0xfe000000, "i;K;L|H,J", level }, \
+ { namea "_" nameb , opcode, 0xfe000000, "K;i;L|H,J", level }, \
+ { nameb "_" namea , opcode, 0xfe000000, "H,J|i;K;L", level }, \
+ { nameb "_" namea , opcode, 0xfe000000, "H,J|K;i;L", level }, \
+ { namea "3_" nameb , opcode, 0xfe000000, "i;K;L|H,J", level }, \
+ { namea "3_" nameb , opcode, 0xfe000000, "K;i;L|H,J", level }, \
+ { nameb "_" namea "3", opcode, 0xfe000000, "H,J|i;K;L", level }, \
+ { nameb "_" namea "3", opcode, 0xfe000000, "H,J|K;i;L", level }
/* R: General register integer operation
Syntax: <i> dst
/* Define c3x opcodes for assembler and disassembler. */
-static const c4x_inst_t c3x_insts[] =
+static const c4x_inst_t c4x_insts[] =
{
/* Put synonyms after the desired forms in table so that they get
overwritten in the lookup table. The disassembler will thus
the sti1||sti2 form is used. We also allow sti2||sti1
which is equivalent to the default sti||sti form.
*/
- B_CLASS_INSN( "absf", 0x00000000, OP_C3X ),
- P_CLASS_INSN( "absf", "stf", 0xc8000000, OP_C3X ),
- A_CLASS_INSN( "absi", 0x00800000, OP_C3X ),
- P_CLASS_INSN( "absi", "sti", 0xca000000, OP_C3X ),
- A_CLASS_INSN( "addc", 0x01000000, OP_C3X ),
- TC_CLASS_INSN( "addc", 0x00000000, OP_C3X ),
- B_CLASS_INSN( "addf", 0x01800000, OP_C3X ),
- SC_CLASS_INSN( "addf", 0x00800000, OP_C3X ),
- QC_CLASS_INSN( "addf", "stf", 0xcc000000, OP_C3X ),
- A_CLASS_INSN( "addi", 0x02000000, OP_C3X ),
- TC_CLASS_INSN( "addi", 0x01000000, OP_C3X ),
- QC_CLASS_INSN( "addi", "sti", 0xce000000, OP_C3X ),
- AU_CLASS_INSN( "and", 0x02800000, OP_C3X ),
- TC_CLASS_INSN( "and", 0x01800000, OP_C3X ),
- QC_CLASS_INSN( "and", "sti", 0xd0000000, OP_C3X ),
- AU_CLASS_INSN( "andn", 0x03000000, OP_C3X ),
- T_CLASS_INSN( "andn", 0x02000000, OP_C3X ),
- A_CLASS_INSN( "ash", 0x03800000, OP_C3X ),
- T_CLASS_INSN( "ash", 0x02800000, OP_C3X ),
- Q_CLASS_INSN( "ash", "sti", 0xd2000000, OP_C3X ),
- J_CLASS_INSN( "bB", "b", 0x68000000, OP_C3X ),
- J_CLASS_INSN( "bBd", "bd", 0x68200000, OP_C3X ),
- { "br", 0x60000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */
- { "brd", 0x61000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */
- { "call", 0x62000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */
- { "callB", 0x70000000, 0xffe00000, "Q" , OP_C3X }, /* JS_CLASS */
- { "callB", 0x72000000, 0xffe00000, "P" , OP_C3X }, /* JS_CLASS */
- B_CLASS_INSN( "cmpf", 0x04000000, OP_C3X ),
- S2_CLASS_INSN( "cmpf", 0x03000000, OP_C3X ),
- A_CLASS_INSN( "cmpi", 0x04800000, OP_C3X ),
- T2_CLASS_INSN( "cmpi", 0x03800000, OP_C3X ),
- D_CLASS_INSN( "dbB", "db", 0x6c000000, OP_C3X ),
- D_CLASS_INSN( "dbBd", "dbd", 0x6c200000, OP_C3X ),
- AF_CLASS_INSN( "fix", 0x05000000, OP_C3X ),
- P_CLASS_INSN( "fix", "sti", 0xd4000000, OP_C3X ),
- BI_CLASS_INSN( "float", 0x05800000, OP_C3X ),
- P_CLASS_INSN( "float", "stf", 0xd6000000, OP_C3X ),
- { "iack", 0x1b200000, 0xffe00000, "@" , OP_C3X }, /* Z_CLASS */
- { "iack", 0x1b400000, 0xffe00000, "*" , OP_C3X }, /* Z_CLASS */
- { "idle", 0x06000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */
- { "idle2", 0x06000001, 0xffffffff, "" , OP_IDLE }, /* Z_CLASS */
- B_CLASS_INSN( "lde", 0x06800000, OP_C3X ),
- B_CLASS_INSN( "ldf", 0x07000000, OP_C3X ),
- LL_CLASS_INSN( "ldf", 0xc4000000, OP_C3X ),
- P_CLASS_INSN( "ldf", "stf", 0xd8000000, OP_C3X ),
- BB_CLASS_INSN( "ldfC", 0x00000000, OP_C3X ),
- B6_CLASS_INSN( "ldfi", 0x07800000, OP_C3X ),
- A_CLASS_INSN( "ldi", 0x08000000, OP_C3X ),
- LL_CLASS_INSN( "ldi", 0xc6000000, OP_C3X ),
- P_CLASS_INSN( "ldi", "sti", 0xda000000, OP_C3X ),
- AB_CLASS_INSN( "ldiC", 0x10000000, OP_C3X ),
- A6_CLASS_INSN( "ldii", 0x08800000, OP_C3X ),
- { "ldp", 0x50700000, 0xffff0000, "#" , OP_C3X }, /* Z_CLASS - synonym for ldiu #,dp */
- B_CLASS_INSN( "ldm", 0x09000000, OP_C3X ),
- { "lopower", 0x10800001,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */
- A_CLASS_INSN( "lsh", 0x09800000, OP_C3X ),
- T_CLASS_INSN( "lsh", 0x04000000, OP_C3X ),
- Q_CLASS_INSN( "lsh", "sti", 0xdc000000, OP_C3X ),
- { "maxspeed",0x10800000,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */
- B_CLASS_INSN( "mpyf", 0x0a000000, OP_C3X ),
- SC_CLASS_INSN( "mpyf", 0x04800000, OP_C3X ),
- M_CLASS_INSN( "mpyf", "addf", 0x80000000, OP_C3X ),
- QC_CLASS_INSN( "mpyf", "stf", 0xde000000, OP_C3X ),
- M_CLASS_INSN( "mpyf", "subf", 0x84000000, OP_C3X ),
- A_CLASS_INSN( "mpyi", 0x0a800000, OP_C3X ),
- TC_CLASS_INSN( "mpyi", 0x05000000, OP_C3X ),
- M_CLASS_INSN( "mpyi", "addi", 0x88000000, OP_C3X ),
- QC_CLASS_INSN( "mpyi", "sti", 0xe0000000, OP_C3X ),
- M_CLASS_INSN( "mpyi", "subi", 0x8c000000, OP_C3X ),
- A_CLASS_INSN( "negb", 0x0b000000, OP_C3X ),
- B_CLASS_INSN( "negf", 0x0b800000, OP_C3X ),
- P_CLASS_INSN( "negf", "stf", 0xe2000000, OP_C3X ),
- A_CLASS_INSN( "negi", 0x0c000000, OP_C3X ),
- P_CLASS_INSN( "negi", "sti", 0xe4000000, OP_C3X ),
- A2_CLASS_INSN( "nop", 0x0c800000, OP_C3X ),
- B_CLASS_INSN( "norm", 0x0d000000, OP_C3X ),
- AU_CLASS_INSN( "not", 0x0d800000, OP_C3X ),
- P_CLASS_INSN( "not", "sti", 0xe6000000, OP_C3X ),
- AU_CLASS_INSN( "or", 0x10000000, OP_C3X ),
- TC_CLASS_INSN( "or", 0x05800000, OP_C3X ),
- QC_CLASS_INSN( "or", "sti", 0xe8000000, OP_C3X ),
- R_CLASS_INSN( "pop", 0x0e200000, OP_C3X ),
- RF_CLASS_INSN( "popf", 0x0ea00000, OP_C3X ),
- R_CLASS_INSN( "push", 0x0f200000, OP_C3X ),
- RF_CLASS_INSN( "pushf", 0x0fa00000, OP_C3X ),
- { "retiB", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */
- { "reti", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retiu */
- { "retsB", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */
- { "rets", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retsu */
- B_CLASS_INSN( "rnd", 0x11000000, OP_C3X ),
- R_CLASS_INSN( "rol", 0x11e00001, OP_C3X ),
- R_CLASS_INSN( "rolc", 0x12600001, OP_C3X ),
- R_CLASS_INSN( "ror", 0x12e0ffff, OP_C3X ),
- R_CLASS_INSN( "rorc", 0x1360ffff, OP_C3X ),
- { "rptb", 0x64000000, 0xff000000, "B" , OP_C3X }, /* I2_CLASS */
- { "rptb", 0x79000000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */
- A3_CLASS_INSN( "rpts", 0x139b0000, OP_C3X ),
- { "sigi", 0x16000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */
- A6_CLASS_INSN( "sigi", 0x16000000, OP_C4X ),
- B7_CLASS_INSN( "stf", 0x14000000, OP_C3X ),
- LS_CLASS_INSN( "stf", 0xc0000000, OP_C3X ),
- B7_CLASS_INSN( "stfi", 0x14800000, OP_C3X ),
- A7_CLASS_INSN( "sti", 0x15000000, OP_C3X ),
- { "sti", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Class A7 - Alias for stik */
- { "sti", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Class A7 */
- LS_CLASS_INSN( "sti", 0xc2000000, OP_C3X ),
- A7_CLASS_INSN( "stii", 0x15800000, OP_C3X ),
- A_CLASS_INSN( "subb", 0x16800000, OP_C3X ),
- T_CLASS_INSN( "subb", 0x06000000, OP_C3X ),
- A_CLASS_INSN( "subc", 0x17000000, OP_C3X ),
- B_CLASS_INSN( "subf", 0x17800000, OP_C3X ),
- S_CLASS_INSN( "subf", 0x06800000, OP_C3X ),
- Q_CLASS_INSN( "subf", "stf", 0xea000000, OP_C3X ),
- A_CLASS_INSN( "subi", 0x18000000, OP_C3X ),
- T_CLASS_INSN( "subi", 0x07000000, OP_C3X ),
- Q_CLASS_INSN( "subi", "sti", 0xec000000, OP_C3X ),
- A_CLASS_INSN( "subrb", 0x18800000, OP_C3X ),
- B_CLASS_INSN( "subrf", 0x19000000, OP_C3X ),
- A_CLASS_INSN( "subri", 0x19800000, OP_C3X ),
- { "swi", 0x66000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */
- { "trapB", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS */
- { "trap", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS - Alias for trapu */
- AU_CLASS_INSN( "tstb", 0x1a000000, OP_C3X ),
- T2C_CLASS_INSN("tstb", 0x07800000, OP_C3X ),
- AU_CLASS_INSN( "xor", 0x1a800000, OP_C3X ),
- TC_CLASS_INSN( "xor", 0x08000000, OP_C3X ),
- QC_CLASS_INSN( "xor", "sti", 0xee000000, OP_C3X ),
-
+ B_CLASS_INSN( "absf", 0x00000000, OP_C3X ),
+ P_CLASS_INSN( "absf", "stf", 0xc8000000, OP_C3X ),
+ A_CLASS_INSN( "absi", 0x00800000, OP_C3X ),
+ P_CLASS_INSN( "absi", "sti", 0xca000000, OP_C3X ),
+ A_CLASS_INSN( "addc", 0x01000000, OP_C3X ),
+ TC_CLASS_INSN( "addc", 0x00000000, OP_C3X ),
+ B_CLASS_INSN( "addf", 0x01800000, OP_C3X ),
+ SC_CLASS_INSN( "addf", 0x00800000, OP_C3X ),
+ QC_CLASS_INSN( "addf", "stf", 0xcc000000, OP_C3X ),
+ A_CLASS_INSN( "addi", 0x02000000, OP_C3X ),
+ TC_CLASS_INSN( "addi", 0x01000000, OP_C3X ),
+ QC_CLASS_INSN( "addi", "sti", 0xce000000, OP_C3X ),
+ AU_CLASS_INSN( "and", 0x02800000, OP_C3X ),
+ TC_CLASS_INSN( "and", 0x01800000, OP_C3X ),
+ QC_CLASS_INSN( "and", "sti", 0xd0000000, OP_C3X ),
+ AU_CLASS_INSN( "andn", 0x03000000, OP_C3X ),
+ T_CLASS_INSN( "andn", 0x02000000, OP_C3X ),
+ A_CLASS_INSN( "ash", 0x03800000, OP_C3X ),
+ T_CLASS_INSN( "ash", 0x02800000, OP_C3X ),
+ Q_CLASS_INSN( "ash", "sti", 0xd2000000, OP_C3X ),
+ J_CLASS_INSN( "bB", "b", 0x68000000, OP_C3X ),
+ J_CLASS_INSN( "bBd", "bd", 0x68200000, OP_C3X ),
+ J_CLASS_INSN( "bBaf", "baf", 0x68a00000, OP_C4X ),
+ J_CLASS_INSN( "bBat", "bat", 0x68600000, OP_C4X ),
+ { "br", 0x60000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */
+ { "brd", 0x61000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */
+ { "call", 0x62000000, 0xff000000, "B" , OP_C3X }, /* I_CLASS */
+ { "callB", 0x70000000, 0xffe00000, "Q" , OP_C3X }, /* JS_CLASS */
+ { "callB", 0x72000000, 0xffe00000, "P" , OP_C3X }, /* JS_CLASS */
+ B_CLASS_INSN( "cmpf", 0x04000000, OP_C3X ),
+ S2_CLASS_INSN( "cmpf", 0x03000000, OP_C3X ),
+ A_CLASS_INSN( "cmpi", 0x04800000, OP_C3X ),
+ T2_CLASS_INSN( "cmpi", 0x03800000, OP_C3X ),
+ D_CLASS_INSN( "dbB", "db", 0x6c000000, OP_C3X ),
+ D_CLASS_INSN( "dbBd", "dbd", 0x6c200000, OP_C3X ),
+ AF_CLASS_INSN( "fix", 0x05000000, OP_C3X ),
+ P_CLASS_INSN( "fix", "sti", 0xd4000000, OP_C3X ),
+ BI_CLASS_INSN( "float", 0x05800000, OP_C3X ),
+ P_CLASS_INSN( "float", "stf", 0xd6000000, OP_C3X ),
+ B6_CLASS_INSN( "frieee", 0x1c000000, OP_C4X ),
+ P_CLASS_INSN( "frieee","stf", 0xf2000000, OP_C4X ),
+ { "iack", 0x1b200000, 0xffe00000, "@" , OP_C3X }, /* Z_CLASS */
+ { "iack", 0x1b400000, 0xffe00000, "*" , OP_C3X }, /* Z_CLASS */
+ { "idle", 0x06000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */
+ { "idlez", 0x06000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */
+ { "idle2", 0x06000001, 0xffffffff, "" , OP_IDLE2 }, /* Z_CLASS */
+ { "laj", 0x63000000, 0xff000000, "B" , OP_C4X }, /* I_CLASS */
+ { "lajB", 0x70200000, 0xffe00000, "Q" , OP_C4X }, /* JS_CLASS */
+ { "lajB", 0x72200000, 0xffe00000, "P" , OP_C4X }, /* JS_CLASS */
+ { "latB", 0x74800000, 0xffe00000, "V" , OP_C4X }, /* Z_CLASS */
+ A_CLASS_INSN( "lb0", 0xb0000000, OP_C4X ),
+ A_CLASS_INSN( "lb1", 0xb0800000, OP_C4X ),
+ A_CLASS_INSN( "lb2", 0xb1000000, OP_C4X ),
+ A_CLASS_INSN( "lb3", 0xb1800000, OP_C4X ),
+ AU_CLASS_INSN( "lbu0", 0xb2000000, OP_C4X ),
+ AU_CLASS_INSN( "lbu1", 0xb2800000, OP_C4X ),
+ AU_CLASS_INSN( "lbu2", 0xb3000000, OP_C4X ),
+ AU_CLASS_INSN( "lbu3", 0xb3800000, OP_C4X ),
+ AY_CLASS_INSN( "lda", 0x1e800000, OP_C4X ),
+ B_CLASS_INSN( "lde", 0x06800000, OP_C3X ),
+ { "ldep", 0x76000000, 0xffe00000, "X,R" , OP_C4X }, /* Z_CLASS */
+ B_CLASS_INSN( "ldf", 0x07000000, OP_C3X ),
+ LL_CLASS_INSN( "ldf", 0xc4000000, OP_C3X ),
+ P_CLASS_INSN( "ldf", "stf", 0xd8000000, OP_C3X ),
+ BB_CLASS_INSN( "ldfC", 0x00000000, OP_C3X ),
+ B6_CLASS_INSN( "ldfi", 0x07800000, OP_C3X ),
+ { "ldhi", 0x1fe00000, 0xffe00000, "U,r" , OP_C4X }, /* Z_CLASS */
+ { "ldhi", 0x1fe00000, 0xffe00000, "#,r" , OP_C4X }, /* Z_CLASS */
+ A_CLASS_INSN( "ldi", 0x08000000, OP_C3X ),
+ LL_CLASS_INSN( "ldi", 0xc6000000, OP_C3X ),
+ P_CLASS_INSN( "ldi", "sti", 0xda000000, OP_C3X ),
+ AB_CLASS_INSN( "ldiC", 0x10000000, OP_C3X ),
+ A6_CLASS_INSN( "ldii", 0x08800000, OP_C3X ),
+ { "ldp", 0x50700000, 0xffff0000, "#" , OP_C3X }, /* Z_CLASS - synonym for ldiu #,dp */
+ B_CLASS_INSN( "ldm", 0x09000000, OP_C3X ),
+ { "ldpe", 0x76800000, 0xffe00000, "Q,Z" , OP_C4X }, /* Z_CLASS */
+ { "ldpk", 0x1F700000, 0xffff0000, "#" , OP_C4X }, /* Z_CLASS */
+ A_CLASS_INSN( "lh0", 0xba000000, OP_C4X ),
+ A_CLASS_INSN( "lh1", 0xba800000, OP_C4X ),
+ AU_CLASS_INSN( "lhu0", 0xbb000000, OP_C4X ),
+ AU_CLASS_INSN( "lhu1", 0xbb800000, OP_C4X ),
+ { "lopower", 0x10800001,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */
+ A_CLASS_INSN( "lsh", 0x09800000, OP_C3X ),
+ T_CLASS_INSN( "lsh", 0x04000000, OP_C3X ),
+ Q_CLASS_INSN( "lsh", "sti", 0xdc000000, OP_C3X ),
+ A_CLASS_INSN( "lwl0", 0xb4000000, OP_C4X ),
+ A_CLASS_INSN( "lwl1", 0xb4800000, OP_C4X ),
+ A_CLASS_INSN( "lwl2", 0xb5000000, OP_C4X ),
+ A_CLASS_INSN( "lwl3", 0xb5800000, OP_C4X ),
+ A_CLASS_INSN( "lwr0", 0xb6000000, OP_C4X ),
+ A_CLASS_INSN( "lwr1", 0xb6800000, OP_C4X ),
+ A_CLASS_INSN( "lwr2", 0xb7000000, OP_C4X ),
+ A_CLASS_INSN( "lwr3", 0xb7800000, OP_C4X ),
+ { "maxspeed",0x10800000,0xffffffff, "" , OP_LPWR }, /* Z_CLASS */
+ A_CLASS_INSN( "mb0", 0xb8000000, OP_C4X ),
+ A_CLASS_INSN( "mb1", 0xb8800000, OP_C4X ),
+ A_CLASS_INSN( "mb2", 0xb9000000, OP_C4X ),
+ A_CLASS_INSN( "mb3", 0xb9800000, OP_C4X ),
+ A_CLASS_INSN( "mh0", 0xbc000000, OP_C4X ),
+ A_CLASS_INSN( "mh1", 0xbc800000, OP_C4X ),
+ A_CLASS_INSN( "mh2", 0xbd000000, OP_C4X ),
+ A_CLASS_INSN( "mh3", 0xbd800000, OP_C4X ),
+ B_CLASS_INSN( "mpyf", 0x0a000000, OP_C3X ),
+ SC_CLASS_INSN( "mpyf", 0x04800000, OP_C3X ),
+ M_CLASS_INSN( "mpyf", "addf", 0x80000000, OP_C3X ),
+ QC_CLASS_INSN( "mpyf", "stf", 0xde000000, OP_C3X ),
+ M_CLASS_INSN( "mpyf", "subf", 0x84000000, OP_C3X ),
+ A_CLASS_INSN( "mpyi", 0x0a800000, OP_C3X ),
+ TC_CLASS_INSN( "mpyi", 0x05000000, OP_C3X ),
+ M_CLASS_INSN( "mpyi", "addi", 0x88000000, OP_C3X ),
+ QC_CLASS_INSN( "mpyi", "sti", 0xe0000000, OP_C3X ),
+ M_CLASS_INSN( "mpyi", "subi", 0x8c000000, OP_C3X ),
+ A_CLASS_INSN( "mpyshi", 0x1d800000, OP_C4X ),
+ TC_CLASS_INSN( "mpyshi", 0x28800000, OP_C4X ),
+ A_CLASS_INSN( "mpyuhi", 0x1e000000, OP_C4X ),
+ TC_CLASS_INSN( "mpyuhi", 0x29000000, OP_C4X ),
+ A_CLASS_INSN( "negb", 0x0b000000, OP_C3X ),
+ B_CLASS_INSN( "negf", 0x0b800000, OP_C3X ),
+ P_CLASS_INSN( "negf", "stf", 0xe2000000, OP_C3X ),
+ A_CLASS_INSN( "negi", 0x0c000000, OP_C3X ),
+ P_CLASS_INSN( "negi", "sti", 0xe4000000, OP_C3X ),
+ A2_CLASS_INSN( "nop", 0x0c800000, OP_C3X ),
+ B_CLASS_INSN( "norm", 0x0d000000, OP_C3X ),
+ AU_CLASS_INSN( "not", 0x0d800000, OP_C3X ),
+ P_CLASS_INSN( "not", "sti", 0xe6000000, OP_C3X ),
+ AU_CLASS_INSN( "or", 0x10000000, OP_C3X ),
+ TC_CLASS_INSN( "or", 0x05800000, OP_C3X ),
+ QC_CLASS_INSN( "or", "sti", 0xe8000000, OP_C3X ),
+ R_CLASS_INSN( "pop", 0x0e200000, OP_C3X ),
+ RF_CLASS_INSN( "popf", 0x0ea00000, OP_C3X ),
+ R_CLASS_INSN( "push", 0x0f200000, OP_C3X ),
+ RF_CLASS_INSN( "pushf", 0x0fa00000, OP_C3X ),
+ BA_CLASS_INSN( "rcpf", 0x1d000000, OP_C4X ),
+ { "retiB", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */
+ { "reti", 0x78000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retiu */
+ { "retiBd", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS */
+ { "retid", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS - Alias for retiud */
+ { "retsB", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */
+ { "rets", 0x78800000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS - Alias for retsu */
+ B_CLASS_INSN( "rnd", 0x11000000, OP_C3X ),
+ R_CLASS_INSN( "rol", 0x11e00001, OP_C3X ),
+ R_CLASS_INSN( "rolc", 0x12600001, OP_C3X ),
+ R_CLASS_INSN( "ror", 0x12e0ffff, OP_C3X ),
+ R_CLASS_INSN( "rorc", 0x1360ffff, OP_C3X ),
+ { "rptb", 0x64000000, 0xff000000, "B" , OP_C3X }, /* I2_CLASS */
+ { "rptb", 0x79000000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */
+ { "rptbd", 0x65000000, 0xff000000, "B" , OP_C4X }, /* I2_CLASS */
+ { "rptbd", 0x79800000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */
+ A3_CLASS_INSN( "rpts", 0x139b0000, OP_C3X ),
+ B_CLASS_INSN( "rsqrf", 0x1c800000, OP_C4X ),
+ { "sigi", 0x16000000, 0xffe00000, "" , OP_C3X }, /* Z_CLASS */
+ A6_CLASS_INSN( "sigi", 0x16000000, OP_C4X ),
+ B7_CLASS_INSN( "stf", 0x14000000, OP_C3X ),
+ LS_CLASS_INSN( "stf", 0xc0000000, OP_C3X ),
+ B7_CLASS_INSN( "stfi", 0x14800000, OP_C3X ),
+ A7_CLASS_INSN( "sti", 0x15000000, OP_C3X ),
+ { "sti", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Class A7 - Alias for stik */
+ { "sti", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Class A7 */
+ LS_CLASS_INSN( "sti", 0xc2000000, OP_C3X ),
+ A7_CLASS_INSN( "stii", 0x15800000, OP_C3X ),
+ { "stik", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Z_CLASS */
+ { "stik", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Z_CLASS */
+ A_CLASS_INSN( "subb", 0x16800000, OP_C3X ),
+ T_CLASS_INSN( "subb", 0x06000000, OP_C3X ),
+ A_CLASS_INSN( "subc", 0x17000000, OP_C3X ),
+ B_CLASS_INSN( "subf", 0x17800000, OP_C3X ),
+ S_CLASS_INSN( "subf", 0x06800000, OP_C3X ),
+ Q_CLASS_INSN( "subf", "stf", 0xea000000, OP_C3X ),
+ A_CLASS_INSN( "subi", 0x18000000, OP_C3X ),
+ T_CLASS_INSN( "subi", 0x07000000, OP_C3X ),
+ Q_CLASS_INSN( "subi", "sti", 0xec000000, OP_C3X ),
+ A_CLASS_INSN( "subrb", 0x18800000, OP_C3X ),
+ B_CLASS_INSN( "subrf", 0x19000000, OP_C3X ),
+ A_CLASS_INSN( "subri", 0x19800000, OP_C3X ),
+ { "swi", 0x66000000, 0xffffffff, "" , OP_C3X }, /* Z_CLASS */
+ B_CLASS_INSN( "toieee", 0x1b800000, OP_C4X ),
+ P_CLASS_INSN( "toieee","stf", 0xf0000000, OP_C4X ),
+ { "trapB", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS */
+ { "trap", 0x74000000, 0xffe00000, "V" , OP_C3X }, /* Z_CLASS - Alias for trapu */
+ AU_CLASS_INSN( "tstb", 0x1a000000, OP_C3X ),
+ T2C_CLASS_INSN("tstb", 0x07800000, OP_C3X ),
+ AU_CLASS_INSN( "xor", 0x1a800000, OP_C3X ),
+ TC_CLASS_INSN( "xor", 0x08000000, OP_C3X ),
+ QC_CLASS_INSN( "xor", "sti", 0xee000000, OP_C3X ),
+
/* Dummy entry, not included in c3x_num_insts. This
lets code examine entry i + 1 without checking
if we've run off the end of the table. */
{ "", 0x0, 0x00, "", 0 }
};
-const unsigned int c3x_num_insts = (((sizeof c3x_insts) / (sizeof c3x_insts[0])) - 1);
-
-/* Define c4x additional opcodes for assembler and disassembler. */
-static const c4x_inst_t c4x_insts[] =
-{
- J_CLASS_INSN( "bBaf", "baf", 0x68a00000, OP_C4X ),
- J_CLASS_INSN( "bBat", "bat", 0x68600000, OP_C4X ),
- B6_CLASS_INSN( "frieee", 0x1c000000, OP_C4X ),
- P_CLASS_INSN( "frieee","stf", 0xf2000000, OP_C4X ),
- { "laj", 0x63000000, 0xff000000, "B" , OP_C4X }, /* I_CLASS */
- { "lajB", 0x70200000, 0xffe00000, "Q" , OP_C4X }, /* JS_CLASS */
- { "lajB", 0x72200000, 0xffe00000, "P" , OP_C4X }, /* JS_CLASS */
- { "latB", 0x74800000, 0xffe00000, "V" , OP_C4X }, /* Z_CLASS */
- A_CLASS_INSN( "lb0", 0xb0000000, OP_C4X ),
- A_CLASS_INSN( "lb1", 0xb0800000, OP_C4X ),
- A_CLASS_INSN( "lb2", 0xb1000000, OP_C4X ),
- A_CLASS_INSN( "lb3", 0xb1800000, OP_C4X ),
- AU_CLASS_INSN( "lbu0", 0xb2000000, OP_C4X ),
- AU_CLASS_INSN( "lbu1", 0xb2800000, OP_C4X ),
- AU_CLASS_INSN( "lbu2", 0xb3000000, OP_C4X ),
- AU_CLASS_INSN( "lbu3", 0xb3800000, OP_C4X ),
- AY_CLASS_INSN( "lda", 0x1e800000, OP_C4X ),
- { "ldep", 0x76000000, 0xffe00000, "X,R" , OP_C4X }, /* Z_CLASS */
- { "ldhi", 0x1fe00000, 0xffe00000, "U,r" , OP_C4X }, /* Z_CLASS */
- { "ldhi", 0x1fe00000, 0xffe00000, "#,r" , OP_C4X }, /* Z_CLASS */
- { "ldpe", 0x76800000, 0xffe00000, "Q,Z" , OP_C4X }, /* Z_CLASS */
- { "ldpk", 0x1F700000, 0xffff0000, "#" , OP_C4X }, /* Z_CLASS */
- A_CLASS_INSN( "lh0", 0xba000000, OP_C4X ),
- A_CLASS_INSN( "lh1", 0xba800000, OP_C4X ),
- AU_CLASS_INSN( "lhu0", 0xbb000000, OP_C4X ),
- AU_CLASS_INSN( "lhu1", 0xbb800000, OP_C4X ),
- A_CLASS_INSN( "lwl0", 0xb4000000, OP_C4X ),
- A_CLASS_INSN( "lwl1", 0xb4800000, OP_C4X ),
- A_CLASS_INSN( "lwl2", 0xb5000000, OP_C4X ),
- A_CLASS_INSN( "lwl3", 0xb5800000, OP_C4X ),
- A_CLASS_INSN( "lwr0", 0xb6000000, OP_C4X ),
- A_CLASS_INSN( "lwr1", 0xb6800000, OP_C4X ),
- A_CLASS_INSN( "lwr2", 0xb7000000, OP_C4X ),
- A_CLASS_INSN( "lwr3", 0xb7800000, OP_C4X ),
- A_CLASS_INSN( "mb0", 0xb8000000, OP_C4X ),
- A_CLASS_INSN( "mb1", 0xb8800000, OP_C4X ),
- A_CLASS_INSN( "mb2", 0xb9000000, OP_C4X ),
- A_CLASS_INSN( "mb3", 0xb9800000, OP_C4X ),
- A_CLASS_INSN( "mh0", 0xbc000000, OP_C4X ),
- A_CLASS_INSN( "mh1", 0xbc800000, OP_C4X ),
- A_CLASS_INSN( "mh2", 0xbd000000, OP_C4X ),
- A_CLASS_INSN( "mh3", 0xbd800000, OP_C4X ),
- A_CLASS_INSN( "mpyshi", 0x1d800000, OP_C4X ),
- TC_CLASS_INSN( "mpyshi", 0x28800000, OP_C4X ),
- A_CLASS_INSN( "mpyuhi", 0x1e000000, OP_C4X ),
- TC_CLASS_INSN( "mpyuhi", 0x29000000, OP_C4X ),
- BA_CLASS_INSN( "rcpf", 0x1d000000, OP_C4X ),
- { "retiBd", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS */
- { "retid", 0x78200000, 0xffe00000, "" , OP_C4X }, /* Z_CLASS - Alias for retiud */
- { "rptbd", 0x65000000, 0xff000000, "B" , OP_C4X }, /* I2_CLASS */
- { "rptbd", 0x79800000, 0xff000000, "Q" , OP_C4X }, /* I2_CLASS */
- B_CLASS_INSN( "rsqrf", 0x1c800000, OP_C4X ),
- { "stik", 0x15000000, 0xffe00000, "T,@" , OP_C4X }, /* Z_CLASS */
- { "stik", 0x15600000, 0xffe00000, "T,*" , OP_C4X }, /* Z_CLASS */
- B_CLASS_INSN( "toieee", 0x1b800000, OP_C4X ),
- P_CLASS_INSN( "toieee","stf", 0xf0000000, OP_C4X ),
-
- /* Dummy entry, not included in num_insts. This
- lets code examine entry i+1 without checking
- if we've run off the end of the table. */
- { "", 0x0, 0x00, "", 0 }
-};
-
const unsigned int c4x_num_insts = (((sizeof c4x_insts) / (sizeof c4x_insts[0])) - 1);
-
-
-struct c4x_cond
-{
- char * name;
- unsigned long cond;
-};
-
-typedef struct c4x_cond c4x_cond_t;
-
-/* Define conditional branch/load suffixes. Put desired form for
- disassembler last. */
-static const c4x_cond_t c4x_conds[] =
-{
- { "u", 0x00 },
- { "c", 0x01 }, { "lo", 0x01 },
- { "ls", 0x02 },
- { "hi", 0x03 },
- { "nc", 0x04 }, { "hs", 0x04 },
- { "z", 0x05 }, { "eq", 0x05 },
- { "nz", 0x06 }, { "ne", 0x06 },
- { "n", 0x07 }, { "l", 0x07 }, { "lt", 0x07 },
- { "le", 0x08 },
- { "p", 0x09 }, { "gt", 0x09 },
- { "nn", 0x0a }, { "ge", 0x0a },
- { "nv", 0x0c },
- { "v", 0x0d },
- { "nuf", 0x0e },
- { "uf", 0x0f },
- { "nlv", 0x10 },
- { "lv", 0x11 },
- { "nluf", 0x12 },
- { "luf", 0x13 },
- { "zuf", 0x14 },
- /* Dummy entry, not included in num_conds. This
- lets code examine entry i+1 without checking
- if we've run off the end of the table. */
- { "", 0x0}
-};
-
-const unsigned int num_conds = (((sizeof c4x_conds) / (sizeof c4x_conds[0])) - 1);
-
-struct c4x_indirect
-{
- char * name;
- unsigned long modn;
-};
-
-typedef struct c4x_indirect c4x_indirect_t;
-
-/* Define indirect addressing modes where:
- d displacement (signed)
- y ir0
- z ir1 */
-
-static const c4x_indirect_t c4x_indirects[] =
-{
- { "*+a(d)", 0x00 },
- { "*-a(d)", 0x01 },
- { "*++a(d)", 0x02 },
- { "*--a(d)", 0x03 },
- { "*a++(d)", 0x04 },
- { "*a--(d)", 0x05 },
- { "*a++(d)%", 0x06 },
- { "*a--(d)%", 0x07 },
- { "*+a(y)", 0x08 },
- { "*-a(y)", 0x09 },
- { "*++a(y)", 0x0a },
- { "*--a(y)", 0x0b },
- { "*a++(y)", 0x0c },
- { "*a--(y)", 0x0d },
- { "*a++(y)%", 0x0e },
- { "*a--(y)%", 0x0f },
- { "*+a(z)", 0x10 },
- { "*-a(z)", 0x11 },
- { "*++a(z)", 0x12 },
- { "*--a(z)", 0x13 },
- { "*a++(z)", 0x14 },
- { "*a--(z)", 0x15 },
- { "*a++(z)%", 0x16 },
- { "*a--(z)%", 0x17 },
- { "*a", 0x18 },
- { "*a++(y)b", 0x19 },
- /* Dummy entry, not included in num_indirects. This
- lets code examine entry i+1 without checking
- if we've run off the end of the table. */
- { "", 0x0}
-};
-
-#define C3X_MODN_MAX 0x19
-
-const unsigned int num_indirects = (((sizeof c4x_indirects) / (sizeof c4x_indirects[0])) - 1);
+2002-11-18 Svein E. Seldal <Svein.Seldal@solidas.com>
+
+ * tic4x-dis.c: Added support for enhanced and special insn.
+ (c4x_print_op): Added insn class 'i' and 'j'
+ (c4x_hash_opcode_special): Add to support special insn
+ (c4x_hash_opcode): Update to support the new opcode-list
+ format. Add support for the new special insns.
+ (c4x_disassemble): New opcode-list support.
+
2002-11-16 Klee Dienes <kdienes@apple.com>
* m88k-dis.c: Include libiberty.h (for xmalloc).
#define C4X_DEBUG 0
-#define C4X_HASH_SIZE 11 /* 11 and above should give unique entries. */
+#define C4X_HASH_SIZE 11 /* 11 (bits) and above should give unique entries. */
+#define C4X_SPESOP_SIZE 8 /* Max 8. ops for special instructions */
typedef enum
{
static int c4x_dp = 0;
static int c4x_pc_offset
- PARAMS ((unsigned int));
+ PARAMS ((unsigned int));
static int c4x_print_char
- PARAMS ((struct disassemble_info *, char));
+ PARAMS ((struct disassemble_info *, char));
static int c4x_print_str
- PARAMS ((struct disassemble_info *, char *));
+ PARAMS ((struct disassemble_info *, char *));
static int c4x_print_register
- PARAMS ((struct disassemble_info *, unsigned long));
+ PARAMS ((struct disassemble_info *, unsigned long));
static int c4x_print_addr
- PARAMS ((struct disassemble_info *, unsigned long));
+ PARAMS ((struct disassemble_info *, unsigned long));
static int c4x_print_relative
- PARAMS ((struct disassemble_info *, unsigned long, long, unsigned long));
+ PARAMS ((struct disassemble_info *, unsigned long, long, unsigned long));
void c4x_print_ftoa
- PARAMS ((unsigned int, FILE *, fprintf_ftype));
+ PARAMS ((unsigned int, FILE *, fprintf_ftype));
static int c4x_print_direct
- PARAMS ((struct disassemble_info *, unsigned long));
+ PARAMS ((struct disassemble_info *, unsigned long));
static int c4x_print_immed
- PARAMS ((struct disassemble_info *, immed_t, unsigned long));
+ PARAMS ((struct disassemble_info *, immed_t, unsigned long));
static int c4x_print_cond
- PARAMS ((struct disassemble_info *, unsigned int));
+ PARAMS ((struct disassemble_info *, unsigned int));
static int c4x_print_indirect
- PARAMS ((struct disassemble_info *, indirect_t, unsigned long));
+ PARAMS ((struct disassemble_info *, indirect_t, unsigned long));
static int c4x_print_op
- PARAMS ((struct disassemble_info *, unsigned long, c4x_inst_t *, unsigned long));
+ PARAMS ((struct disassemble_info *, unsigned long, c4x_inst_t *, unsigned long));
+static void c4x_hash_opcode_special
+ PARAMS ((c4x_inst_t **, const c4x_inst_t *));
static void c4x_hash_opcode
- PARAMS ((c4x_inst_t **, const c4x_inst_t *));
+ PARAMS ((c4x_inst_t **, c4x_inst_t **, const c4x_inst_t *, unsigned long));
static int c4x_disassemble
- PARAMS ((unsigned long, unsigned long, struct disassemble_info *));
+ PARAMS ((unsigned long, unsigned long, struct disassemble_info *));
int print_insn_tic4x
- PARAMS ((bfd_vma, struct disassemble_info *));
+ PARAMS ((bfd_vma, struct disassemble_info *));
static int
EXTRU (instruction, 15, 0));
break;
+ case 'i': /* Extended indirect 0--7 */
+ if ( EXTRU (instruction, 7, 5) == 7 )
+ {
+ if( !c4x_print_register (info, EXTRU (instruction, 4, 0)) )
+ return 0;
+ break;
+ }
+ /* Fallthrough */
+
case 'I': /* indirect (short) 0--7 */
if (! c4x_print_indirect (info, INDIRECT_SHORT,
EXTRU (instruction, 7, 0)))
return 0;
break;
+ case 'j': /* Extended indirect 8--15 */
+ if ( EXTRU (instruction, 15, 13) == 7 )
+ {
+ if( !c4x_print_register (info, EXTRU (instruction, 12, 8)) )
+ return 0;
+ break;
+ }
+
case 'J': /* indirect (short) 8--15 */
if (! c4x_print_indirect (info, INDIRECT_SHORT,
EXTRU (instruction, 15, 8)))
}
static void
-c4x_hash_opcode (optable, inst)
+c4x_hash_opcode_special (optable_special, inst)
+ c4x_inst_t **optable_special;
+ const c4x_inst_t *inst;
+{
+ int i;
+
+ for( i=0; i<C4X_SPESOP_SIZE; i++ )
+ if( optable_special[i] != NULL
+ && optable_special[i]->opcode == inst->opcode )
+ {
+ /* Collision (we have it already) - overwrite */
+ optable_special[i] = (void *)inst;
+ return;
+ }
+
+ for( i=0; i<C4X_SPESOP_SIZE; i++ )
+ if( optable_special[i] == NULL )
+ {
+ /* Add the new opcode */
+ optable_special[i] = (void *)inst;
+ return;
+ }
+
+ /* This should never occur. This happens if the number of special
+ instructions exceeds C4X_SPESOP_SIZE. Please increase the variable
+ of this variable */
+#if C4X_DEBUG
+ printf("optable_special[] is full, please increase C4X_SPESOP_SIZE!\n");
+#endif
+}
+
+static void
+c4x_hash_opcode (optable, optable_special, inst, c4x_oplevel)
c4x_inst_t **optable;
+ c4x_inst_t **optable_special;
const c4x_inst_t *inst;
+ const unsigned long c4x_oplevel;
{
int j;
int opcode = inst->opcode >> (32 - C4X_HASH_SIZE);
have unique entries so there's no point having a linked list
for each entry? */
for (j = opcode; j < opmask; j++)
- if ((j & opmask) == opcode)
+ if ( (j & opmask) == opcode
+ && inst->oplevel & c4x_oplevel )
{
#if C4X_DEBUG
/* We should only have collisions for synonyms like
printf("Collision at index %d, %s and %s\n",
j, optable[j]->name, inst->name);
#endif
- optable[j] = (void *)inst;
+ /* Catch those ops that collide with others already inside the
+ hash, and have a opmask greater than the one we use in the
+ hash. Store them in a special-list, that will handle full
+ 32-bit INSN, not only the first 11-bit (or so). */
+ if ( optable[j] != NULL
+ && inst->opmask & ~(opmask << (32 - C4X_HASH_SIZE)) )
+ {
+ /* Add the instruction already on the list */
+ c4x_hash_opcode_special(optable_special, optable[j]);
+
+ /* Add the new instruction */
+ c4x_hash_opcode_special(optable_special, inst);
+ }
+
+ optable[j] = (void *)inst;
}
}
struct disassemble_info *info;
{
static c4x_inst_t **optable = NULL;
+ static c4x_inst_t **optable_special = NULL;
c4x_inst_t *p;
int i;
+ unsigned long c4x_oplevel;
c4x_version = info->mach;
+
+ c4x_oplevel = (IS_CPU_C4X (c4x_version)) ? OP_C4X : 0;
+ c4x_oplevel |= OP_C3X|OP_LPWR|OP_IDLE2|OP_ENH;
if (optable == NULL)
{
optable = (c4x_inst_t **)
xcalloc (sizeof (c4x_inst_t *), (1 << C4X_HASH_SIZE));
+
+ optable_special = (c4x_inst_t **)
+ xcalloc (sizeof (c4x_inst_t *), C4X_SPESOP_SIZE );
+
/* Install opcodes in reverse order so that preferred
forms overwrite synonyms. */
- for (i = c3x_num_insts - 1; i >= 0; i--)
- c4x_hash_opcode (optable, &c3x_insts[i]);
- if (IS_CPU_C4X (c4x_version))
- {
- for (i = c4x_num_insts - 1; i >= 0; i--)
- c4x_hash_opcode (optable, &c4x_insts[i]);
- }
+ for (i = c4x_num_insts - 1; i >= 0; i--)
+ c4x_hash_opcode (optable, optable_special, &c4x_insts[i], c4x_oplevel);
+
+ /* We now need to remove the insn that are special from the
+ "normal" optable, to make the disasm search this extra list
+ for them.
+ */
+ for (i=0; i<C4X_SPESOP_SIZE; i++)
+ if ( optable_special[i] != NULL )
+ optable[optable_special[i]->opcode >> (32 - C4X_HASH_SIZE)] = NULL;
}
/* See if we can pick up any loading of the DP register... */
if ((instruction >> 16) == 0x5070 || (instruction >> 16) == 0x1f70)
c4x_dp = EXTRU (instruction, 15, 0);
-
+
p = optable[instruction >> (32 - C4X_HASH_SIZE)];
- if (p != NULL && ((instruction & p->opmask) == p->opcode)
- && c4x_print_op (NULL, instruction, p, pc))
- c4x_print_op (info, instruction, p, pc);
+ if ( p != NULL )
+ {
+ if ( ((instruction & p->opmask) == p->opcode)
+ && c4x_print_op (NULL, instruction, p, pc) )
+ c4x_print_op (info, instruction, p, pc);
+ else
+ (*info->fprintf_func) (info->stream, "%08x", instruction);
+ }
else
- (*info->fprintf_func) (info->stream, "%08x", instruction);
+ {
+ for (i = 0; i<C4X_SPESOP_SIZE; i++)
+ if (optable_special[i] != NULL
+ && optable_special[i]->opcode == instruction )
+ {
+ (*info->fprintf_func)(info->stream, "%s", optable_special[i]->name);
+ break;
+ }
+ if (i==C4X_SPESOP_SIZE)
+ (*info->fprintf_func) (info->stream, "%08x", instruction);
+ }
/* Return size of insn in words. */
return 1;
projects / binutils-gdb.git / commitdiff