radv: remove radv_get_image_cmask_info()

It's unnecessary to duplicate fields in another struct.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 0065b15dfdfc4c08e4fcc401cad460ccc90d8abb..b1da5815f48f80669031a202d8409ee1d54edd75 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -4408,7 +4408,7 @@ radv_initialise_color_surface(struct radv_device *device,
 
                cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
                cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
-               cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
+               cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
 
                cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
 
@@ -4428,7 +4428,7 @@ radv_initialise_color_surface(struct radv_device *device,
 
        /* CMASK variables */
        va = radv_buffer_get_va(iview->bo) + iview->image->offset;
-       va += iview->image->cmask.offset;
+       va += iview->image->cmask_offset;
        cb->cb_color_cmask = va >> 8;
 
        va = radv_buffer_get_va(iview->bo) + iview->image->offset;

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 221b554e73e52b772238a58657a088bf72d93c7d..ce12bb61fb9cb03e9bc7e2cdd7a4ca0f9305da81 100644 (file)
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -937,7 +937,7 @@ si_make_texture_descriptor(struct radv_device *device,
                                          S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
 
                        if (radv_image_is_tc_compat_cmask(image)) {
-                               va = gpu_address + image->offset + image->cmask.offset;
+                               va = gpu_address + image->offset + image->cmask_offset;
 
                                fmask_state[5] |= S_008F24_META_DATA_ADDRESS(va >> 40);
                                fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
@@ -950,7 +950,7 @@ si_make_texture_descriptor(struct radv_device *device,
                        fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
 
                        if (radv_image_is_tc_compat_cmask(image)) {
-                               va = gpu_address + image->offset + image->cmask.offset;
+                               va = gpu_address + image->offset + image->cmask_offset;
 
                                fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
                                fmask_state[7] |= va >> 8;
@@ -1136,45 +1136,27 @@ radv_image_alloc_fmask(struct radv_device *device,
        image->alignment = MAX2(image->alignment, image->fmask.alignment);
 }
 
-static void
-radv_image_get_cmask_info(struct radv_device *device,
-                         struct radv_image *image,
-                         struct radv_cmask_info *out)
-{
-       assert(image->plane_count == 1);
-
-       if (device->physical_device->rad_info.chip_class >= GFX9) {
-               out->alignment = image->planes[0].surface.cmask_alignment;
-               out->size = image->planes[0].surface.cmask_size;
-               return;
-       }
-
-       out->slice_tile_max = image->planes[0].surface.u.legacy.cmask_slice_tile_max;
-       out->alignment = image->planes[0].surface.cmask_alignment;
-       out->slice_size = image->planes[0].surface.cmask_slice_size;
-       out->size = image->planes[0].surface.cmask_size;
-}
-
 static void
 radv_image_alloc_cmask(struct radv_device *device,
                       struct radv_image *image)
 {
+       unsigned cmask_alignment = image->planes[0].surface.cmask_alignment;
+       unsigned cmask_size = image->planes[0].surface.cmask_size;
        uint32_t clear_value_size = 0;
-       radv_image_get_cmask_info(device, image, &image->cmask);
 
-       if (!image->cmask.size)
+       if (!cmask_size)
                return;
 
-       assert(image->cmask.alignment);
+       assert(cmask_alignment);
 
-       image->cmask.offset = align64(image->size, image->cmask.alignment);
+       image->cmask_offset = align64(image->size, cmask_alignment);
        /* + 8 for storing the clear values */
        if (!image->clear_value_offset) {
-               image->clear_value_offset = image->cmask.offset + image->cmask.size;
+               image->clear_value_offset = image->cmask_offset + cmask_size;
                clear_value_size = 8;
        }
-       image->size = image->cmask.offset + image->cmask.size + clear_value_size;
-       image->alignment = MAX2(image->alignment, image->cmask.alignment);
+       image->size = image->cmask_offset + cmask_size + clear_value_size;
+       image->alignment = MAX2(image->alignment, cmask_alignment);
 }
 
 static void

diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 8ddc2e38cd4bc54f54cd9bf12acb37194228319f..e6e96a103f164d408a451286f8eeae5cccc8e9cd 100644 (file)
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1330,15 +1330,18 @@ radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
                 struct radv_image *image,
                 const VkImageSubresourceRange *range, uint32_t value)
 {
-       uint64_t offset = image->offset + image->cmask.offset;
+       uint64_t offset = image->offset + image->cmask_offset;
        uint64_t size;
 
        if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
                /* TODO: clear layers. */
-               size = image->cmask.size;
+               size = image->planes[0].surface.cmask_size;
        } else {
-               offset += image->cmask.slice_size * range->baseArrayLayer;
-               size = image->cmask.slice_size * radv_get_layerCount(image, range);
+               unsigned cmask_slice_size =
+                       image->planes[0].surface.cmask_slice_size;
+
+               offset += cmask_slice_size * range->baseArrayLayer;
+               size = cmask_slice_size * radv_get_layerCount(image, range);
        }
 
        return radv_fill_buffer(cmd_buffer, image->bo, offset, size, value);

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 1a0b22d63b85ab822ba57761f8ba6e88cc4930c5..33c2d4b8620b296a49cdfeb10bd7094c1b36be5c 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1561,15 +1561,6 @@ struct radv_fmask_info {
        uint64_t slice_size;
 };
 
-struct radv_cmask_info {
-       uint64_t offset;
-       uint64_t size;
-       unsigned alignment;
-       unsigned slice_tile_max;
-       unsigned slice_size;
-};
-
-
 struct radv_image_plane {
        VkFormat format;
        struct radeon_surf surface;
@@ -1604,7 +1595,7 @@ struct radv_image {
        bool tc_compatible_cmask;
 
        struct radv_fmask_info fmask;
-       struct radv_cmask_info cmask;
+       uint64_t cmask_offset;
        uint64_t clear_value_offset;
        uint64_t fce_pred_offset;
        uint64_t dcc_pred_offset;
@@ -1654,7 +1645,7 @@ bool radv_layout_dcc_compressed(const struct radv_image *image,
 static inline bool
 radv_image_has_cmask(const struct radv_image *image)
 {
-       return image->cmask.size;
+       return image->planes[0].surface.cmask_size;
 }
 
 /**