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diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index aad393606e8ad98f3507800a23df6d2fcf8b3b61..8bd65546a21b1a796171ca78bff4c049e20be9cd 100644 (file)
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -223,10 +223,12 @@ and therefore have no value are marked with 'NOT'
 
 Image of JTAG jumper wire connections on ULX3S FPGA side
 
-[[!img HDL_workflow/ulx3s_fpga_jtag_wires.jpg size="200x" ]] 
+[[!img HDL_workflow/ulx3s_fpga_jtag_wires.jpg size="500x" ]] 
 
 Image of JTAG jumper wire connections on ft232r side
 
+[[!img HDL_workflow/ft232r_jtag_wires.jpg size="500x" ]] 
+
 # VERSA ECP5 Connections
 
 Table of connections: