(no commit message)

diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn
index 9e832390b0c92d0023495503c5b02ac18291c0df..b08ff553f389fb4de5c8b0ae6e793ebae9fa144a 100644 (file)
--- a/openpower/sv/remap.mdwn
+++ b/openpower/sv/remap.mdwn
@@ -120,6 +120,64 @@ which have the same format.
 
 [[!inline raw="yes" pages="openpower/sv/shape_table_format" ]]
 
+# svshape instruction
+
+`svshape` is a convenience instruction that reduces instruction
+count for common usage patterns, particularly Matrix, DCT and FFT. It sets up
+(overwrites) all required SVSHAPE SPRs and also modifies SVSTATE
+including VL and MAXVL. Using `svshape` therefore does not also
+require `setvl`.
+
+Form: SVM-Form SV "Matrix" Form (see [[isatables/fields.text]])
+
+    svshape SVxd,SVyd,SVzd,SVRM,vf
+
+| 0.5|6.10  |11.15  |16..20 | 21..25 | 25 | 26..30 |31|  name    |
+| -- | --   | ---   | ----- | ------ | -- | ------ |--| -------- |
+|OPCD| SVxd | SVyd  | SVzd  | SVRM   | vf | XO     |/ | svstate  |
+
+Fields:
+
+* **SVxd** - SV REMAP "xdim" (SVGPR>>1 for Indexed REMAP)
+* **SVyd** - SV REMAP "ydim"
+* **SVzd** - SV REMAP "zdim"
+* **SVRM** - SV REMAP Mode (0b00000 for Matrix, 0b00001 for FFT etc.)
+* **vf** - sets "Vertical-First" mode
+* **XO** - standard 5-bit XO field
+
+| SVRM   | Remap Mode description |
+| --     | --              |
+| 0b0000 | Matrix 1/2/3D    |
+| 0b0001 | FFT Butterfly   |
+| 0b0010 | DCT Inner butterfly, pre-calculated coefficients |
+| 0b0011 | DCT Outer butterfly  |
+| 0b0100 | DCT Inner butterfly, on-the-fly (Vertical-First Mode) |
+| 0b0101 | DCT COS table index generation |
+| 0b0110 | DCT half-swap   |
+| 0b0111 | reserved  |
+| 0b1000 | Indexed (XY straight) |
+| 0b1001 | Indexed (YX swapped)  |
+| 0b1010 | iDCT Inner butterfly, pre-calculated coefficients |
+| 0b1011 | iDCT Outer butterfly  |
+| 0b1100 | iDCT Inner butterfly, on-the-fly (Vertical-First Mode) |
+| 0b1101 | iDCT COS table index generation |
+| 0b1110 | iDCT half-swap   |
+| 0b1111 | FFT half-swap   |
+
+Examples showing how all of these Modes operate exists in the online
+[SVP64 unit tests](https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/decoder/isa;hb=HEAD)
+
+In Indexed Mode, there are only 5 bits available to specify the GPR
+to use, out of 128 GPRs (7 bit numbering).  Therefore, only the top
+5 bits are given in the `SVxd` field: the bottom two implicit bits
+will be zero (`SVxd || 0b00`).
+
+`svshape` has *limited applicability* due to being a 32-bit instruction.
+The full capability of SVSHAPE SPRs may be accessed by directly writing
+to SVSHAPE0-3 with `mtspr`. Circumstances include Matrices with dimensions
+larger than 32, and in-place Transpose.  Potentially a future v3.1 Prefixed
+instruction, `psvshape`, may extend the capability here.
+
 # REMAP Matrix pseudocode
 
 The algorithm below shows how REMAP works more clearly, and may be
@@ -203,64 +261,6 @@ pipeline overlaps.  Out-of-order / Superscalar micro-architectures with
 register-renaming will have an easier time dealing with this than
 DSP-style SIMD micro-architectures.
 
-# svshape instruction
-
-`svshape` is a convenience instruction that reduces instruction
-count for common usage patterns, particularly Matrix, DCT and FFT. It sets up
-(overwrites) all required SVSHAPE SPRs and also modifies SVSTATE
-including VL and MAXVL. Using `svshape` therefore does not also
-require `setvl`.
-
-Form: SVM-Form SV "Matrix" Form (see [[isatables/fields.text]])
-
-    svshape SVxd,SVyd,SVzd,SVRM,vf
-
-| 0.5|6.10  |11.15  |16..20 | 21..25 | 25 | 26..30 |31|  name    |
-| -- | --   | ---   | ----- | ------ | -- | ------ |--| -------- |
-|OPCD| SVxd | SVyd  | SVzd  | SVRM   | vf | XO     |/ | svstate  |
-
-Fields:
-
-* **SVxd** - SV REMAP "xdim" (SVGPR>>1 for Indexed REMAP)
-* **SVyd** - SV REMAP "ydim"
-* **SVzd** - SV REMAP "zdim"
-* **SVRM** - SV REMAP Mode (0b00000 for Matrix, 0b00001 for FFT etc.)
-* **vf** - sets "Vertical-First" mode
-* **XO** - standard 5-bit XO field
-
-| SVRM   | Remap Mode description |
-| --     | --              |
-| 0b0000 | Matrix 1/2/3D    |
-| 0b0001 | FFT Butterfly   |
-| 0b0010 | DCT Inner butterfly, pre-calculated coefficients |
-| 0b0011 | DCT Outer butterfly  |
-| 0b0100 | DCT Inner butterfly, on-the-fly (Vertical-First Mode) |
-| 0b0101 | DCT COS table index generation |
-| 0b0110 | DCT half-swap   |
-| 0b0111 | reserved  |
-| 0b1000 | Indexed (XY straight) |
-| 0b1001 | Indexed (YX swapped)  |
-| 0b1010 | iDCT Inner butterfly, pre-calculated coefficients |
-| 0b1011 | iDCT Outer butterfly  |
-| 0b1100 | iDCT Inner butterfly, on-the-fly (Vertical-First Mode) |
-| 0b1101 | iDCT COS table index generation |
-| 0b1110 | iDCT half-swap   |
-| 0b1111 | FFT half-swap   |
-
-Examples showing how all of these Modes operate exists in the online
-[SVP64 unit tests](https://git.libre-soc.org/?p=openpower-isa.git;a=tree;f=src/openpower/decoder/isa;hb=HEAD)
-
-In Indexed Mode, there are only 5 bits available to specify the GPR
-to use, out of 128 GPRs (7 bit numbering).  Therefore, only the top
-5 bits are given in the `SVxd` field: the bottom two implicit bits
-will be zero (`SVxd || 0b00`).
-
-`svshape` has *limited applicability* due to being a 32-bit instruction.
-The full capability of SVSHAPE SPRs may be accessed by directly writing
-to SVSHAPE0-3 with `mtspr`. Circumstances include Matrices with dimensions
-larger than 32, and in-place Transpose.  Potentially a future v3.1 Prefixed
-instruction, `psvshape`, may extend the capability here.
-
 # 4x4 Matrix to vec4 Multiply Example
 
 The following settings will allow a 4x4 matrix (starting at f8), expressed