config: Unify caches used in regressions and adjust L2 MSHRs

This patch unified the L1 and L2 caches used throughout the
regressions instead of declaring different, but very similar,
configurations in the different scripts.

The patch also changes the default L2 configuration to match what it
used to be for the fs and se scripts (until the last patch that
updated the regressions to also make use of the cache config). The
MSHRs and targets per MSHR are now set to a more realistic default of
20 and 12, respectively.

As a result of both the aforementioned changes, many of the regression
stats are changed. A follow-on patch will bump the stats.

diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index e6cbb1a75b3cdced06171dfd5bbc8b55697f1e45..6f1aff4430d273d68e4dc5340dbc514b97f84756 100644 (file)
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -60,8 +60,8 @@ class L2Cache(BaseCache):
     block_size = 64
     hit_latency = 20
     response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
+    mshrs = 20
+    tgts_per_mshr = 12
     write_buffers = 8
 
 class IOCache(BaseCache):

diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index edec312d0effc9aa30d1f265fb418b9c3cd02425..baeab677ac50860a773c3e56d71f69af22030f24 100644 (file)
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -29,23 +29,12 @@
 import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
-
-class MyCache(BaseCache):
-    assoc = 2
-    block_size = 64
-    hit_latency = 2
-    response_latency = 2
-    mshrs = 10
-    tgts_per_mshr = 5
-
-class MyL1Cache(MyCache):
-    is_top_level = True
+from Caches import *
 
 cpu = InOrderCPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
-                              MyL1Cache(size = '256kB'),
-                              MyCache(size = '2MB', hit_latency = 20,
-                                      response_latency = 20))
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
+                              L1Cache(size = '256kB'),
+                              L2Cache(size = '2MB'))
 
 cpu.clock = '2GHz'
 

diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 4db2d4f2a3d140d73a9ac11ab3e52d02b01fc13f..55c086d69ebc87498c40bb05bfec7420f8dd12d7 100644 (file)
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -28,30 +28,8 @@
 
 import m5
 from m5.objects import *
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 12
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
+m5.util.addToPath('../configs/common')
+from Caches import *
 
 #MAX CORES IS 8 with the fals sharing method
 nb_cores = 8
@@ -65,7 +43,7 @@ system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
 
 # l2cache & bus
 system.toL2Bus = CoherentBus(clock="2GHz", width=16)
-system.l2c = L2(clock = '2GHz', size='64kB', assoc=8)
+system.l2c = L2Cache(clock = '2GHz', size='64kB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 
 # connect l2c to membus
@@ -73,7 +51,7 @@ system.l2c.mem_side = system.membus.slave
 
 # add L1 caches
 for cpu in cpus:
-    cpu.l1c = L1(size = '32kB', assoc = 4)
+    cpu.l1c = L1Cache(size = '32kB', assoc = 4)
     cpu.l1c.cpu_side = cpu.test
     cpu.l1c.mem_side = system.toL2Bus.slave
     system.funcbus.slave = cpu.functional

diff --git a/tests/configs/o3-timing-checker.py b/tests/configs/o3-timing-checker.py
index 4ff3f01871246ecff8ee0f0135b1fbafce45b171..a4dddb08fa95a901391a0026e70e7186ab214552 100644 (file)
--- a/tests/configs/o3-timing-checker.py
+++ b/tests/configs/o3-timing-checker.py
@@ -38,25 +38,14 @@
 import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
-
-class MyCache(BaseCache):
-    assoc = 2
-    block_size = 64
-    hit_latency = 2
-    response_latency = 2
-    mshrs = 10
-    tgts_per_mshr = 5
-
-class MyL1Cache(MyCache):
-    is_top_level = True
-    tgts_per_mshr = 20
+from Caches import *
 
 cpu = DerivO3CPU(cpu_id=0)
 cpu.createInterruptController()
 cpu.addCheckerCpu()
-cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
-                              MyL1Cache(size = '256kB'),
-                              MyCache(size = '2MB'))
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
+                              L1Cache(size = '256kB'),
+                              L2Cache(size = '2MB'))
 # @todo Note that the L2 latency here is unmodified and 2 cycles,
 # should set hit latency and response latency to 20 cycles as for
 # other scripts

diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index b9bc40bc24c80df278b8bf6d9c02e1fdfe1e31af..30c2f413eca988aaad5b41b531fd1fc212f38f30 100644 (file)
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -29,23 +29,12 @@
 import m5
 from m5.objects import *
 m5.util.addToPath('../configs/common')
-
-class MyCache(BaseCache):
-    assoc = 2
-    block_size = 64
-    hit_latency = 2
-    response_latency = 2
-    mshrs = 10
-    tgts_per_mshr = 5
-
-class MyL1Cache(MyCache):
-    is_top_level = True
-    tgts_per_mshr = 20
+from Caches import *
 
 cpu = DerivO3CPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
-                              MyL1Cache(size = '256kB'),
-                              MyCache(size = '2MB'))
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
+                              L1Cache(size = '256kB'),
+                              L2Cache(size = '2MB'))
 # @todo Note that the L2 latency here is unmodified and 2 cycles,
 # should set hit latency and response latency to 20 cycles as for
 # other scripts

diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index 6dde4ed686f507d73aead05f745d03fdd5f65288..231c4ebe90af73eb414178d0be6a6846d4009099 100644 (file)
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -28,30 +28,8 @@
 
 import m5
 from m5.objects import *
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
+m5.util.addToPath('../configs/common')
+from Caches import *
 
 nb_cores = 4
 cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
@@ -63,7 +41,7 @@ system = System(cpu = cpus,
 
 # l2cache & bus
 system.toL2Bus = CoherentBus(clock = '2GHz')
-system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
+system.l2c = L2Caches(clock = '2GHz', size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 
 # connect l2c to membus
@@ -71,8 +49,8 @@ system.l2c.mem_side = system.membus.slave
 
 # add L1 caches
 for cpu in cpus:
-    cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
-                                L1(size = '32kB', assoc = 4))
+    cpu.addPrivateSplitL1Caches(L1Caches(size = '32kB', assoc = 1),
+                                L1Caches(size = '32kB', assoc = 4))
     # create the interrupt controller
     cpu.createInterruptController()
     # connect cpu level-1 caches to shared level-2 cache

diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index 3e5e92d8c4029491813e532b60499cbce7168f83..aad15a2ac0ffbf8bea226494a9678953192af5f0 100644 (file)
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -28,30 +28,8 @@
 
 import m5
 from m5.objects import *
-
-# --------------------
-# Base L1 Cache
-# ====================
-
-class L1(BaseCache):
-    hit_latency = 2
-    response_latency = 2
-    block_size = 64
-    mshrs = 4
-    tgts_per_mshr = 8
-    is_top_level = True
-
-# ----------------------
-# Base L2 Cache
-# ----------------------
-
-class L2(BaseCache):
-    block_size = 64
-    hit_latency = 20
-    response_latency = 20
-    mshrs = 92
-    tgts_per_mshr = 16
-    write_buffers = 8
+m5.util.addToPath('../configs/common')
+from Caches import *
 
 nb_cores = 4
 cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
@@ -61,7 +39,7 @@ system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
 
 # l2cache & bus
 system.toL2Bus = CoherentBus(clock = '2GHz')
-system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
+system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
 system.l2c.cpu_side = system.toL2Bus.master
 
 # connect l2c to membus
@@ -69,8 +47,8 @@ system.l2c.mem_side = system.membus.slave
 
 # add L1 caches
 for cpu in cpus:
-    cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
-                                L1(size = '32kB', assoc = 4))
+    cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
+                                L1Cache(size = '32kB', assoc = 4))
     # create the interrupt controller
     cpu.createInterruptController()
     # connect cpu level-1 caches to shared level-2 cache

diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index beeadced9d928be0304ff256ad88aae752d9fcbb..5a851ba2584e8d5d2aeb8244fb00019b428b3be4 100644 (file)
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -28,23 +28,13 @@
 
 import m5
 from m5.objects import *
-
-class MyCache(BaseCache):
-    assoc = 2
-    block_size = 64
-    hit_latency = 2
-    response_latency = 2
-    mshrs = 10
-    tgts_per_mshr = 5
-
-class MyL1Cache(MyCache):
-    is_top_level = True
+m5.util.addToPath('../configs/common')
+from Caches import *
 
 cpu = TimingSimpleCPU(cpu_id=0)
-cpu.addTwoLevelCacheHierarchy(MyL1Cache(size = '128kB'),
-                              MyL1Cache(size = '256kB'),
-                              MyCache(size = '2MB', hit_latency= 20,
-                                      response_latency = 20))
+cpu.addTwoLevelCacheHierarchy(L1Cache(size = '128kB'),
+                              L1Cache(size = '256kB'),
+                              L2Cache(size = '2MB'))
 system = System(cpu = cpu,
                 physmem = SimpleMemory(),
                 membus = CoherentBus())