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diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index da962bb9542e84e0ab2dcc32eaf1c1e7e469e927..7b937d750c2ace088db2b7bb4410b07852b2ad01 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -983,6 +983,20 @@ binaries, the size of each PE's TLB-aware
 L1 Cache needed would be miniscule compared
 to the average high-end CPU.
 
+**Comparison of PE-CPU to GPU-CPU interaction**
+
+The informed reader will have noted the remarkable similarity between how
+a CPU communicates with a GPU to schedule tasks, and the proposed
+architecture.  CPUs schedule tasks as follows:
+
+* User-space program encounters an OpenGL function, in the
+  CPU's ISA.
+* Proprietary GPU Driver, still in the CPU's ISA, prepares a
+  Shader Binary written in the GPU's ISA.
+* GPU Driver wishes to transfer both the data and the Shader Binary
+  to the GPU. Both may only do so via Shared Memory, usually
+  DMA over PCIe.
+
 **Roadmap summary of Advanced SVP64**
 
 The future direction for SVP64, then, is: