i386.md (*vec_extract2vdi_1): Merge with *vec_extractv2di_1_rex64.

	* config/i386/i386.md (*vec_extract2vdi_1): Merge with
	*vec_extractv2di_1_rex64.  Use x64 isa attribute.

From-SVN: r197208

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6fc2f47efb82dc30d952da83c37898c2eaf18ef7..73b5c9f5c234744ad87f5bbabe3f97e7f01ae396 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2013-03-28  Uros Bizjak  <ubizjak@gmail.com>
+
+       * config/i386/i386.md (*vec_extract2vdi_1): Merge with
+       *vec_extractv2di_1_rex64.  Use x64 isa attribute.
+
 2013-03-28   Naveen H.S  <Naveen.Hurugalawadi@caviumnetworks.com>
 
        * config/aarch64/aarch64.md (*and<mode>3_compare0): New pattern.

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index e2bb68ba18f9c581ff5ca192bfcbbb82dd95cb21..28d9fc0de9a30098e493e03de9ccd0ef2a8cdd8d 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -7426,31 +7426,12 @@
   [(set (match_dup 0) (match_dup 1))]
   "operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));")
 
-(define_insn "*vec_extractv2di_1_rex64"
-  [(set (match_operand:DI 0 "nonimmediate_operand"     "=m,x,x,x,r")
-       (vec_select:DI
-         (match_operand:V2DI 1 "nonimmediate_operand" " x,0,x,o,o")
-         (parallel [(const_int 1)])))]
-  "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
-  "@
-   %vmovhps\t{%1, %0|%0, %1}
-   psrldq\t{$8, %0|%0, 8}
-   vpsrldq\t{$8, %1, %0|%0, %1, 8}
-   %vmovq\t{%H1, %0|%0, %H1}
-   mov{q}\t{%H1, %0|%0, %H1}"
-  [(set_attr "isa" "*,noavx,avx,*,*")
-   (set_attr "type" "ssemov,sseishft1,sseishft1,ssemov,imov")
-   (set_attr "length_immediate" "*,1,1,*,*")
-   (set_attr "memory" "*,none,none,*,*")
-   (set_attr "prefix" "maybe_vex,orig,vex,maybe_vex,orig")
-   (set_attr "mode" "V2SF,TI,TI,TI,DI")])
-
 (define_insn "*vec_extractv2di_1"
-  [(set (match_operand:DI 0 "nonimmediate_operand"     "=m,x,x,x,x,x")
+  [(set (match_operand:DI 0 "nonimmediate_operand"     "=m,x,x,x,x,x,r")
        (vec_select:DI
-         (match_operand:V2DI 1 "nonimmediate_operand" " x,0,x,o,x,o")
+         (match_operand:V2DI 1 "nonimmediate_operand" " x,0,x,o,x,o,o")
          (parallel [(const_int 1)])))]
-  "!TARGET_64BIT && TARGET_SSE
+  "(TARGET_64BIT || TARGET_SSE)
    && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
   "@
    %vmovhps\t{%1, %0|%0, %1}
@@ -7458,13 +7439,14 @@
    vpsrldq\t{$8, %1, %0|%0, %1, 8}
    %vmovq\t{%H1, %0|%0, %H1}
    movhlps\t{%1, %0|%0, %1}
-   movlps\t{%H1, %0|%0, %H1}"
-  [(set_attr "isa" "*,sse2_noavx,avx,sse2,noavx,noavx")
-   (set_attr "type" "ssemov,sseishft1,sseishft1,ssemov,ssemov,ssemov")
-   (set_attr "length_immediate" "*,1,1,*,*,*")
-   (set_attr "memory" "*,none,none,*,*,*")
-   (set_attr "prefix" "maybe_vex,orig,vex,maybe_vex,orig,orig")
-   (set_attr "mode" "V2SF,TI,TI,TI,V4SF,V2SF")])
+   movlps\t{%H1, %0|%0, %H1}
+   mov{q}\t{%H1, %0|%0, %H1}"
+  [(set_attr "isa" "*,sse2_noavx,avx,sse2,noavx,noavx,x64")
+   (set_attr "type" "ssemov,sseishft1,sseishft1,ssemov,ssemov,ssemov,imov")
+   (set_attr "length_immediate" "*,1,1,*,*,*,*")
+   (set_attr "memory" "*,none,none,*,*,*,*")
+   (set_attr "prefix" "maybe_vex,orig,vex,maybe_vex,orig,orig,orig")
+   (set_attr "mode" "V2SF,TI,TI,TI,V4SF,V2SF,DI")])
 
 (define_insn "*vec_dupv4si"
   [(set (match_operand:V4SI 0 "register_operand"     "=x,x,x")