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+# Tuesday 5th December 17:00 UTC
+
+* Previous week's notes: [[meetings/sync_up/sync_up_2023-12-05]]
+* Next day's notes: [[meetings/sync_up/sync_up_2023-12-06]]
+* Next week's notes: [[meetings/sync_up/sync_up_2023-12-12]]
+
+**TODO EDIT, this is a clone/copy of last weeks notes (easier, saves time)
+
+# Main Agenda
+
+* reminder of **only 12 weeks** until march 1st deadline
+  for completion of cavatools and cryptoprimitives.
+
+Meeting notes:
+
+- Deprecated SimpleV prefix format from 2019: <https://libre-soc.org/simple_v_extension/sv_prefix_proposal/>
+- RISC-V example extension: <https://github.com/riscv-software-src/riscv-isa-sim/blob/master/customext/cflush.cc>
+- The first step is to make modifications to `sv_analysis.py` to classify the RISC-V instructions.
+  <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/sv_analysis.py;hb=HEAD>
+- Standard RISC-V opcode format: <https://github.com/riscv/riscv-opcodes>
+
+- [bug #980](https://bugs.libre-soc.org/show_bug.cgi?id=980)
+  - A lot of work, need to focus on the basics
+  - Issues with current Python pseudo-code compiler:
+    - pseudocode is full of python-isms such as some variables are
+    python ints and some are selectableint and some are strings etc.
+    - plus, the parser currently has wrong operator precedence
+    [bug #1082](https://bugs.libre-soc.org/show_bug.cgi?id=1082).
+  - Suggested minimal goal for bug #980 is:
+    - Use AST (operands, flow, etc. as we already do for generated
+    Python func's) and a custom visitor function to convert to C code. 
+    - Generate C functions which can be compiled without errors.
+    - Generated functions can be run from a main function to confirm results.
+    - Jacob suggested using `maddedu` as a benchmark, since it has
+    non-trivial pseudo-code.
+    - 
+
+
+# Dmitry
+
+* Update [bug #1126](https://bugs.libre-soc.org/show_bug.cgi?id=1126)
+to include git commit descriptions.
+* Check whether RISC-V have their own way of describing the instructions
+  (likely they do).
+* Familiarise yourself with
+[svanalysis.py](https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/sv_analysis.py;h=21778ad02d78c4f7ef5b6df93e096f4abbe365ad;hb=HEAD),
+as we will need a similar tool for RISC-V.
+* Check what RISC-V support in binutils looks like. *Needed for confirming
+the details of the RISC-V binutils grant*.
+
+# Sadoon
+
+- Work together with Shriya (with Luke's asssitance) on Poly1305/ED25519.
+- Submitted talk proposals for FOSDEM 2024 
+
+# Jacob
+
+- [bug #1169](https://bugs.libre-soc.org/show_bug.cgi?id=1169)
+Completed the necessary bits of mmap for ELF task.
+
+# David
+
+-
+
+# Andrey
+
+- Check with Dmitry on git commit descriptions (bug #1126).
+Once comment made, add to [[HDL_workflow]] documentation.
+
+# Luke
+
+* [bug #672](https://bugs.libre-soc.org/show_bug.cgi?id=672)
+  long story, pospopcount needs bmatflip (aka vgbbd in VSX)
+  but also needed sv.bc fixing
+  [bug #1215](https://bugs.libre-soc.org/show_bug.cgi?id=1215)
+  which is related/similar to the DDFFirst issue on scalar source/dest
+  [bug #1183](https://bugs.libre-soc.org/show_bug.cgi?id=1183)
+  which jacob also noted for sv.cmpi/ff needed on bigmul.
+* Guide Dmitry on svanalysis.py.
+* Guide Shriya in Poly1305
+  [bug #1157](https://bugs.libre-soc.org/show_bug.cgi?id=1157)
+  and ED25519 [bug #1151](https://bugs.libre-soc.org/show_bug.cgi?id=1151)
+  to assist Sadoon.
+  
+# Shriya
+
+- Work together with Sadoon on Poly1305 and ED25519.
+
+# Tobias
+
+* created fosdem talk bug, [bug #1213](https://bugs.libre-soc.org/show_bug.cgi?id=1213)
+
+[[!tag meeting2023]]
+[[!tag meeting_sync_up]]
+