mips3 or greater, then mark the object file 32BITMODE. */
static int mips_32bitmode = 0;
+/* Some ISA's have delay slots for instructions which read or write
+ from a coprocessor (eg. mips1-mips3); some don't (eg mips4).
+ Return true if instructions marked INSN_LOAD_COPROC_DELAY,
+ INSN_COPROC_MOVE_DELAY, or INSN_WRITE_COND_CODE actually have a
+ delay slot in this ISA. The uses of this macro assume that any
+ ISA that has delay slots for one of these, has them for all. They
+ also assume that ISAs which don't have delays for these insns, don't
+ have delays for the INSN_LOAD_MEMORY_DELAY instructions either. */
+#define ISA_HAS_COPROC_DELAYS(ISA) ( \
+ (ISA) == 1 \
+ || (ISA) == 2 \
+ || (ISA) == 3 \
+ )
+
+/* Return true if ISA supports 64 bit gp register instructions. */
+#define ISA_HAS_64BIT_REGS(ISA) ( \
+ (ISA) == 3 \
+ || (ISA) == 4 \
+ )
+
/* Whether the processor uses hardware interlocks to protect
reads from the HI and LO registers, and thus does not
require nops to be inserted.
/* Whether the processor uses hardware interlocks to protect reads
from the GPRs, and thus does not require nops to be inserted. */
#define gpr_interlocks \
- (mips_opts.isa >= 2 \
+ (mips_opts.isa != 1 \
|| mips_cpu == 3900)
/* As with other "interlocks" this is used by hardware that has FP
if (strcmp (cpu, "mips") == 0)
{
- if (mips_opts.isa < 0)
- mips_cpu = 3000;
+ if (mips_opts.isa < 0)
+ mips_cpu = 3000;
- else if (mips_opts.isa == 2)
+ else if (mips_opts.isa == 2)
mips_cpu = 6000;
else if (mips_opts.isa == 3)
a = NULL;
}
- if (mips_opts.isa < 2 && mips_trap)
+ if (mips_opts.isa == 1 && mips_trap)
as_bad (_("trap exception not supported at ISA 1"));
/* Set the EABI kind based on the ISA before the user gets
to change the ISA with directives. This isn't really
the best, but then neither is basing the abi on the isa. */
- if (mips_opts.isa > 2
+ if (ISA_HAS_64BIT_REGS (mips_opts.isa)
&& mips_abi_string
&& 0 == strcmp (mips_abi_string,"eabi"))
mips_eabi64 = 1;
if (mips_cpu != 0 && mips_cpu != -1)
{
ok = bfd_set_arch_mach (stdoutput, bfd_arch_mips, mips_cpu);
-
+
/* If they asked for mips1 or mips2 and a cpu that is
mips3 or greater, then mark the object file 32BITMODE. */
if (mips_isa_from_cpu != -1
- && mips_opts.isa <= 2 && mips_isa_from_cpu > 2)
+ && ! ISA_HAS_64BIT_REGS (mips_opts.isa)
+ && ISA_HAS_64BIT_REGS (mips_isa_from_cpu))
mips_32bitmode = 1;
}
else
prev_pinfo = prev_insn.insn_mo->pinfo;
if (! mips_opts.noreorder
- && mips_opts.isa < 4
+ && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
|| (! gpr_interlocks
&& (prev_pinfo & INSN_LOAD_MEMORY_DELAY))))
/* The previous insn might require a delay slot, depending upon
the contents of the current insn. */
if (! mips_opts.mips16
- && mips_opts.isa < 4
+ && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& (((prev_pinfo & INSN_LOAD_COPROC_DELAY)
&& ! cop_interlocks)
|| (! gpr_interlocks
++nops;
}
else if (! mips_opts.mips16
- && mips_opts.isa < 4
+ && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
&& ! cop_interlocks)
- || (mips_opts.isa < 2
+ || (mips_opts.isa == 1
&& (prev_pinfo & INSN_COPROC_MEMORY_DELAY))))
{
/* A generic coprocessor delay. The previous instruction
}
}
else if (! mips_opts.mips16
- && mips_opts.isa < 4
+ && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& (prev_pinfo & INSN_WRITE_COND_CODE)
&& ! cop_interlocks)
{
instruction, we must check for these cases compared to the
instruction previous to the previous instruction. */
if ((! mips_opts.mips16
- && mips_opts.isa < 4
+ && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
&& (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
&& (pinfo & INSN_READ_COND_CODE)
we can not swap, and I don't feel like handling that
case. */
|| (! mips_opts.mips16
- && mips_opts.isa < 4
+ && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& (pinfo & INSN_READ_COND_CODE))
/* We can not swap with an instruction that requires a
delay slot, becase the target of the branch might
interfere with that instruction. */
|| (! mips_opts.mips16
- && mips_opts.isa < 4
+ && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& (prev_pinfo
/* Itbl support may require additional care here. */
& (INSN_LOAD_COPROC_DELAY
&& ! gpr_interlocks
&& (prev_pinfo & INSN_LOAD_MEMORY_DELAY))
|| (! mips_opts.mips16
- && mips_opts.isa < 2
+ && mips_opts.isa == 1
/* Itbl support may require additional care here. */
&& (prev_pinfo & INSN_COPROC_MEMORY_DELAY))
/* We can not swap with a branch instruction. */
delay, and sets a register that the branch reads, we
can not swap. */
|| (! mips_opts.mips16
- && mips_opts.isa < 4
+ && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
/* Itbl support may require additional care here. */
&& ((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
|| (! gpr_interlocks
nops = 0;
if ((! mips_opts.mips16
- && mips_opts.isa < 4
+ && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& (! cop_interlocks
&& (prev_insn.insn_mo->pinfo
& (INSN_LOAD_COPROC_DELAY
&& (prev_insn.insn_mo->pinfo
& INSN_LOAD_MEMORY_DELAY))
|| (! mips_opts.mips16
- && mips_opts.isa < 2
+ && mips_opts.isa == 1
&& (prev_insn.insn_mo->pinfo
& INSN_COPROC_MEMORY_DELAY)))
{
/* Itbl support may require additional care here. */
++nops;
if ((! mips_opts.mips16
- && mips_opts.isa < 4
+ && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& (! cop_interlocks
&& prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
|| (! hilo_interlocks
nops = 0;
}
else if ((! mips_opts.mips16
- && mips_opts.isa < 4
+ && ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& (! cop_interlocks
&& prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE))
|| (! hilo_interlocks
/* Search until we get a match for NAME. */
while (1)
{
+ insn_isa = 0;
+
if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA1)
insn_isa = 1;
else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA2)
insn_isa = 3;
else if ((insn.insn_mo->membership & INSN_ISA) == INSN_ISA4)
insn_isa = 4;
- else
- insn_isa = 15;
if (strcmp (fmt, insn.insn_mo->args) == 0
&& insn.insn_mo->pinfo != INSN_MACRO
- && (insn_isa <= mips_opts.isa
+ && ((insn_isa != 0
+ && insn_isa <= mips_opts.isa)
|| (mips_cpu == 4650
&& (insn.insn_mo->membership & INSN_4650) != 0)
|| (mips_cpu == 4010
|| ! ep->X_unsigned
|| sizeof (ep->X_add_number) > 4
|| (ep->X_add_number & 0x80000000) == 0))
- || ((mips_opts.isa < 3 || ! dbl)
+ || ((! ISA_HAS_64BIT_REGS (mips_opts.isa) || ! dbl)
&& (ep->X_add_number &~ (offsetT) 0xffffffff) == 0)
- || (mips_opts.isa < 3
+ || (! ISA_HAS_64BIT_REGS (mips_opts.isa)
&& ! dbl
&& ((ep->X_add_number &~ (offsetT) 0xffffffff)
== ~ (offsetT) 0xffffffff)))
/* The value is larger than 32 bits. */
- if (mips_opts.isa < 3)
+ if (! ISA_HAS_64BIT_REGS (mips_opts.isa))
{
as_bad (_("Number larger than 32 bits"));
macro_build ((char *) NULL, counter, ep, "addiu", "t,r,j", reg, 0,
frag_grow (20);
macro_build ((char *) NULL, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL);
p = frag_var (rs_machine_dependent, 8, 0,
p += 4;
macro_build (p, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
}
frag_grow (20);
macro_build ((char *) NULL, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP);
macro_build ((char *) NULL, counter, (expressionS *) NULL, "nop", "");
ep->X_add_symbol, (offsetT) 0, (char *) NULL);
macro_build (p, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
if (ex.X_add_number != 0)
ex.X_op = O_constant;
macro_build ((char *) NULL, counter, &ex,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
}
(int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, counter, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", reg, reg, GP);
macro_build ((char *) NULL, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT_LO16, reg);
p = frag_var (rs_machine_dependent, 12 + off, 0,
}
macro_build (p, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", reg, (int) BFD_RELOC_MIPS_GOT16, GP);
p += 4;
p += 4;
macro_build (p, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
if (ex.X_add_number != 0)
ex.X_op = O_constant;
macro_build ((char *) NULL, counter, &ex,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", reg, reg, (int) BFD_RELOC_LO16);
}
*/
macro_build ((char *) NULL, counter, ep,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", reg, GP, (int) BFD_RELOC_MIPS_GPREL);
}
case M_BGT_I:
/* check for > max integer */
maxnum = 0x7fffffff;
- if (mips_opts.isa >= 3 && sizeof (maxnum) > 4)
+ if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4)
{
maxnum <<= 16;
maxnum |= 0xffff;
}
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number >= maxnum
- && (mips_opts.isa < 3 || sizeof (maxnum) > 4))
+ && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4))
{
do_false:
/* result is always false */
return;
}
maxnum = 0x7fffffff;
- if (mips_opts.isa >= 3 && sizeof (maxnum) > 4)
+ if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4)
{
maxnum <<= 16;
maxnum |= 0xffff;
maxnum = - maxnum - 1;
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number <= maxnum
- && (mips_opts.isa < 3 || sizeof (maxnum) > 4))
+ && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4))
{
do_true:
/* result is always true */
likely = 1;
case M_BGTU_I:
if (sreg == 0
- || (mips_opts.isa < 3
+ || (! ISA_HAS_64BIT_REGS (mips_opts.isa)
&& imm_expr.X_op == O_constant
&& imm_expr.X_add_number == 0xffffffff))
goto do_false;
likely = 1;
case M_BLE_I:
maxnum = 0x7fffffff;
- if (mips_opts.isa >= 3 && sizeof (maxnum) > 4)
+ if (ISA_HAS_64BIT_REGS (mips_opts.isa) && sizeof (maxnum) > 4)
{
maxnum <<= 16;
maxnum |= 0xffff;
}
if (imm_expr.X_op == O_constant
&& imm_expr.X_add_number >= maxnum
- && (mips_opts.isa < 3 || sizeof (maxnum) > 4))
+ && (! ISA_HAS_64BIT_REGS (mips_opts.isa) || sizeof (maxnum) > 4))
goto do_true;
if (imm_expr.X_op != O_constant)
as_bad (_("Unsupported large constant"));
likely = 1;
case M_BLEU_I:
if (sreg == 0
- || (mips_opts.isa < 3
+ || (! ISA_HAS_64BIT_REGS (mips_opts.isa)
&& imm_expr.X_op == O_constant
&& imm_expr.X_add_number == 0xffffffff))
goto do_true;
treg, (int) BFD_RELOC_PCREL_HI16_S);
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", treg, treg, (int) BFD_RELOC_PCREL_LO16);
return;
frag_grow (20);
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL);
p = frag_var (rs_machine_dependent, 8, 0,
p += 4;
macro_build (p, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
}
}
macro_build (p, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
/* FIXME: If breg == 0, and the next instruction uses
"nop", "");
macro_build ((char *) NULL, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
(void) frag_var (rs_machine_dependent, 0, 0,
"nop", "");
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", treg, AT, breg);
breg = 0;
macro_build ((char *) NULL, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", AT, AT, (int) BFD_RELOC_LO16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, AT);
(void) frag_var (rs_machine_dependent, 0, 0,
tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, GP);
macro_build ((char *) NULL, &icnt, &offset_expr,
"nop", "");
macro_build ((char *) NULL, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
"nop", "");
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", treg, AT, breg);
dreg = treg;
macro_build ((char *) NULL, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", AT, AT, (int) BFD_RELOC_LO16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", dreg, dreg, AT);
p += 4;
macro_build (p, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
/* FIXME: If add_number is 0, and there was no base
p += 4;
macro_build (p, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", treg, AT, breg);
p += 4;
p += 4;
macro_build (p, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", AT, AT, (int) BFD_RELOC_LO16);
p += 4;
macro_build (p, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, AT);
p += 4;
*/
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", tempreg, GP, (int) BFD_RELOC_MIPS_GPREL);
}
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", treg, tempreg, breg);
expr1.X_add_number = mips_cprestore_offset;
macro_build ((char *) NULL, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", GP, (int) BFD_RELOC_LO16, mips_frame_reg);
}
{
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_CALL16, GP);
PIC_CALL_REG, (int) BFD_RELOC_MIPS_CALL_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", PIC_CALL_REG, PIC_CALL_REG, GP);
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_CALL_LO16, PIC_CALL_REG);
}
macro_build (p, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", PIC_CALL_REG,
(int) BFD_RELOC_MIPS_GOT16, GP);
}
macro_build (p, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", PIC_CALL_REG, PIC_CALL_REG,
(int) BFD_RELOC_LO16);
expr1.X_add_number = mips_cprestore_offset;
macro_build ((char *) NULL, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", GP, (int) BFD_RELOC_LO16,
mips_frame_reg);
frag_grow (28);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", tempreg, breg, GP);
macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
p += 4;
macro_build (p, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, breg);
if (p != NULL)
frag_grow (20);
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
(char *) NULL);
macro_build (p, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, breg);
macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
tempreg, (int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, GP);
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT_LO16,
tempreg);
}
macro_build (p, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", tempreg, (int) BFD_RELOC_MIPS_GOT16, GP);
p += 4;
p += 4;
macro_build (p, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", tempreg, tempreg, (int) BFD_RELOC_LO16);
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", tempreg, tempreg, breg);
macro_build ((char *) NULL, &icnt, &expr1, s, fmt, treg,
{
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", tempreg, breg, GP);
macro_build ((char *) NULL, &icnt, &offset_expr, s, fmt,
or in offset_expr. */
if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
{
- if (mips_opts.isa >= 3)
+ if (ISA_HAS_64BIT_REGS (mips_opts.isa))
load_register (&icnt, treg, &imm_expr, 1);
else
{
{
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
}
a single instruction. */
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", AT, GP, (int) BFD_RELOC_MIPS_GPREL);
offset_expr.X_op = O_constant;
abort ();
/* Now we load the register(s). */
- if (mips_opts.isa >= 3)
+ if (ISA_HAS_64BIT_REGS (mips_opts.isa))
macro_build ((char *) NULL, &icnt, &offset_expr, "ld", "t,o(b)",
treg, (int) BFD_RELOC_LO16, AT);
else
or in offset_expr. */
if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
{
- load_register (&icnt, AT, &imm_expr, mips_opts.isa >= 3);
- if (mips_opts.isa >= 3)
+ load_register (&icnt, AT, &imm_expr, ISA_HAS_64BIT_REGS (mips_opts.isa));
+ if (ISA_HAS_64BIT_REGS (mips_opts.isa))
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
"dmtc1", "t,S", AT, treg);
else
s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
if (strcmp (s, ".lit8") == 0)
{
- if (mips_opts.isa >= 2)
+ if (mips_opts.isa != 1)
{
macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
"T,o(b)", treg, (int) BFD_RELOC_MIPS_LITERAL, GP);
if (mips_pic == SVR4_PIC)
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
else
macro_build_lui ((char *) NULL, &icnt, &offset_expr, AT);
}
- if (mips_opts.isa >= 2)
+ if (mips_opts.isa != 1)
{
macro_build ((char *) NULL, &icnt, &offset_expr, "ldc1",
"T,o(b)", treg, (int) BFD_RELOC_LO16, AT);
to adjust when loading from memory. */
r = BFD_RELOC_LO16;
dob:
- assert (mips_opts.isa < 2);
+ assert (mips_opts.isa == 1);
macro_build ((char *) NULL, &icnt, &offset_expr, "lwc1", "T,o(b)",
target_big_endian ? treg + 1 : treg,
(int) r, breg);
}
/* Itbl support may require additional care here. */
coproc = 1;
- if (mips_opts.isa >= 2)
+ if (mips_opts.isa != 1)
{
s = "ldc1";
goto ld;
return;
}
- if (mips_opts.isa >= 2)
+ if (mips_opts.isa != 1)
{
s = "sdc1";
goto st;
goto ldd_std;
case M_LD_AB:
- if (mips_opts.isa >= 3)
+ if (ISA_HAS_64BIT_REGS (mips_opts.isa))
{
s = "ld";
goto ld;
goto ldd_std;
case M_SD_AB:
- if (mips_opts.isa >= 3)
+ if (ISA_HAS_64BIT_REGS (mips_opts.isa))
{
s = "sd";
goto st;
frag_grow (36);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, breg, GP);
tempreg = AT;
{
macro_build (p, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, breg, AT);
if (p != NULL)
frag_grow (24 + off);
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, breg, AT);
/* Itbl support may require additional care here. */
AT, (int) BFD_RELOC_MIPS_GOT_HI16);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, AT, GP);
macro_build ((char *) NULL, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT_LO16, AT);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "nop", "");
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, breg, AT);
/* Itbl support may require additional care here. */
}
macro_build (p, &icnt, &offset_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "lw" : "ld"),
"t,o(b)", AT, (int) BFD_RELOC_MIPS_GOT16, GP);
p += 4;
{
macro_build (p, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, breg, AT);
p += 4;
{
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, breg, GP);
tempreg = AT;
case M_SD_OB:
s = "sw";
sd_ob:
- assert (bfd_arch_bits_per_address (stdoutput) == 32 || mips_opts.isa < 3);
+ assert (bfd_arch_bits_per_address (stdoutput) == 32
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa));
macro_build ((char *) NULL, &icnt, &offset_expr, s, "t,o(b)", treg,
(int) BFD_RELOC_LO16, breg);
offset_expr.X_add_number += 4;
as_bad (_("opcode not supported on this processor"));
return;
}
- assert (mips_opts.isa < 2);
+ assert (mips_opts.isa == 1);
/* Even on a big endian machine $fn comes before $fn+1. We have
to adjust when storing to memory. */
macro_build ((char *) NULL, &icnt, &offset_expr, "swc1", "T,o(b)",
imm_expr.X_add_number = -imm_expr.X_add_number;
macro_build ((char *) NULL, &icnt, &imm_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", dreg, sreg,
(int) BFD_RELOC_LO16);
ip->insn_mo->name);
macro_build ((char *) NULL, &icnt, &expr1,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", dreg, 0, (int) BFD_RELOC_LO16);
return;
imm_expr.X_add_number = -imm_expr.X_add_number;
macro_build ((char *) NULL, &icnt, &imm_expr,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addiu" : "daddiu"),
"t,r,j", dreg, sreg, (int) BFD_RELOC_LO16);
used_at = 0;
case M_TRUNCWD:
case M_TRUNCWS:
- assert (mips_opts.isa < 2);
+ assert (mips_opts.isa == 1);
sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, AT, breg);
if (! target_big_endian)
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, AT, breg);
if (target_big_endian)
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, AT, breg);
if (! target_big_endian)
if (breg != 0)
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", AT, AT, breg);
if (! target_big_endian)
assert (strcmp (insn->name, str) == 0);
+ insn_isa = 0;
if ((insn->membership & INSN_ISA) == INSN_ISA1)
insn_isa = 1;
else if ((insn->membership & INSN_ISA) == INSN_ISA2)
insn_isa = 3;
else if ((insn->membership & INSN_ISA) == INSN_ISA4)
insn_isa = 4;
- else
- insn_isa = 15;
- if (insn_isa <= mips_opts.isa)
+ if (insn_isa != 0
+ && insn_isa <= mips_opts.isa)
ok = true;
else if (insn->pinfo == INSN_MACRO)
ok = false;
++insn;
continue;
}
- if (insn_isa == 15
+
+ if (insn_isa == 0
|| insn_isa <= mips_opts.isa)
insn_error = _("opcode not supported on this processor");
else
as_bad (_("Invalid float register number (%d)"), regno);
if ((regno & 1) != 0
- && mips_opts.isa < 3
+ && ! ISA_HAS_64BIT_REGS (mips_opts.isa)
&& ! (strcmp (str, "mtc1") == 0
|| strcmp (str, "mfc1") == 0
|| strcmp (str, "lwc1") == 0
offset_expr to the low order 32 bits.
Otherwise, set imm_expr to the entire 64 bit
constant. */
- if (mips_opts.isa < 3)
+ if (! ISA_HAS_64BIT_REGS (mips_opts.isa))
{
imm_expr.X_op = O_constant;
offset_expr.X_op = O_constant;
&& imm_expr.X_op == O_constant)
|| (more
&& imm_expr.X_add_number < 0
- && mips_opts.isa >= 3
+ && ISA_HAS_64BIT_REGS (mips_opts.isa)
&& imm_expr.X_unsigned
&& sizeof (imm_expr.X_add_number) <= 4))
{
macro_build ((char *) NULL, &icnt, &ex,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "sw" : "sd"),
"t,o(b)", GP, (int) BFD_RELOC_LO16, SP);
reg = tc_get_register (0);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL,
((bfd_arch_bits_per_address (stdoutput) == 32
- || mips_opts.isa < 3)
+ || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
? "addu" : "daddu"),
"d,v,t", reg, reg, GP);
projects / binutils-gdb.git / commitdiff