radeonsi: support creating EQAA color textures

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 0f3546b02daecf7f406f58b6e509cc4f7e36403e..23977186611189b4cd4e287b4c238ec195243b81 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -247,7 +247,7 @@ void vi_dcc_clear_level(struct si_context *sctx,
                assert(rtex->buffer.b.b.last_level == 0);
                /* 4x and 8x MSAA needs a sophisticated compute shader for
                 * the clear. See AMDVLK. */
-               assert(rtex->buffer.b.b.nr_samples <= 2);
+               assert(rtex->num_color_samples <= 2);
                clear_size = rtex->surface.dcc_size;
        } else {
                unsigned num_layers = util_num_layers(&rtex->buffer.b.b, level);
@@ -258,7 +258,7 @@ void vi_dcc_clear_level(struct si_context *sctx,
                 * dcc_fast_clear_size bytes for each layer. A compute shader
                 * would be more efficient than separate per-layer clear operations.
                 */
-               assert(rtex->buffer.b.b.nr_samples <= 2 || num_layers == 1);
+               assert(rtex->num_color_samples <= 2 || num_layers == 1);
 
                dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset;
                clear_size = rtex->surface.u.legacy.level[level].dcc_fast_clear_size *

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index b5caf944759c52e36821b69a78a40b7a6119d94f..241385baed7a6ec5ec917f3986046e5c424dfebe 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -254,6 +254,7 @@ struct r600_texture {
        unsigned                        color_clear_value[2];
        unsigned                        last_msaa_resolve_target_micro_mode;
        unsigned                        num_level0_transfers;
+       unsigned                        num_color_samples;
 
        /* Depth buffer compression and fast clear. */
        uint64_t                        htile_offset;

diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index 1e328b90b62a2441470702e29a23a8edd8f9ba55..52b8b87732f18c269687cd3d70e19b5b925ec76e 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -220,6 +220,7 @@ static unsigned si_texture_get_offset(struct si_screen *sscreen,
 static int si_init_surface(struct si_screen *sscreen,
                           struct radeon_surf *surface,
                           const struct pipe_resource *ptex,
+                          unsigned num_color_samples,
                           enum radeon_surf_mode array_mode,
                           unsigned pitch_in_bytes_override,
                           unsigned offset,
@@ -274,13 +275,13 @@ static int si_init_surface(struct si_screen *sscreen,
 
        /* VI: DCC clear for 4x and 8x MSAA array textures unimplemented. */
        if (sscreen->info.chip_class == VI &&
-           ptex->nr_samples >= 4 &&
+           num_color_samples >= 4 &&
            ptex->array_size > 1)
                flags |= RADEON_SURF_DISABLE_DCC;
 
        /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
        if (sscreen->info.chip_class >= GFX9 &&
-           ptex->nr_samples >= 4)
+           num_color_samples >= 4)
                flags |= RADEON_SURF_DISABLE_DCC;
 
        if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
@@ -301,7 +302,7 @@ static int si_init_surface(struct si_screen *sscreen,
        if (!(ptex->flags & SI_RESOURCE_FLAG_FORCE_TILING))
                flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
 
-       r = sscreen->ws->surface_init(sscreen->ws, ptex, ptex->nr_samples,
+       r = sscreen->ws->surface_init(sscreen->ws, ptex, num_color_samples,
                                      flags, bpe, array_mode, surface);
        if (r) {
                return r;
@@ -1145,6 +1146,7 @@ void si_print_texture_info(struct si_screen *sscreen,
 static struct r600_texture *
 si_texture_create_object(struct pipe_screen *screen,
                         const struct pipe_resource *base,
+                        unsigned num_color_samples,
                         struct pb_buffer *buf,
                         struct radeon_surf *surface)
 {
@@ -1168,6 +1170,7 @@ si_texture_create_object(struct pipe_screen *screen,
 
        rtex->surface = *surface;
        rtex->size = rtex->surface.surf_size;
+       rtex->num_color_samples = num_color_samples;
 
        rtex->tc_compatible_htile = rtex->surface.htile_size != 0 &&
                                    (rtex->surface.flags &
@@ -1384,6 +1387,12 @@ si_choose_tiling(struct si_screen *sscreen,
        return RADEON_SURF_MODE_2D;
 }
 
+static unsigned si_get_num_color_samples(const struct pipe_resource *templ,
+                                        bool imported)
+{
+       return CLAMP(templ->nr_samples, 1, 8);
+}
+
 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
                                        const struct pipe_resource *templ)
 {
@@ -1404,10 +1413,10 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen,
                !is_flushed_depth &&
                templ->nr_samples <= 1 && /* TC-compat HTILE is less efficient with MSAA */
                util_format_is_depth_or_stencil(templ->format);
-
+       unsigned num_color_samples = si_get_num_color_samples(templ, false);
        int r;
 
-       r = si_init_surface(sscreen, &surface, templ,
+       r = si_init_surface(sscreen, &surface, templ, num_color_samples,
                            si_choose_tiling(sscreen, templ, tc_compatible_htile),
                            0, 0, false, false, is_flushed_depth,
                            tc_compatible_htile);
@@ -1416,7 +1425,8 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen,
        }
 
        return (struct pipe_resource *)
-              si_texture_create_object(screen, templ, NULL, &surface);
+              si_texture_create_object(screen, templ, num_color_samples,
+                                       NULL, &surface);
 }
 
 static struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen,
@@ -1447,13 +1457,17 @@ static struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen,
        si_surface_import_metadata(sscreen, &surface, &metadata,
                                     &array_mode, &is_scanout);
 
-       r = si_init_surface(sscreen, &surface, templ, array_mode, stride,
-                             offset, true, is_scanout, false, false);
+       unsigned num_color_samples = si_get_num_color_samples(templ, true);
+
+       r = si_init_surface(sscreen, &surface, templ, num_color_samples,
+                           array_mode, stride, offset, true, is_scanout,
+                           false, false);
        if (r) {
                return NULL;
        }
 
-       rtex = si_texture_create_object(screen, templ, buf, &surface);
+       rtex = si_texture_create_object(screen, templ, num_color_samples,
+                                       buf, &surface);
        if (!rtex)
                return NULL;
 
@@ -2375,17 +2389,18 @@ si_texture_from_memobj(struct pipe_screen *screen,
                 */
                array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
                is_scanout = false;
-
        }
 
-       r = si_init_surface(sscreen, &surface, templ,
-                             array_mode, memobj->stride,
-                             offset, true, is_scanout,
-                             false, false);
+       unsigned num_color_samples = si_get_num_color_samples(templ, true);
+
+       r = si_init_surface(sscreen, &surface, templ, num_color_samples,
+                           array_mode, memobj->stride, offset, true,
+                           is_scanout, false, false);
        if (r)
                return NULL;
 
-       rtex = si_texture_create_object(screen, templ, memobj->buf, &surface);
+       rtex = si_texture_create_object(screen, templ, num_color_samples,
+                                       memobj->buf, &surface);
        if (!rtex)
                return NULL;