riscv: enable unaligned memory accesses

Sometimes an ld instruction will be split across a
cache boundary.  Previously RISC-V was set to not
allow this.  This patch fixes that.

Change-Id: I8bc8ea6d67f65a9b3662e14c4037f4224799d20f
Reviewed-on: https://gem5-review.googlesource.com/2341
Maintainer: Alec Roelke <ar4jc@virginia.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index f7a2c8762c99d5572219ddac895f95f0588bfe01..327d644983f50b884baf91ee7b629968f1377f7e 100644 (file)
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -65,8 +65,8 @@ const Addr PageBytes = ULL(1) << PageShift;
 
 const ExtMachInst NoopMachInst = 0x00000013;
 
-// Memory accesses can not be unaligned
-const bool HasUnalignedMemAcc = false;
+// Memory accesses can be unaligned (at least for double-word memory accesses)
+const bool HasUnalignedMemAcc = true;
 
 const bool CurThreadInfoImplemented = false;
 const int CurThreadInfoReg = -1;