Merge zizzer:/bk/newmem

into  zower.eecs.umich.edu:/eecshome/m5/newmem

src/arch/isa_parser.py:
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
src/cpu/o3/iew_impl.hh:
    Hand Merge

--HG--
extra : convert_revision : ae1b25cde85ab8ec275a09d554acd372887d4d47

diff --cc src/arch/isa_parser.py
index 59eb18c9c80752f2d4191aee90bd162adae8972e,aacdf455f57230ddce51a8d00041b2591d1c06f6..5f6a33565733685651e40b3b050dc068bc6704ce
--- 1/src/arch/isa_parser.py
--- 2/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@@ -1307,7 -1362,7 +1362,7 @@@ class ControlRegOperand(Operand)
          bit_select = 0
          if (self.ctype == 'float' or self.ctype == 'double'):
              error(0, 'Attempt to read control register as FP')
-         base = 'xc->readMiscRegWithEffect(%s)' % self.reg_spec
 -        base = 'xc->readMiscRegOperand(this, %s)' % self.src_reg_idx
++        base = 'xc->readMiscRegOperandWithEffect(%s)' % self.reg_spec
          if self.size == self.dflt_size:
              return '%s = %s;\n' % (self.base_name, base)
          else:

diff --cc src/arch/sparc/faults.cc
Simple merge

diff --cc src/arch/sparc/intregfile.hh
index d66d0fcb779c09abdbca4fdee023e1eb1f70a2a3,503f3c453c6c04b295e5e4b2ca241b6e3deb3915..716d45a657f1e3c1ae9170bcceef4e69d6a63d21
--- 1/src/arch/sparc/intregfile.hh
--- 2/src/arch/sparc/intregfile.hh
+++ b/src/arch/sparc/intregfile.hh
@@@ -67,9 -72,10 +72,10 @@@ namespace SparcIS
                  (unsigned int)(-1) :
                  (1 << FrameOffsetBits) - 1;
  
 -        IntReg regGlobals[MaxGL][RegsPerFrame];
 +        IntReg regGlobals[MaxGL+1][RegsPerFrame];
          IntReg regSegments[2 * NWindows][RegsPerFrame];
          IntReg microRegs[NumMicroIntRegs];
+         IntReg regs[NumIntRegs];
  
          enum regFrame {Globals, Outputs, Locals, Inputs, NumFrames};
  

diff --cc src/arch/sparc/isa/decoder.isa
Simple merge

diff --cc src/arch/sparc/isa/formats/mem/basicmem.isa
index 55e9fba459526dbbdfebfc002b581087c3b4dff1,d5b17d720c61075be5dac0295d29c02bacdaa941..ed0c41e61d5c384321f78c0572e3dbd01fd9f70f
--- 1/src/arch/sparc/isa/formats/mem/basicmem.isa
--- 2/src/arch/sparc/isa/formats/mem/basicmem.isa
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa
@@@ -52,13 -52,17 +52,17 @@@ def template MemDeclare {
  }};
  
  let {{
 -    def doMemFormat(code, execute, faultCode, name, Name, opt_flags):
 +    def doMemFormat(code, execute, faultCode, name, Name, asi, opt_flags):
          addrCalcReg = 'EA = Rs1 + Rs2;'
          addrCalcImm = 'EA = Rs1 + imm;'
-         iop = InstObjParams(name, Name, 'Mem', code,
-                 opt_flags, {"fault_check": faultCode, "ea_code": addrCalcReg})
-         iop_imm = InstObjParams(name, Name + "Imm", 'MemImm', code,
-                 opt_flags, {"fault_check": faultCode, "ea_code": addrCalcImm})
+         iop = InstObjParams(name, Name, 'Mem',
+                 {"code": code, "fault_check": faultCode,
+                  "ea_code": addrCalcReg},
+                 opt_flags)
+         iop_imm = InstObjParams(name, Name + "Imm", 'MemImm',
+                 {"code": code, "fault_check": faultCode,
+                  "ea_code": addrCalcImm},
+                 opt_flags)
          header_output = MemDeclare.subst(iop) + MemDeclare.subst(iop_imm)
          decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
          decode_block = ROrImmDecode.subst(iop)
@@@ -72,16 -76,16 +76,16 @@@ def format LoadAlt(code, asi, *opt_flag
          (header_output,
           decoder_output,
           exec_output,
-          decode_block) = doMemFormat(code, LoadExecute,
+          decode_block) = doMemFormat(code, LoadFuncs,
 -            AlternateAsiPrivFaultCheck, name, Name, opt_flags)
 +            AlternateASIPrivFaultCheck, name, Name, asi, opt_flags)
  }};
  
 -def format StoreAlt(code, *opt_flags) {{
 +def format StoreAlt(code, asi, *opt_flags) {{
          (header_output,
           decoder_output,
           exec_output,
-          decode_block) = doMemFormat(code, StoreExecute,
+          decode_block) = doMemFormat(code, StoreFuncs,
 -            AlternateAsiPrivFaultCheck, name, Name, opt_flags)
 +            AlternateASIPrivFaultCheck, name, Name, asi, opt_flags)
  }};
  
  def format Load(code, *opt_flags) {{
@@@ -89,7 -93,7 +93,7 @@@
           decoder_output,
           exec_output,
           decode_block) = doMemFormat(code,
-              LoadExecute, '', name, Name, 0, opt_flags)
 -             LoadFuncs, '', name, Name, opt_flags)
++             LoadFuncs, '', name, Name, 0, opt_flags)
  }};
  
  def format Store(code, *opt_flags) {{
@@@ -97,5 -101,5 +101,5 @@@
           decoder_output,
           exec_output,
           decode_block) = doMemFormat(code,
-              StoreExecute, '', name, Name, 0, opt_flags)
 -             StoreFuncs, '', name, Name, opt_flags)
++             StoreFuncs, '', name, Name, 0, opt_flags)
  }};

diff --cc src/arch/sparc/isa/formats/mem/blockmem.isa
index 7a1a58d13cb0f45a0be2c4b4f9fc9098e64f5fe6,c124dc600e8d15135412be618096af468cebd614..a0b235a614af0c28aca7f67f50ee496b94f61468
--- 1/src/arch/sparc/isa/formats/mem/blockmem.isa
--- 2/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@@ -314,26 -314,26 +314,26 @@@ let {
          return (header_output, decoder_output, exec_output, decode_block)
  }};
  
 -def format BlockLoad(code, *opt_flags) {{
 -    # We need to make sure to check the highest priority fault last.
 -    # That way, if other faults have been detected, they'll be overwritten
 -    # rather than the other way around.
 -    faultCode = AlternateASIPrivFaultCheck + BlockAlignmentFaultCheck
 -    (header_output,
 -     decoder_output,
 -     exec_output,
 -     decode_block) = doBlockMemFormat(code, faultCode,
 -         LoadFuncs, name, Name, opt_flags)
 +def format BlockLoad(code, asi, *opt_flags) {{
 +        # We need to make sure to check the highest priority fault last.
 +        # That way, if other faults have been detected, they'll be overwritten
 +        # rather than the other way around.
 +        faultCode = AlternateASIPrivFaultCheck + BlockAlignmentFaultCheck
 +        (header_output,
 +         decoder_output,
 +         exec_output,
 +         decode_block) = doBlockMemFormat(code, faultCode,
-              LoadExecute, name, Name, asi, opt_flags)
++             LoadFuncs, name, Name, asi, opt_flags)
  }};
  
 -def format BlockStore(code, *opt_flags) {{
 -    # We need to make sure to check the highest priority fault last.
 -    # That way, if other faults have been detected, they'll be overwritten
 -    # rather than the other way around.
 -    faultCode = AlternateASIPrivFaultCheck + BlockAlignmentFaultCheck
 -    (header_output,
 -     decoder_output,
 -     exec_output,
 -     decode_block) = doBlockMemFormat(code, faultCode,
 -         StoreFuncs, name, Name, opt_flags)
 +def format BlockStore(code, asi, *opt_flags) {{
 +        # We need to make sure to check the highest priority fault last.
 +        # That way, if other faults have been detected, they'll be overwritten
 +        # rather than the other way around.
 +        faultCode = AlternateASIPrivFaultCheck + BlockAlignmentFaultCheck
 +        (header_output,
 +         decoder_output,
 +         exec_output,
 +         decode_block) = doBlockMemFormat(code, faultCode,
-              StoreExecute, name, Name, asi, opt_flags)
++             StoreFuncs, name, Name, asi, opt_flags)
  }};

diff --cc src/arch/sparc/isa/formats/mem/util.isa
index 3e9fd7a7dee9a01d4c78b436d808f22686640fa0,e872230003ba848a9f496f89deb262e93747316a..03b08ae18f0a5a0f5512ca2a23fad7d8d4bca2a7
--- 1/src/arch/sparc/isa/formats/mem/util.isa
--- 2/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@@ -310,21 -318,10 +321,11 @@@ let {
  //and in the other they're distributed across two. Also note that for
  //execute functions, the name of the base class doesn't matter.
  let {{
-     def doSplitExecute(code, execute, name, Name, asi, opt_flags, microParam):
 -    def doSplitExecute(execute, name, Name, opt_flags, microParam):
++    def doSplitExecute(execute, name, Name, asi, opt_flags, microParam):
 +        microParam["asi_val"] = asi;
-         codeParam = microParam.copy()
-         codeParam["ea_code"] = ''
-         codeIop = InstObjParams(name, Name, '', code, opt_flags, codeParam)
-         eaIop = InstObjParams(name, Name, '', microParam["ea_code"],
-                 opt_flags, microParam)
-         iop = InstObjParams(name, Name, '', code, opt_flags, microParam)
-         (iop.ea_decl,
-          iop.ea_rd,
-          iop.ea_wb) = (eaIop.op_decl, eaIop.op_rd, eaIop.op_wb)
-         (iop.code_decl,
-          iop.code_rd,
-          iop.code_wb) = (codeIop.op_decl, codeIop.op_rd, codeIop.op_wb)
-         return execute.subst(iop)
+         iop = InstObjParams(name, Name, '', microParam, opt_flags)
+         (execf, initf, compf) = execute
+         return execf.subst(iop) + initf.subst(iop) + compf.subst(iop)
  
  
      def doDualSplitExecute(code, eaRegCode, eaImmCode, execute,
@@@ -333,8 -330,9 +334,9 @@@
          for (eaCode, name, Name) in (
                  (eaRegCode, nameReg, NameReg),
                  (eaImmCode, nameImm, NameImm)):
-             microParams = {"ea_code" : eaCode, "fault_check": faultCode}
-             executeCode += doSplitExecute(code, execute, name, Name,
+             microParams = {"code": code, "ea_code": eaCode,
+                 "fault_check": faultCode}
+             executeCode += doSplitExecute(execute, name, Name,
 -                    opt_flags, microParams)
 +                    asi, opt_flags, microParams)
          return executeCode
  }};

diff --cc src/arch/sparc/isa_traits.hh
Simple merge

diff --cc src/arch/sparc/miscregfile.cc
index 53559c072e9c35b7c36d03028147637720c89a12,50a4f487103d59b4ca3165d16812d7d562dd9e85..6641d38bb7027e7d8edf5ea1999234e915ca4534
--- 1/src/arch/sparc/miscregfile.cc
--- 2/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@@ -46,15 -50,15 +46,9 @@@ class Checkpoint
  string SparcISA::getMiscRegName(RegIndex index)
  {
      static::string miscRegName[NumMiscRegs] =
-        {"y", "ccr", "asi", "tick", "fprs", "pcr", "pic",
-         "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
-         "stick", "stick_cmpr",
-         "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
-         "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
-         "wstate", "gl",
-         "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
-         "hstick_cmpr",
-         "fsr"};
+         {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
 -         "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
 -         "stick", "stick_cmpr",
 -         "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
+          "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
+          "wstate",*/ "gl",
 -         "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
 -         "hstick_cmpr",
 -         "fsr"};
      return miscRegName[index];
  }
  

diff --cc src/arch/sparc/miscregfile.hh
Simple merge

diff --cc src/arch/sparc/regfile.cc
Simple merge

diff --cc src/arch/sparc/regfile.hh
Simple merge

diff --cc src/cpu/exetrace.cc
index 3fe40b4c167513ae20b6ecaa1be9be081f328b0d,780a0c4f77076bd071bf2fd4a4cf86f1c9da8448..98e75d83aa8b2de80c0c1ac832d1e6e28de81270
--- 1/src/cpu/exetrace.cc
--- 2/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@@ -385,18 -381,26 +391,26 @@@ Trace::InstRecord::dump(ostream &outs
                          diffPil = true;
                      if(shared_data->cwp != thread->readMiscReg(MISCREG_CWP))
                          diffCwp = true;
-                     if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE))
+                     //if(shared_data->cansave != thread->readMiscReg(MISCREG_CANSAVE))
+                     if(shared_data->cansave !=
+                             thread->readIntReg(NumIntArchRegs + 3))
                          diffCansave = true;
+                     //if(shared_data->canrestore !=
+                     //            thread->readMiscReg(MISCREG_CANRESTORE))
                      if(shared_data->canrestore !=
-                             thread->readMiscReg(MISCREG_CANRESTORE))
+                             thread->readMiscReg(NumIntArchRegs + 4))
                          diffCanrestore = true;
-                     if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN))
+                     //if(shared_data->otherwin != thread->readMiscReg(MISCREG_OTHERWIN))
+                     if(shared_data->otherwin !=
+                             thread->readIntReg(NumIntArchRegs + 5))
                          diffOtherwin = true;
-                     if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN))
+                     //if(shared_data->cleanwin != thread->readMiscReg(MISCREG_CLEANWIN))
+                     if(shared_data->cleanwin !=
+                             thread->readMiscReg(NumIntArchRegs + 6))
                          diffCleanwin = true;
  
 -                    if (diffPC || diffInst || diffRegs || diffTpc || diffTnpc ||
 -                            diffTstate || diffTt || diffHpstate ||
 +                    if ((diffPC || diffCC || diffInst || diffRegs || diffTpc ||
 +                            diffTnpc || diffTstate || diffTt || diffHpstate ||
                              diffHtstate || diffHtba || diffPstate || diffY ||
                              diffCcr || diffTl || diffGl || diffAsi || diffPil ||
                              diffCwp || diffCansave || diffCanrestore ||

diff --cc src/cpu/o3/fetch.hh
Simple merge

diff --cc src/cpu/o3/iew_impl.hh
index 76047b295353e17127700b6dd617d80c1a8c2373,24c8484b48ad57d72ae429c58ea8fb37ce6bd29d..70200d64855b7113d394fd812ffb68d9515b4581
--- 1/src/cpu/o3/iew_impl.hh
--- 2/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@@ -514,7 -525,9 +525,10 @@@ DefaultIEW<Impl>::squashDueToMemOrder(D
      toCommit->squash[tid] = true;
      toCommit->squashedSeqNum[tid] = inst->seqNum;
      toCommit->nextPC[tid] = inst->readNextPC();
+ #if ISA_HAS_DELAY_SLOT
+     toCommit->nextNPC[tid] = inst->readNextNPC();
+ #endif
 +    toCommit->branchMispredict[tid] = false;
  
      toCommit->includeSquashInst[tid] = false;
  
@@@ -531,7 -544,9 +545,10 @@@ DefaultIEW<Impl>::squashDueToMemBlocked
      toCommit->squash[tid] = true;
      toCommit->squashedSeqNum[tid] = inst->seqNum;
      toCommit->nextPC[tid] = inst->readPC();
+ #if ISA_HAS_DELAY_SLOT
+     toCommit->nextNPC[tid] = inst->readNextNPC();
+ #endif
 +    toCommit->branchMispredict[tid] = false;
  
      // Must include the broadcasted SN in the squash.
      toCommit->includeSquashInst[tid] = true;