Add handling of init attributes in "opt_expr -undriven"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index af6d352afa04e6a4cf7612451f664d0a27f3587b..b445afdc806114cae94d3376cfa5b168961055a4 100644 (file)
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -39,6 +39,9 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
        SigPool used_signals;
        SigPool all_signals;
 
+       dict<SigBit, pair<Wire*, State>> initbits;
+       pool<Wire*> revisit_initwires;
+
        for (auto cell : module->cells())
        for (auto &conn : cell->connections()) {
                if (!ct.cell_known(cell->type) || ct.cell_output(cell->type, conn.first))
@@ -48,6 +51,14 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
        }
 
        for (auto wire : module->wires()) {
+               if (wire->attributes.count("\\init")) {
+                       SigSpec sig = sigmap(wire);
+                       Const initval = wire->attributes.at("\\init");
+                       for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) {
+                               if (initval[i] == State::S0 || initval[i] == State::S1)
+                                       initbits[sig[i]] = make_pair(wire, initval[i]);
+                       }
+               }
                if (wire->port_input)
                        driven_signals.add(sigmap(wire));
                if (wire->port_output)
@@ -67,10 +78,38 @@ void replace_undriven(RTLIL::Design *design, RTLIL::Module *module)
                if (sig.size() == 0)
                        continue;
 
-               log_debug("Setting undriven signal in %s to undef: %s\n", RTLIL::id2cstr(module->name), log_signal(c));
-               module->connect(RTLIL::SigSig(c, RTLIL::SigSpec(RTLIL::State::Sx, c.width)));
+               Const val(RTLIL::State::Sx, GetSize(sig));
+               for (int i = 0; i < GetSize(sig); i++) {
+                       SigBit bit = sigmap(sig[i]);
+                       auto cursor = initbits.find(bit);
+                       if (cursor != initbits.end()) {
+                               revisit_initwires.insert(cursor->second.first);
+                               val[i] = cursor->second.second;
+                       }
+               }
+
+               log_debug("Setting undriven signal in %s to constant: %s = %s\n", RTLIL::id2cstr(module->name), log_signal(sig), log_signal(val));
+               module->connect(sig, val);
                did_something = true;
        }
+
+       if (!revisit_initwires.empty())
+       {
+               SigMap sm2(module);
+
+               for (auto wire : revisit_initwires) {
+                       SigSpec sig = sm2(wire);
+                       Const initval = wire->attributes.at("\\init");
+                       for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) {
+                               if (SigBit(initval[i]) == sig[i])
+                                       initval[i] = State::Sx;
+                       }
+                       if (initval.is_fully_undef())
+                               wire->attributes.erase("\\init");
+                       else
+                               wire->attributes["\\init"] = initval;
+               }
+       }
 }
 
 void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell, std::string info, std::string out_port, RTLIL::SigSpec out_val)

diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc
index 4b889d672e8a6599c745608bc4f2a13c7c554fd7..c6e12248e6d7298429bf98b1ba43d4d5b4543f3e 100644 (file)
--- a/techlibs/ecp5/synth_ecp5.cc
+++ b/techlibs/ecp5/synth_ecp5.cc
@@ -253,7 +253,7 @@ struct SynthEcp5Pass : public ScriptPass
                        if (!nodffe)
                                run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*");
                        run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
-                       run("opt_expr -mux_undef");
+                       run("opt_expr -undriven -mux_undef");
                        run("simplemap");
                        run("ecp5_ffinit");
                }