proof-of-concept, redirect RS1 to class sv_proc_t

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index f37eaa783fad3915bb0afe1fb3501f7038b0dd86..4c1c161de853c4633633b57ef21cc2877b9be353 100644 (file)
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -73,6 +73,17 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
     return p->s.FN(p, s_insn, pc);
 }
 
+#ifdef USING_NOREGS
+#define sv_enabled false
+// not going to make any difference...
+#define DEST_PREDINT 1
+#define SRC_PREDINT 1
+#define PRED_ARGS dest_pred,dest_pred,dest_pred,dest_pred,&dest_pred
+#define OFFS_ARGS dest_offs,dest_offs,dest_offs,dest_offs,dest_offs
+#else
+#define sv_enabled true
+#endif
+
 reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
 {
   int xlen = ISASZ;
@@ -83,10 +94,6 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
   // and create an sv-variant.  also an opportunity to pass
   // in a stack of other things that are needed.
   insn_bits_t bits = s_insn.bits();
-#ifdef USING_NOREGS
-  insn_t insn(bits);
-  #include INCLUDEFILE
-#else
   int vlen = 0;
   if (p->get_state()->prv == 0) { // XXX HACK - disable in supervisor mode
     vlen = p->get_state()->vl;
@@ -106,8 +113,11 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
   reg_t target_pred = ~0x0;
   bool zeroingtarg = false;
 #endif
-  sv_insn_t insn(p, bits, floatintmap, PRED_ARGS, OFFS_ARGS);
-  p->s.insn = insn;
+  sv_insn_t insn(p, sv_enabled, bits, floatintmap, PRED_ARGS, OFFS_ARGS);
+  p->s.set_insn(&insn);
+#ifdef USING_NOREGS
+  #include INCLUDEFILE
+#else
 #ifdef INSN_TYPE_BRANCH
   sv_pred_entry *r = insn.get_predentry(s_insn.rs2(), true);
   reg_t _target_reg = 0;
@@ -211,7 +221,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
 #endif
 #ifdef INSN_C_SWSP
     fprintf(stderr, "pre %s %x vloop %d %d %d" \
-                      "vlen %d stop %d pred %lx rdv %lx v %d rvc2 %d sp %lx\n",
+                      "vlen %d stop %d pred %lx rdv %lx v %d rvc2 %ld sp %lx\n",
                 xstr(INSN), INSNCODE, voffs, *src_offs, *dest_offs,
                 vlen, insn.stop_vloop(),
                 dest_pred & (1<<voffs), READ_REG(insn._rvc_rs2()),
@@ -219,7 +229,7 @@ reg_t sv_proc_t::FN(processor_t* p, insn_t s_insn, reg_t pc)
 #endif
 #ifdef INSN_C_LWSP
     fprintf(stderr, "pre %s %x vloop %d %d %d" \
-                      "vlen %d stop %d pred %lx rdv %lx rd %d rvc2 %d sp %lx\n",
+                      "vlen %d stop %d pred %lx rdv %lx rd %d rvc2 %ld sp %lx\n",
                 xstr(INSN), INSNCODE, voffs, *src_offs, *dest_offs,
                 vlen, insn.stop_vloop(),
                 dest_pred & (1<<voffs), READ_REG(insn._rd()),

diff --git a/riscv/rocc.cc b/riscv/rocc.cc
index db03e37c4869e39f5a96808706dac09a3e25b266..49509b5e0151d3d8f1576eeab33a774baa5af0e7 100644 (file)
--- a/riscv/rocc.cc
+++ b/riscv/rocc.cc
@@ -4,6 +4,14 @@
 #include "trap.h"
 #include <cstdlib>
 
+// skip for now
+#ifdef SPIKE_SIMPLEV
+#define customX(n) \
+  static reg_t c##n(processor_t* p, insn_t insn, reg_t pc) \
+  { \
+    return 0; \
+  }
+#else
 #define customX(n) \
   static reg_t c##n(processor_t* p, insn_t insn, reg_t pc) \
   { \
@@ -23,6 +31,7 @@
     illegal_instruction(); \
     return 0; \
   }
+#endif
 
 customX(0)
 customX(1)

diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index 8438f1cb212209ccfb0d8c569b4fd168b9050301..adbb0d66a16056de61047626248ab47fe05f33f6 100644 (file)
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -22,11 +22,11 @@ class processor_t;
 class sv_insn_t: public insn_t
 {
 public:
-  sv_insn_t(processor_t *pr, insn_bits_t bits, unsigned int f,
+  sv_insn_t(processor_t *pr, bool _sv_enabled, insn_bits_t bits, unsigned int f,
             uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3,
             uint64_t *p_im,
             int *o_rd, int *o_rs1, int *o_rs2, int *o_rs3, int *o_imm) :
-            insn_t(bits), p(pr), vloop_continue(false),
+            insn_t(bits), p(pr), sv_enabled(_sv_enabled), vloop_continue(false),
             at_least_one_reg_vectorised(false), fimap(f),
             offs_rd(o_rd), offs_rs1(o_rs1), offs_rs2(o_rs2), offs_rs3(o_rs3),
             offs_imm(o_imm),
@@ -76,6 +76,7 @@ public:
   bool stop_vloop(void);
 
   processor_t *p;
+  bool sv_enabled;
 
   // cached version of remap: if remap is called multiple times
   // by an emulated instruction it would increment the loop offset

diff --git a/riscv/sv_insn_redirect.cc b/riscv/sv_insn_redirect.cc
index 85ed53687f934bc909bdd3ce36802104e4d9ef65..e222922f63f9ec5adad97784feb44e6db91c71fc 100644 (file)
--- a/riscv/sv_insn_redirect.cc
+++ b/riscv/sv_insn_redirect.cc
@@ -5,3 +5,15 @@ void (sv_proc_t::WRITE_RD)(reg_t value)
 {
     WRITE_RD( value );
 }
+
+/*
+reg_t (sv_proc_t::READ_REG)(uint64_t i)
+{
+    return READ_REG ( i );
+}
+*/
+
+RS1::operator reg_t () const {
+    return _insn->p->get_state()->XPR[_insn->rs1()];
+}
+

diff --git a/riscv/sv_insn_redirect.h b/riscv/sv_insn_redirect.h
index ebdc607052e1b7e791695e8dff3c9d584d48ccf6..2e71c951ceb9b4a36a25ae1577d0b2ec2fab916d 100644 (file)
--- a/riscv/sv_insn_redirect.h
+++ b/riscv/sv_insn_redirect.h
@@ -1,29 +1,49 @@
 #ifndef SV_INSN_REDIRECT_H
 #define SV_INSN_REDIRECT_H
 
+#include <stdio.h>
 #include "decode.h"
 #include "sv_decode.h"
 
+#undef RS1
+
 class processor_t;
 class insn_t;
 
+class RS1 {
+    public:
+        sv_insn_t *_insn;
+        RS1() : _insn(NULL) {}
+        //sv_insn_t & operator = (sv_insn_t &i)
+        //{ _insn = &i; return i; }
+        operator reg_t () const;
+};
+
 class sv_proc_t
 {
 public:
     sv_proc_t(processor_t *_p) : p(_p) {}
     void (WRITE_RD)(reg_t value);
+    //reg_t (READ_REG)(uint64_t i);
 
     processor_t *p;
 
+    class RS1 RS1;
+
     class {
         public:
         sv_insn_t *_insn;
         sv_insn_t & operator = (sv_insn_t &i)
         { _insn = &i; return i; }
-        operator sv_insn_t () const { return *_insn; }
+        operator sv_insn_t () const & { return *_insn; }
         uint64_t rd() { return _insn->rd(); }
     } insn;
 
+    void set_insn(sv_insn_t *i) {
+        this->insn = *i;
+        RS1._insn = i;
+    }
+
 #include "sv_insn_decl.h"
 };