cpu/soc_core: automatically set csr mapping to 0x00000000 when using CPUNone, remove...

diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py
index 4c273e50b7b71e71e81a41aeab7af1260c51caf0..d861bf07ed48113226e4001727427d8362f833ec 100644 (file)
--- a/litex/soc/cores/cpu/__init__.py
+++ b/litex/soc/cores/cpu/__init__.py
@@ -28,6 +28,7 @@ class CPUNone(CPU):
     io_regions           = {0x00000000: 0x100000000} # origin, length
     periph_buses         = []
     memory_buses         = []
+    mem_map              = {"csr": 0x00000000}
 
 CPU_GCC_TRIPLE_RISCV32 = (
     "riscv64-unknown-elf",

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 8a4dd9371f451f928731c267ff91aa6870891c1c..a44f6d8f67316c1c40a0fe1fbb2437a5529cf67a 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -85,7 +85,6 @@ class SoCCore(LiteXSoC):
         csr_alignment            = 32,
         csr_address_width        = 14,
         csr_paging               = 0x800,
-        csr_base                 = None,
         # Identifier parameters
         ident                    = "",
         ident_version            = False,
@@ -185,7 +184,7 @@ class SoCCore(LiteXSoC):
             self.add_timer(name="timer0")
 
         # Add CSR bridge
-        self.add_csr_bridge(self.mem_map["csr"] if csr_base is None else csr_base)
+        self.add_csr_bridge(self.mem_map["csr"])
 
     # Methods --------------------------------------------------------------------------------------