radeonsi/gfx10: enable 1D textures

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 80ea6915d0a9eff2a6737304e9288f9e42e5a90f..7d871c47204afca4540ef09a8bfc5d29ae2d55dd 100644 (file)
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1471,6 +1471,8 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
         * must sample 1D textures as 2D. */
        if (config->is_3d)
                AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_3D;
+       else if (info->chip_class != GFX9 && config->is_1d)
+               AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_1D;
        else
                AddrSurfInfoIn.resourceType = ADDR_RSRC_TEX_2D;
 

diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 0c8a7b11380ba35ea07a7f789ea43dab4ca2fff1..ca577b6e5db7c63147d7485280ae4445071e2427 100644 (file)
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -253,6 +253,7 @@ struct ac_surf_info {
 
 struct ac_surf_config {
        struct ac_surf_info info;
+       unsigned is_1d : 1;
        unsigned is_3d : 1;
        unsigned is_cube : 1;
 };

diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
index 01df9962ee8bc3451866b53cddab58906a3c5ea3..2707d5fc89191885fbd895086cde14feac8f68ca 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
@@ -93,7 +93,7 @@ ac_texture_dim_from_tgsi_target(struct si_screen *screen, enum tgsi_texture_type
        switch (target) {
        case TGSI_TEXTURE_1D:
        case TGSI_TEXTURE_SHADOW1D:
-               if (screen->info.chip_class >= GFX9)
+               if (screen->info.chip_class == GFX9)
                        return ac_image_2d;
                return ac_image_1d;
        case TGSI_TEXTURE_2D:
@@ -110,7 +110,7 @@ ac_texture_dim_from_tgsi_target(struct si_screen *screen, enum tgsi_texture_type
                return ac_image_cube;
        case TGSI_TEXTURE_1D_ARRAY:
        case TGSI_TEXTURE_SHADOW1D_ARRAY:
-               if (screen->info.chip_class >= GFX9)
+               if (screen->info.chip_class == GFX9)
                        return ac_image_2darray;
                return ac_image_1darray;
        case TGSI_TEXTURE_2D_ARRAY:
@@ -287,15 +287,14 @@ static void image_fetch_coords(
                coords[chan] = tmp;
        }
 
-       if (ctx->screen->info.chip_class >= GFX9) {
+       if (ctx->screen->info.chip_class == GFX9) {
                /* 1D textures are allocated and used as 2D on GFX9. */
                if (target == TGSI_TEXTURE_1D) {
                        coords[1] = ctx->i32_0;
                } else if (target == TGSI_TEXTURE_1D_ARRAY) {
                        coords[2] = coords[1];
                        coords[1] = ctx->i32_0;
-               } else if (ctx->screen->info.chip_class == GFX9 &&
-                          target == TGSI_TEXTURE_2D) {
+               } else if (target == TGSI_TEXTURE_2D) {
                        /* The hw can't bind a slice of a 3D image as a 2D
                         * image, because it ignores BASE_ARRAY if the target
                         * is 3D. The workaround is to read BASE_ARRAY and set
@@ -920,7 +919,7 @@ static LLVMValueRef fix_resinfo(struct si_shader_context *ctx,
        LLVMBuilderRef builder = ctx->ac.builder;
 
        /* 1D textures are allocated and used as 2D on GFX9. */
-        if (ctx->screen->info.chip_class >= GFX9 &&
+        if (ctx->screen->info.chip_class == GFX9 &&
            (target == TGSI_TEXTURE_1D_ARRAY ||
             target == TGSI_TEXTURE_SHADOW1D_ARRAY)) {
                LLVMValueRef layers =
@@ -1457,7 +1456,7 @@ static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
                        num_src_deriv_channels = 1;
 
                        /* 1D textures are allocated and used as 2D on GFX9. */
-                       if (ctx->screen->info.chip_class >= GFX9) {
+                       if (ctx->screen->info.chip_class == GFX9) {
                                num_dst_deriv_channels = 2;
                        } else {
                                num_dst_deriv_channels = 1;
@@ -1499,7 +1498,7 @@ static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
        }
 
        /* 1D textures are allocated and used as 2D on GFX9. */
-       if (ctx->screen->info.chip_class >= GFX9) {
+       if (ctx->screen->info.chip_class == GFX9) {
                LLVMValueRef filler;
 
                /* Use 0.5, so that we don't sample the border color. */

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index b857e102cc1ef5abacd7d5fb41fe93ed02d63a76..8d6ef8c6a3fe12d1c5d85e5cf7bdc8ab76874ef1 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1985,7 +1985,7 @@ static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex,
        /* GFX9 allocates 1D textures as 2D. */
        if ((res_target == PIPE_TEXTURE_1D ||
             res_target == PIPE_TEXTURE_1D_ARRAY) &&
-           sscreen->info.chip_class >= GFX9 &&
+           sscreen->info.chip_class == GFX9 &&
            tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
                if (res_target == PIPE_TEXTURE_1D)
                        res_target = PIPE_TEXTURE_2D;

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 1dff1b3447eebdd0365925c2e34145db473470a2..4f410d5c88ef35d3aa0496318ebf68a72e468a7e 100644 (file)
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -88,8 +88,10 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
    config.info.storage_samples = tex->nr_storage_samples;
    config.info.levels = tex->last_level + 1;
    config.info.num_channels = util_format_get_nr_components(tex->format);
-   config.is_3d = !!(tex->target == PIPE_TEXTURE_3D);
-   config.is_cube = !!(tex->target == PIPE_TEXTURE_CUBE);
+   config.is_1d = tex->target == PIPE_TEXTURE_1D ||
+                  tex->target == PIPE_TEXTURE_1D_ARRAY;
+   config.is_3d = tex->target == PIPE_TEXTURE_3D;
+   config.is_cube = tex->target == PIPE_TEXTURE_CUBE;
 
    /* Use different surface counters for color and FMASK, so that MSAA MRTs
     * always use consecutive surface indices when FMASK is allocated between