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diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index 1a5b885963a007e33178b71229dccfbe3ca3609b..afbac817716c1f5292be247163aa846566d5afab 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -147,9 +147,9 @@ Note that the operation takes place at the maximum bitwidth (max of src and dest
 
 # Reduce mode
 
-There are two variants here.  The first is when the destination is scalar and at least one of the sources is Vector.  The second is more complex and involves reduction on vectors.
+There are two variants here.  The first is when the destination is scalar and at least one of the sources is Vector.  The second is more complex and involves map-reduction on vectors.
 
-The defining characteristic distinguishing Scalar-dest reduce mode from Vector reduce mode is that Scalar-dest reduce issues VL element operations whereas Vector reduce mode performs an actual map-reduce (tree reduction) typically `O(VL log VL)` actual computations.
+The defining characteristic distinguishing Scalar-dest reduce mode from Vector reduce mode is that Scalar-dest reduce issues VL element operations, whereas Vector reduce mode performs an actual map-reduce (tree reduction): typically `O(VL log VL)` actual computations.
 
 ## Scalar result reduce mode
 
@@ -168,7 +168,7 @@ where, clearly, r3 is being used to accumulate the addition of all elements is t
 
 However, *unless* the operation is marked as "mapreduce", SV **terminates** at the first scalar operation.  Only by marking the operation as "mapreduce" will it continue to issue multiple sub-looped (element) instructions in `Program Order`.
 
-Other examples include shift-mask operations where a Vector of inserts into a single destination register is required, as a way to construct a value quickly from multiple arbitrary bit-ranges and bit-offsets.  Using the same register as both the source and destination, with Vectirs of different offsets masks and values to be inserted has multiple applications including Video, cryptography and JIT compilation. 
+Other examples include shift-mask operations where a Vector of inserts into a single destination register is required, as a way to construct a value quickly from multiple arbitrary bit-ranges and bit-offsets.  Using the same register as both the source and destination, with Vectors of different offsets masks and values to be inserted has multiple applications including Video, cryptography and JIT compilation. 
 
 ## Vector result reduce mode