This function is no longer used anywhere in gem5.
Small helper functions which had been put alongside vtophys on ARM and
RISCV were also moved into src/arch/arm/remote_gdb.cc and
src/arch/power/pagetable.hh, the only places they were used.
Change-Id: Iba72f6c4b797a35a785a5bb781d602c943541fa7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26234
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
stacktrace.hh
types.hh
utility.hh
- vtophys.hh
'''),
env.subst('${TARGET_ISA}'))
Source('tlb.cc')
Source('tlbi_op.cc')
Source('utility.cc')
- Source('vtophys.cc')
SimObject('ArmFsWorkload.py')
SimObject('ArmInterrupts.py')
#include "arch/arm/isa_traits.hh"
#include "arch/arm/utility.hh"
-#include "arch/arm/vtophys.hh"
#include "sim/serialize.hh"
namespace ArmISA {
#include "arch/arm/registers.hh"
#include "arch/arm/system.hh"
#include "arch/arm/utility.hh"
-#include "arch/arm/vtophys.hh"
+#include "arch/generic/tlb.hh"
#include "base/chunk_generator.hh"
#include "base/intmath.hh"
#include "base/remote_gdb.hh"
using namespace std;
using namespace ArmISA;
+static bool
+tryTranslate(ThreadContext *tc, Addr addr)
+{
+ // Set up a functional memory Request to pass to the TLB
+ // to get it to translate the vaddr to a paddr
+ auto req = std::make_shared<Request>(addr, 64, 0x40, -1, 0, 0);
+
+ // Check the TLBs for a translation
+ // It's possible that there is a valid translation in the tlb
+ // that is no loger valid in the page table in memory
+ // so we need to check here first
+ //
+ // Calling translateFunctional invokes a table-walk if required
+ // so we should always succeed
+ auto *dtb = tc->getDTBPtr();
+ auto *itb = tc->getITBPtr();
+ return dtb->translateFunctional(req, tc, BaseTLB::Read) == NoFault ||
+ itb->translateFunctional(req, tc, BaseTLB::Read) == NoFault;
+}
+
RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc, int _port)
: BaseRemoteGDB(_system, tc, _port), regCache32(this), regCache64(this)
{
{
if (FullSystem) {
for (ChunkGenerator gen(va, len, PageBytes); !gen.done(); gen.next()) {
- if (!virtvalid(context(), gen.addr())) {
+ if (!tryTranslate(context(), gen.addr())) {
DPRINTF(GDBAcc, "acc: %#x mapping is invalid\n", va);
return false;
}
#include <string>
#include "arch/arm/isa_traits.hh"
-#include "arch/arm/vtophys.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
#include "arch/arm/isa_traits.hh"
#include "arch/arm/pagetable.hh"
#include "arch/arm/utility.hh"
-#include "arch/arm/vtophys.hh"
#include "arch/generic/tlb.hh"
#include "base/statistics.hh"
#include "mem/request.hh"
#include "arch/arm/isa_traits.hh"
#include "arch/arm/system.hh"
#include "arch/arm/tlb.hh"
-#include "arch/arm/vtophys.hh"
#include "cpu/base.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/thread_context.hh"
+++ /dev/null
-/*
- * Copyright (c) 2010, 2012-2013 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * Copyright (c) 2007-2008 The Florida State University
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/arm/vtophys.hh"
-
-#include <string>
-
-#include "arch/arm/faults.hh"
-#include "arch/arm/table_walker.hh"
-#include "arch/arm/tlb.hh"
-#include "base/chunk_generator.hh"
-#include "base/trace.hh"
-#include "cpu/thread_context.hh"
-#include "mem/fs_translating_port_proxy.hh"
-
-using namespace std;
-using namespace ArmISA;
-
-static std::pair<bool, Addr>
-try_translate(ThreadContext *tc, Addr addr)
-{
- Fault fault;
- // Set up a functional memory Request to pass to the TLB
- // to get it to translate the vaddr to a paddr
- auto req = std::make_shared<Request>(addr, 64, 0x40, -1, 0, 0);
- BaseTLB *tlb;
-
- // Check the TLBs for a translation
- // It's possible that there is a valid translation in the tlb
- // that is no loger valid in the page table in memory
- // so we need to check here first
- //
- // Calling translateFunctional invokes a table-walk if required
- // so we should always succeed
- tlb = tc->getDTBPtr();
- fault = tlb->translateFunctional(req, tc, BaseTLB::Read);
- if (fault == NoFault)
- return std::make_pair(true, req->getPaddr());
-
- tlb = tc->getITBPtr();
- fault = tlb->translateFunctional(req, tc, BaseTLB::Read);
- if (fault == NoFault)
- return std::make_pair(true, req->getPaddr());
-
- return std::make_pair(false, 0);
-}
-
-Addr
-ArmISA::vtophys(ThreadContext *tc, Addr addr)
-{
- const std::pair<bool, Addr> translation(try_translate(tc, addr));
-
- if (translation.first)
- return translation.second;
- else
- panic("Table walkers support functional accesses. "
- "We should never get here.");
-}
-
-bool
-ArmISA::virtvalid(ThreadContext *tc, Addr vaddr)
-{
- const std::pair<bool, Addr> translation(try_translate(tc, vaddr));
-
- return translation.first;
-}
-
-
+++ /dev/null
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * Copyright (c) 2007-2008 The Florida State University
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_ARM_VTOPHYS_HH__
-#define __ARCH_ARM_VTOPHYS_HH__
-
-#include "arch/arm/isa_traits.hh"
-#include "arch/arm/utility.hh"
-
-class ThreadContext;
-
-namespace ArmISA
-{
-
-inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
-
-Addr vtophys(ThreadContext *tc, Addr vaddr);
-bool virtvalid(ThreadContext *tc, Addr vaddr);
-
-} // namespace ArmISA
-
-#endif // __ARCH_ARM_VTOPHYS_HH__
-
Source('system.cc')
Source('tlb.cc')
Source('utility.cc')
- Source('vtophys.cc')
SimObject('MipsInterrupts.py')
SimObject('MipsISA.py')
#include "arch/generic/linux/threadinfo.hh"
#include "arch/mips/idle_event.hh"
#include "arch/mips/system.hh"
-#include "arch/vtophys.hh"
#include "base/loader/symtab.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include <string>
#include "arch/mips/decoder.hh"
-#include "arch/mips/vtophys.hh"
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "debug/GDBMisc.hh"
#include <string>
#include "arch/mips/isa_traits.hh"
-#include "arch/mips/vtophys.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
#include "arch/mips/system.hh"
#include "arch/mips/registers.hh"
-#include "arch/mips/vtophys.hh"
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "arch/mips/isa_traits.hh"
#include "arch/mips/pagetable.hh"
#include "arch/mips/utility.hh"
-#include "arch/mips/vtophys.hh"
#include "base/statistics.hh"
#include "mem/request.hh"
#include "params/MipsTLB.hh"
#include "arch/mips/isa_traits.hh"
#include "arch/mips/registers.hh"
-#include "arch/mips/vtophys.hh"
#include "base/bitfield.hh"
#include "base/logging.hh"
#include "cpu/static_inst.hh"
+++ /dev/null
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * Copyright (c) 2007 MIPS Technologies, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/mips/vtophys.hh"
-
-#include "base/logging.hh"
-
-Addr
-MipsISA::vtophys(ThreadContext *tc, Addr addr)
-{
- fatal("VTOPHYS: Unimplemented on MIPS\n");
-}
-
+++ /dev/null
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * Copyright (c) 2007 MIPS Technologies, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_MIPS_VTOPHYS_HH__
-#define __ARCH_MIPS_VTOPHYS_HH__
-
-#include "arch/mips/isa_traits.hh"
-#include "arch/mips/utility.hh"
-
-class ThreadContext;
-
-namespace MipsISA
-{
-
-Addr vtophys(ThreadContext *tc, Addr vaddr);
-
-} // namespace MipsISA
-
-#endif // __ARCH_MIPS_VTOPHYS_HH__
-
Source('stacktrace.cc')
Source('tlb.cc')
Source('utility.cc')
- Source('vtophys.cc')
SimObject('PowerInterrupts.py')
SimObject('PowerISA.py')
#include "arch/power/isa_traits.hh"
#include "arch/power/utility.hh"
-#include "arch/power/vtophys.hh"
-namespace PowerISA {
+namespace PowerISA
+{
+
+static inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
struct VAddr
{
#include <string>
-#include "arch/power/vtophys.hh"
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "debug/GDBMisc.hh"
#include "arch/power/isa_traits.hh"
#include "arch/power/pagetable.hh"
#include "arch/power/utility.hh"
-#include "arch/power/vtophys.hh"
#include "base/statistics.hh"
#include "mem/request.hh"
#include "params/PowerTLB.hh"
+++ /dev/null
-/*
- * Copyright (c) 2012 Google
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/power/vtophys.hh"
-
-using namespace std;
-
-Addr
-PowerISA::vtophys(ThreadContext *tc, Addr addr)
-{
- fatal("vtophys: Unimplemented on POWER\n");
-}
-
+++ /dev/null
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * Copyright (c) 2007-2008 The Florida State University
- * Copyright (c) 2009 The University of Edinburgh
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_POWER_VTOPHYS_HH__
-#define __ARCH_POWER_VTOPHYS_HH__
-
-#include "arch/power/isa_traits.hh"
-#include "arch/power/utility.hh"
-
-class ThreadContext;
-
-namespace PowerISA
-{
-
-Addr vtophys(ThreadContext *tc, Addr vaddr);
-
-inline Addr
-PteAddr(Addr a)
-{
- return (a & PteMask) << PteShift;
-}
-
-} // namespace PowerISA
-
-#endif // __ARCH_POWER_VTOPHYS_HH__
-
#include "arch/riscv/isa_traits.hh"
#include "arch/riscv/pagetable.hh"
#include "arch/riscv/utility.hh"
-#include "arch/riscv/vtophys.hh"
#include "base/statistics.hh"
#include "mem/request.hh"
#include "params/RiscvTLB.hh"
+++ /dev/null
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * Copyright (c) 2007-2008 The Florida State University
- * Copyright (c) 2009 The University of Edinburgh
- * Copyright (c) 2014-2015 Sven Karlsson
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_RISCV_VTOPHYS_HH__
-#define __ARCH_RISCV_VTOPHYS_HH__
-
-#include "arch/riscv/isa_traits.hh"
-#include "arch/riscv/utility.hh"
-
-class ThreadContext;
-
-namespace RiscvISA
-{
-
-static inline Addr
-vtophys(ThreadContext *tc, Addr vaddr)
-{
- fatal("VTOPHYS: Unimplemented on RISC-V\n");
-}
-
-} // namespace RiscvISA
-
-#endif // __ARCH_RISCV_VTOPHYS_HH__
-
Source('tlb.cc')
Source('ua2005.cc')
Source('utility.cc')
- Source('vtophys.cc')
SimObject('SparcFsWorkload.py')
SimObject('SparcInterrupts.py')
#include "arch/sparc/fs_workload.hh"
#include "arch/sparc/faults.hh"
-#include "arch/vtophys.hh"
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include <csignal>
#include <string>
-#include "arch/vtophys.hh"
#include "base/intmath.hh"
#include "base/remote_gdb.hh"
#include "base/socket.hh"
#include "arch/sparc/utility.hh"
#include "arch/sparc/faults.hh"
-#include "arch/sparc/vtophys.hh"
#include "mem/fs_translating_port_proxy.hh"
namespace SparcISA {
+++ /dev/null
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/sparc/vtophys.hh"
-
-#include <string>
-
-#include "arch/sparc/pagetable.hh"
-#include "arch/sparc/tlb.hh"
-#include "base/chunk_generator.hh"
-#include "base/compiler.hh"
-#include "base/trace.hh"
-#include "cpu/thread_context.hh"
-#include "debug/VtoPhys.hh"
-#include "mem/port_proxy.hh"
-
-using namespace std;
-
-namespace SparcISA
-{
-
-Addr
-vtophys(ThreadContext *tc, Addr addr)
-{
- // Here we have many options and are really implementing something like
- // a fill handler to find the address since there isn't a multilevel
- // table for us to walk around.
- //
- // 1. We are currently hyperpriv, return the address unmodified
- // 2. The mmu is off return(ra->pa)
- // 3. We are currently priv, use ctx0* tsbs to find the page
- // 4. We are not priv, use ctxN0* tsbs to find the page
- // For all accesses we check the tlbs first since it's possible that
- // long standing pages (e.g. locked kernel mappings) won't be in the tsb
- uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
-
- bool hpriv = bits(tlbdata,0,0);
- // bool priv = bits(tlbdata,2,2);
- bool addr_mask = bits(tlbdata,3,3);
- bool data_real = !bits(tlbdata,5,5);
- bool inst_real = !bits(tlbdata,4,4);
- bool ctx_zero = bits(tlbdata,18,16) > 0;
- int part_id = bits(tlbdata,15,8);
- int pri_context = bits(tlbdata,47,32);
- // int sec_context = bits(tlbdata,63,48);
-
- PortProxy &mem = tc->getPhysProxy();
- TLB* itb = dynamic_cast<TLB *>(tc->getITBPtr());
- TLB* dtb = dynamic_cast<TLB *>(tc->getDTBPtr());
- TlbEntry* tbe;
- PageTableEntry pte;
- Addr tsbs[4];
- Addr va_tag;
- TteTag ttetag;
-
- if (hpriv)
- return addr;
-
- if (addr_mask)
- addr = addr & VAddrAMask;
-
- tbe = dtb->lookup(addr, part_id, data_real, ctx_zero ? 0 : pri_context ,
- false);
- if (tbe)
- goto foundtbe;
-
- tbe = itb->lookup(addr, part_id, inst_real, ctx_zero ? 0 : pri_context,
- false);
- if (tbe)
- goto foundtbe;
-
- // We didn't find it in the tlbs, so lets look at the TSBs
- dtb->GetTsbPtr(tc, addr, ctx_zero ? 0 : pri_context, tsbs);
- va_tag = bits(addr, 63, 22);
- for (int x = 0; x < 4; x++) {
- ttetag = betoh(mem.read<uint64_t>(tsbs[x]));
- if (ttetag.valid() && ttetag.va() == va_tag) {
- uint64_t entry = mem.read<uint64_t>(tsbs[x]) + sizeof(uint64_t);
- // I think it's sun4v at least!
- pte.populate(betoh(entry), PageTableEntry::sun4v);
- DPRINTF(VtoPhys, "Virtual(%#x)->Physical(%#x) found in TTE\n",
- addr, pte.translate(addr));
- goto foundpte;
- }
- }
- panic("couldn't translate %#x\n", addr);
-
- foundtbe:
- pte = tbe->pte;
- DPRINTF(VtoPhys, "Virtual(%#x)->Physical(%#x) found in TLB\n", addr,
- pte.translate(addr));
- foundpte:
- return pte.translate(addr);
-}
-
-} // namespace SparcISA
+++ /dev/null
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_SPARC_VTOPHYS_HH__
-#define __ARCH_SPARC_VTOPHYS_HH__
-
-#include "arch/sparc/isa_traits.hh"
-
-class ThreadContext;
-
-namespace SparcISA
-{
-
-Addr vtophys(ThreadContext *tc, Addr vaddr);
-
-}; // namespace SparcISA
-
-#endif // __ARCH_SPARC_VTOPHYS_HH__
-
Source('tlb.cc')
Source('types.cc')
Source('utility.cc')
- Source('vtophys.cc')
SimObject('X86FsWorkload.py')
SimObject('X86ISA.py')
#include "arch/x86/linux/fs_workload.hh"
-#include "arch/vtophys.hh"
#include "arch/x86/isa_traits.hh"
#include "arch/x86/regs/int.hh"
#include "base/trace.hh"
#include "arch/x86/faults.hh"
#include "arch/x86/pagetable.hh"
#include "arch/x86/tlb.hh"
-#include "arch/x86/vtophys.hh"
#include "base/bitfield.hh"
#include "base/trie.hh"
#include "cpu/base.hh"
#include <string>
-#include "arch/vtophys.hh"
#include "arch/x86/pagetable_walker.hh"
#include "arch/x86/process.hh"
#include "arch/x86/regs/int.hh"
#include <string>
#include "arch/x86/isa_traits.hh"
-#include "arch/x86/vtophys.hh"
#include "base/bitfield.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
+++ /dev/null
-/*
- * Copyright (c) 2007 The Hewlett-Packard Development Company
- * All rights reserved.
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "arch/x86/vtophys.hh"
-
-#include <string>
-
-#include "arch/x86/pagetable_walker.hh"
-#include "arch/x86/tlb.hh"
-#include "base/trace.hh"
-#include "cpu/thread_context.hh"
-#include "debug/VtoPhys.hh"
-
-using namespace std;
-
-Addr
-X86ISA::vtophys(ThreadContext *tc, Addr vaddr)
-{
- Walker *walker = dynamic_cast<TLB *>(tc->getDTBPtr())->getWalker();
- unsigned logBytes;
- Addr addr = vaddr;
- Fault fault = walker->startFunctional(
- tc, addr, logBytes, BaseTLB::Read);
- if (fault != NoFault)
- panic("vtophys page walk returned fault\n");
- Addr masked_addr = vaddr & mask(logBytes);
- Addr paddr = addr | masked_addr;
- DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
- return paddr;
-}
+++ /dev/null
-/*
- * Copyright (c) 2007 The Hewlett-Packard Development Company
- * All rights reserved.
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __ARCH_X86_VTOPHYS_HH__
-#define __ARCH_X86_VTOPHYS_HH__
-
-#include "base/types.hh"
-
-class ThreadContext;
-
-namespace X86ISA
-{
-
-Addr vtophys(ThreadContext *tc, Addr vaddr);
-
-}
-
-#endif // __ARCH_X86_VTOPHYS_HH__
projects / gem5.git / commitdiff