inteconnect/stream: use PipeValid implementation for Buffer

diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py
index 9f81e76c8fe687b481d729f5224a8afcfc2d2de6..b25a58bfce2d9ae1ece1744cc155f074fd700f54 100644 (file)
--- a/litex/soc/interconnect/stream.py
+++ b/litex/soc/interconnect/stream.py
@@ -592,19 +592,6 @@ class Monitor(Module, AutoCSR):
             underflow_counter = MonitorCounter(reset, latch, ~endpoint.valid & endpoint.ready, self.underflows.status)
             self.submodules += underflow_counter
 
-# Buffer -------------------------------------------------------------------------------------------
-
-class Buffer(PipelinedActor):
-    def __init__(self, layout):
-        self.sink   = Endpoint(layout)
-        self.source = Endpoint(layout)
-        PipelinedActor.__init__(self, 1)
-        self.sync += \
-            If(self.pipe_ce,
-                self.source.payload.eq(self.sink.payload),
-                self.source.param.eq(self.sink.param)
-            )
-
 # Pipe ---------------------------------------------------------------------------------------------
 
 class PipeValid(Module):
@@ -658,6 +645,10 @@ class PipeReady(Module):
             )
         ]
 
+# Buffer -------------------------------------------------------------------------------------------
+
+class Buffer(PipeValid): pass # FIXME: Replace Buffer with PipeValid in codebase?
+
 # Cast ---------------------------------------------------------------------------------------------
 
 class Cast(CombinatorialActor):