We now use a 4-bit writemask for all instruction types, which makes it
easier to write generic helper functions to manipulte writemasks.
NOTE: This is a candidate for the 7.10 branch.
}
code->inst[ip].inst0 |= R500_INST_TEX_SEM_WAIT;
- code->inst[ip].inst0 |= (inst->RGB.WriteMask << 11) | (inst->Alpha.WriteMask << 14);
+ code->inst[ip].inst0 |= (inst->RGB.WriteMask << 11);
+ code->inst[ip].inst0 |= inst->Alpha.WriteMask ? 1 << 14 : 0;
code->inst[ip].inst0 |= (inst->RGB.OutputWriteMask << 15) | (inst->Alpha.OutputWriteMask << 18);
if (inst->Nop) {
code->inst[ip].inst0 |= R500_INST_NOP;
}
if (needalpha) {
- pair->Alpha.WriteMask |= GET_BIT(inst->DstReg.WriteMask, 3);
+ pair->Alpha.WriteMask |= (GET_BIT(inst->DstReg.WriteMask, 3) << 3);
if (pair->Alpha.WriteMask) {
pair->Alpha.DestIndex = inst->DstReg.Index;
}
struct rc_pair_sub_instruction {
unsigned int Opcode:8;
unsigned int DestIndex:RC_REGISTER_INDEX_BITS;
- unsigned int WriteMask:3;
+ unsigned int WriteMask:4;
unsigned int Target:2;
unsigned int OutputWriteMask:3;
unsigned int DepthWriteMask:1;