More accurate CHANGELOG

diff --git a/CHANGELOG b/CHANGELOG
index 6e3faa9ff98a66bf1228926ead26ea67bd2787dc..139f71672b74ef26b2a663169c4b14a99dca34aa 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -17,7 +17,9 @@ Yosys 0.8 .. Yosys 0.8-dev
     - Added "rename -src"
     - Added "equiv_opt" pass
     - Added "read_aiger" frontend
-    - Added "abc9" pass (experimental, accessible using synth_xilinx -abc9 and synth_ice40 -abc9)
+    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
+    - Added "synth_xilinx -abc9" (experimental)
+    - Added "synth_ice40 -abc9" (experimental)
     - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"