[libre-riscv-dev] Debug port (was Re: minimum viable ASIC)
authorwhygee <whygee@f-cpu.org>
Fri, 8 May 2020 15:27:06 +0000 (17:27 +0200)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Fri, 8 May 2020 15:27:08 +0000 (16:27 +0100)
a7/b20094b44be4c1d6bd7f803450990809288fdf [new file with mode: 0644]

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+Subject: [libre-riscv-dev] Debug port (was Re:  minimum viable ASIC)
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