#include "compiler/glsl/ir.h"
#include "brw_fs.h"
-#include "brw_fs_surface_builder.h"
#include "brw_nir.h"
#include "util/u_math.h"
#include "util/bitscan.h"
using namespace brw;
-using namespace brw::surface_access;
void
fs_visitor::emit_nir_code()
cs_prog_data->uses_num_work_groups = true;
- fs_reg surf_index = brw_imm_ud(surface);
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(surface);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(1); /* num components */
/* Read the 3 GLuint components of gl_NumWorkGroups */
for (unsigned i = 0; i < 3; i++) {
- fs_reg read_result =
- emit_untyped_read(bld, surf_index,
- brw_imm_ud(i << 2),
- 1 /* dims */, 1 /* size */,
- BRW_PREDICATE_NONE);
- read_result.type = dest.type;
- bld.MOV(dest, read_result);
- dest = offset(dest, bld, 1);
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = brw_imm_ud(i << 2);
+ bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
+ offset(dest, bld, i), srcs, SURFACE_LOGICAL_NUM_SRCS);
}
break;
}
assert(stage == MESA_SHADER_COMPUTE);
const unsigned bit_size = nir_dest_bit_size(instr->dest);
- fs_reg offset_reg = retype(get_nir_src(instr->src[0]),
- BRW_REGISTER_TYPE_UD);
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GEN7_BTI_SLM);
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[0]);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
/* Make dest unsigned because that's what the temporary will be */
dest.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
/* Read the vector */
if (nir_intrinsic_align(instr) >= 4) {
assert(nir_dest_bit_size(instr->dest) == 32);
- fs_reg read_result = emit_untyped_read(bld, brw_imm_ud(GEN7_BTI_SLM),
- offset_reg, 1 /* dims */,
- instr->num_components,
- BRW_PREDICATE_NONE);
- for (unsigned i = 0; i < instr->num_components; i++)
- bld.MOV(offset(dest, bld, i), offset(read_result, bld, i));
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
+ fs_inst *inst =
+ bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
+ dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
+ inst->size_written = instr->num_components * dispatch_width * 4;
} else {
assert(nir_dest_bit_size(instr->dest) <= 32);
assert(nir_dest_num_components(instr->dest) == 1);
- fs_reg read_result =
- emit_byte_scattered_read(bld, brw_imm_ud(GEN7_BTI_SLM), offset_reg,
- 1 /* dims */, 1, bit_size,
- BRW_PREDICATE_NONE);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size);
+
+ fs_reg read_result = bld.vgrf(BRW_REGISTER_TYPE_UD);
+ bld.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
+ read_result, srcs, SURFACE_LOGICAL_NUM_SRCS);
bld.MOV(dest, read_result);
}
break;
assert(stage == MESA_SHADER_COMPUTE);
const unsigned bit_size = nir_src_bit_size(instr->src[0]);
- fs_reg val_reg = get_nir_src(instr->src[0]);
- fs_reg offset_reg = retype(get_nir_src(instr->src[1]),
- BRW_REGISTER_TYPE_UD);
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GEN7_BTI_SLM);
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[1]);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
- val_reg.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
+ fs_reg data = get_nir_src(instr->src[0]);
+ data.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
assert(nir_intrinsic_write_mask(instr) ==
(1u << instr->num_components) - 1);
if (nir_intrinsic_align(instr) >= 4) {
assert(nir_src_bit_size(instr->src[0]) == 32);
assert(nir_src_num_components(instr->src[0]) <= 4);
- emit_untyped_write(bld, brw_imm_ud(GEN7_BTI_SLM), offset_reg, val_reg,
- 1 /* dims */, instr->num_components,
- BRW_PREDICATE_NONE);
+ srcs[SURFACE_LOGICAL_SRC_DATA] = data;
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
+ bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
+ fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
} else {
assert(nir_src_bit_size(instr->src[0]) <= 32);
assert(nir_src_num_components(instr->src[0]) == 1);
- fs_reg write_src = bld.vgrf(BRW_REGISTER_TYPE_UD);
- bld.MOV(write_src, val_reg);
- emit_byte_scattered_write(bld, brw_imm_ud(GEN7_BTI_SLM), offset_reg,
- write_src, 1 /* dims */, bit_size,
- BRW_PREDICATE_NONE);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size);
+
+ srcs[SURFACE_LOGICAL_SRC_DATA] = bld.vgrf(BRW_REGISTER_TYPE_UD);
+ bld.MOV(srcs[SURFACE_LOGICAL_SRC_DATA], data);
+
+ bld.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
+ fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
}
break;
}
brw_imm_ud(stage_prog_data->binding_table.ssbo_start));
}
- return surf_index;
+ return bld.emit_uniformize(surf_index);
}
static unsigned
/* Get some metadata from the image intrinsic. */
const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
- const unsigned dims = image_intrinsic_coord_components(instr);
const GLenum format = nir_intrinsic_format(instr);
- const unsigned dest_components = nir_intrinsic_dest_components(instr);
- /* Get the arguments of the image intrinsic. */
- const fs_reg image = get_nir_image_intrinsic_image(bld, instr);
- const fs_reg coords = retype(get_nir_src(instr->src[1]),
- BRW_REGISTER_TYPE_UD);
- fs_reg tmp;
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] =
+ get_nir_image_intrinsic_image(bld, instr);
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[1]);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] =
+ brw_imm_ud(image_intrinsic_coord_components(instr));
/* Emit an image load, store or atomic op. */
if (instr->intrinsic == nir_intrinsic_image_load) {
- tmp = emit_typed_read(bld, image, coords, dims,
- instr->num_components);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
+ fs_inst *inst =
+ bld.emit(SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,
+ dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
+ inst->size_written = instr->num_components * dispatch_width * 4;
} else if (instr->intrinsic == nir_intrinsic_image_store) {
- const fs_reg src0 = get_nir_src(instr->src[3]);
- emit_typed_write(bld, image, coords, src0, dims,
- instr->num_components);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
+ srcs[SURFACE_LOGICAL_SRC_DATA] = get_nir_src(instr->src[3]);
+ bld.emit(SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
+ fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
} else {
int op;
unsigned num_srcs = info->num_srcs;
unreachable("Not reachable.");
}
- const fs_reg src0 = (num_srcs >= 4 ?
- get_nir_src(instr->src[3]) : fs_reg());
- const fs_reg src1 = (num_srcs >= 5 ?
- get_nir_src(instr->src[4]) : fs_reg());
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(op);
- tmp = emit_typed_atomic(bld, image, coords, src0, src1, dims, 1, op);
- }
+ fs_reg data;
+ if (num_srcs >= 4)
+ data = get_nir_src(instr->src[3]);
+ if (num_srcs >= 5) {
+ fs_reg tmp = bld.vgrf(data.type, 2);
+ fs_reg sources[2] = { data, get_nir_src(instr->src[4]) };
+ bld.LOAD_PAYLOAD(tmp, sources, 2, 0);
+ data = tmp;
+ }
+ srcs[SURFACE_LOGICAL_SRC_DATA] = data;
- /* Assign the result. */
- for (unsigned c = 0; c < dest_components; ++c) {
- bld.MOV(offset(retype(dest, tmp.type), bld, c),
- offset(tmp, bld, c));
+ bld.emit(SHADER_OPCODE_TYPED_ATOMIC_LOGICAL,
+ dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
}
break;
}
}
case nir_intrinsic_image_load_raw_intel: {
- const fs_reg image = get_nir_image_intrinsic_image(bld, instr);
- const fs_reg addr = retype(get_nir_src(instr->src[1]),
- BRW_REGISTER_TYPE_UD);
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] =
+ get_nir_image_intrinsic_image(bld, instr);
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[1]);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
- fs_reg tmp = emit_untyped_read(bld, image, addr, 1,
- instr->num_components);
-
- for (unsigned c = 0; c < instr->num_components; ++c) {
- bld.MOV(offset(retype(dest, tmp.type), bld, c),
- offset(tmp, bld, c));
- }
+ fs_inst *inst =
+ bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
+ dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
+ inst->size_written = instr->num_components * dispatch_width * 4;
break;
}
case nir_intrinsic_image_store_raw_intel: {
- const fs_reg image = get_nir_image_intrinsic_image(bld, instr);
- const fs_reg addr = retype(get_nir_src(instr->src[1]),
- BRW_REGISTER_TYPE_UD);
- const fs_reg data = retype(get_nir_src(instr->src[2]),
- BRW_REGISTER_TYPE_UD);
-
if (stage == MESA_SHADER_FRAGMENT)
brw_wm_prog_data(prog_data)->has_side_effects = true;
- emit_untyped_write(bld, image, addr, data, 1,
- instr->num_components);
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] =
+ get_nir_image_intrinsic_image(bld, instr);
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[1]);
+ srcs[SURFACE_LOGICAL_SRC_DATA] = get_nir_src(instr->src[2]);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
+
+ bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
+ fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
break;
}
assert(devinfo->gen >= 7);
const unsigned bit_size = nir_dest_bit_size(instr->dest);
- fs_reg surf_index = get_nir_ssbo_intrinsic_index(bld, instr);
- fs_reg offset_reg = retype(get_nir_src(instr->src[1]),
- BRW_REGISTER_TYPE_UD);
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] =
+ get_nir_ssbo_intrinsic_index(bld, instr);
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[1]);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
/* Make dest unsigned because that's what the temporary will be */
dest.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
/* Read the vector */
if (nir_intrinsic_align(instr) >= 4) {
assert(nir_dest_bit_size(instr->dest) == 32);
- fs_reg read_result = emit_untyped_read(bld, surf_index, offset_reg,
- 1 /* dims */,
- instr->num_components,
- BRW_PREDICATE_NONE);
- for (unsigned i = 0; i < instr->num_components; i++)
- bld.MOV(offset(dest, bld, i), offset(read_result, bld, i));
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
+ fs_inst *inst =
+ bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
+ dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
+ inst->size_written = instr->num_components * dispatch_width * 4;
} else {
assert(nir_dest_bit_size(instr->dest) <= 32);
assert(nir_dest_num_components(instr->dest) == 1);
- fs_reg read_result =
- emit_byte_scattered_read(bld, surf_index, offset_reg,
- 1 /* dims */, 1, bit_size,
- BRW_PREDICATE_NONE);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size);
+
+ fs_reg read_result = bld.vgrf(BRW_REGISTER_TYPE_UD);
+ bld.emit(SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
+ read_result, srcs, SURFACE_LOGICAL_NUM_SRCS);
bld.MOV(dest, read_result);
}
break;
brw_wm_prog_data(prog_data)->has_side_effects = true;
const unsigned bit_size = nir_src_bit_size(instr->src[0]);
- fs_reg val_reg = get_nir_src(instr->src[0]);
- fs_reg surf_index = get_nir_ssbo_intrinsic_index(bld, instr);
- fs_reg offset_reg = retype(get_nir_src(instr->src[2]),
- BRW_REGISTER_TYPE_UD);
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] =
+ get_nir_ssbo_intrinsic_index(bld, instr);
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[2]);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
- val_reg.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
+ fs_reg data = get_nir_src(instr->src[0]);
+ data.type = brw_reg_type_from_bit_size(bit_size, BRW_REGISTER_TYPE_UD);
assert(nir_intrinsic_write_mask(instr) ==
(1u << instr->num_components) - 1);
if (nir_intrinsic_align(instr) >= 4) {
assert(nir_src_bit_size(instr->src[0]) == 32);
assert(nir_src_num_components(instr->src[0]) <= 4);
- emit_untyped_write(bld, surf_index, offset_reg, val_reg,
- 1 /* dims */, instr->num_components,
- BRW_PREDICATE_NONE);
+ srcs[SURFACE_LOGICAL_SRC_DATA] = data;
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(instr->num_components);
+ bld.emit(SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
+ fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
} else {
assert(nir_src_bit_size(instr->src[0]) <= 32);
assert(nir_src_num_components(instr->src[0]) == 1);
- fs_reg write_src = bld.vgrf(BRW_REGISTER_TYPE_UD);
- bld.MOV(write_src, val_reg);
- emit_byte_scattered_write(bld, surf_index, offset_reg,
- write_src, 1 /* dims */, bit_size,
- BRW_PREDICATE_NONE);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(bit_size);
+
+ srcs[SURFACE_LOGICAL_SRC_DATA] = bld.vgrf(BRW_REGISTER_TYPE_UD);
+ bld.MOV(srcs[SURFACE_LOGICAL_SRC_DATA], data);
+
+ bld.emit(SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
+ fs_reg(), srcs, SURFACE_LOGICAL_NUM_SRCS);
}
break;
}
if (nir_intrinsic_infos[instr->intrinsic].has_dest)
dest = get_nir_dest(instr->dest);
- fs_reg surface = get_nir_ssbo_intrinsic_index(bld, instr);
- fs_reg offset = get_nir_src(instr->src[1]);
- fs_reg data1;
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] = get_nir_ssbo_intrinsic_index(bld, instr);
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[1]);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(op);
+
+ fs_reg data;
if (op != BRW_AOP_INC && op != BRW_AOP_DEC && op != BRW_AOP_PREDEC)
- data1 = get_nir_src(instr->src[2]);
- fs_reg data2;
- if (op == BRW_AOP_CMPWR)
- data2 = get_nir_src(instr->src[3]);
+ data = get_nir_src(instr->src[2]);
+
+ if (op == BRW_AOP_CMPWR) {
+ fs_reg tmp = bld.vgrf(data.type, 2);
+ fs_reg sources[2] = { data, get_nir_src(instr->src[3]) };
+ bld.LOAD_PAYLOAD(tmp, sources, 2, 0);
+ data = tmp;
+ }
+ srcs[SURFACE_LOGICAL_SRC_DATA] = data;
/* Emit the actual atomic operation */
- fs_reg atomic_result = emit_untyped_atomic(bld, surface, offset,
- data1, data2,
- 1 /* dims */, 1 /* rsize */,
- op,
- BRW_PREDICATE_NONE);
- dest.type = atomic_result.type;
- bld.MOV(dest, atomic_result);
+ bld.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
+ dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
}
void
if (nir_intrinsic_infos[instr->intrinsic].has_dest)
dest = get_nir_dest(instr->dest);
- fs_reg surface = get_nir_ssbo_intrinsic_index(bld, instr);
- fs_reg offset = get_nir_src(instr->src[1]);
- fs_reg data1 = get_nir_src(instr->src[2]);
- fs_reg data2;
- if (op == BRW_AOP_FCMPWR)
- data2 = get_nir_src(instr->src[3]);
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] = get_nir_ssbo_intrinsic_index(bld, instr);
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = get_nir_src(instr->src[1]);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(op);
+
+ fs_reg data = get_nir_src(instr->src[2]);
+ if (op == BRW_AOP_FCMPWR) {
+ fs_reg tmp = bld.vgrf(data.type, 2);
+ fs_reg sources[2] = { data, get_nir_src(instr->src[3]) };
+ bld.LOAD_PAYLOAD(tmp, sources, 2, 0);
+ data = tmp;
+ }
+ srcs[SURFACE_LOGICAL_SRC_DATA] = data;
/* Emit the actual atomic operation */
- fs_reg atomic_result = emit_untyped_atomic_float(bld, surface, offset,
- data1, data2,
- 1 /* dims */, 1 /* rsize */,
- op,
- BRW_PREDICATE_NONE);
- dest.type = atomic_result.type;
- bld.MOV(dest, atomic_result);
+ bld.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL,
+ dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
}
void
if (nir_intrinsic_infos[instr->intrinsic].has_dest)
dest = get_nir_dest(instr->dest);
- fs_reg surface = brw_imm_ud(GEN7_BTI_SLM);
- fs_reg offset;
- fs_reg data1;
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GEN7_BTI_SLM);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(op);
+
+ fs_reg data;
if (op != BRW_AOP_INC && op != BRW_AOP_DEC && op != BRW_AOP_PREDEC)
- data1 = get_nir_src(instr->src[1]);
- fs_reg data2;
- if (op == BRW_AOP_CMPWR)
- data2 = get_nir_src(instr->src[2]);
+ data = get_nir_src(instr->src[1]);
+ if (op == BRW_AOP_CMPWR) {
+ fs_reg tmp = bld.vgrf(data.type, 2);
+ fs_reg sources[2] = { data, get_nir_src(instr->src[2]) };
+ bld.LOAD_PAYLOAD(tmp, sources, 2, 0);
+ data = tmp;
+ }
+ srcs[SURFACE_LOGICAL_SRC_DATA] = data;
/* Get the offset */
if (nir_src_is_const(instr->src[0])) {
- offset = brw_imm_ud(instr->const_index[0] +
- nir_src_as_uint(instr->src[0]));
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] =
+ brw_imm_ud(instr->const_index[0] + nir_src_as_uint(instr->src[0]));
} else {
- offset = vgrf(glsl_type::uint_type);
- bld.ADD(offset,
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = vgrf(glsl_type::uint_type);
+ bld.ADD(srcs[SURFACE_LOGICAL_SRC_ADDRESS],
retype(get_nir_src(instr->src[0]), BRW_REGISTER_TYPE_UD),
brw_imm_ud(instr->const_index[0]));
}
/* Emit the actual atomic operation operation */
- fs_reg atomic_result = emit_untyped_atomic(bld, surface, offset,
- data1, data2,
- 1 /* dims */, 1 /* rsize */,
- op,
- BRW_PREDICATE_NONE);
- dest.type = atomic_result.type;
- bld.MOV(dest, atomic_result);
+ bld.emit(SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
+ dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
}
void
if (nir_intrinsic_infos[instr->intrinsic].has_dest)
dest = get_nir_dest(instr->dest);
- fs_reg surface = brw_imm_ud(GEN7_BTI_SLM);
- fs_reg offset;
- fs_reg data1 = get_nir_src(instr->src[1]);
- fs_reg data2;
- if (op == BRW_AOP_FCMPWR)
- data2 = get_nir_src(instr->src[2]);
+ fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
+ srcs[SURFACE_LOGICAL_SRC_SURFACE] = brw_imm_ud(GEN7_BTI_SLM);
+ srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(1);
+ srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(op);
+
+ fs_reg data = get_nir_src(instr->src[1]);
+ if (op == BRW_AOP_FCMPWR) {
+ fs_reg tmp = bld.vgrf(data.type, 2);
+ fs_reg sources[2] = { data, get_nir_src(instr->src[2]) };
+ bld.LOAD_PAYLOAD(tmp, sources, 2, 0);
+ data = tmp;
+ }
+ srcs[SURFACE_LOGICAL_SRC_DATA] = data;
/* Get the offset */
if (nir_src_is_const(instr->src[0])) {
- offset = brw_imm_ud(instr->const_index[0] +
- nir_src_as_uint(instr->src[0]));
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] =
+ brw_imm_ud(instr->const_index[0] + nir_src_as_uint(instr->src[0]));
} else {
- offset = vgrf(glsl_type::uint_type);
- bld.ADD(offset,
- retype(get_nir_src(instr->src[0]), BRW_REGISTER_TYPE_UD),
- brw_imm_ud(instr->const_index[0]));
+ srcs[SURFACE_LOGICAL_SRC_ADDRESS] = vgrf(glsl_type::uint_type);
+ bld.ADD(srcs[SURFACE_LOGICAL_SRC_ADDRESS],
+ retype(get_nir_src(instr->src[0]), BRW_REGISTER_TYPE_UD),
+ brw_imm_ud(instr->const_index[0]));
}
/* Emit the actual atomic operation operation */
- fs_reg atomic_result = emit_untyped_atomic_float(bld, surface, offset,
- data1, data2,
- 1 /* dims */, 1 /* rsize */,
- op,
- BRW_PREDICATE_NONE);
- dest.type = atomic_result.type;
- bld.MOV(dest, atomic_result);
+ bld.emit(SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL,
+ dest, srcs, SURFACE_LOGICAL_NUM_SRCS);
}
void
+++ /dev/null
-/*
- * Copyright © 2013-2015 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#include "isl/isl.h"
-#include "brw_fs_surface_builder.h"
-#include "brw_fs.h"
-
-using namespace brw;
-
-namespace brw {
- namespace surface_access {
- namespace {
- /**
- * Generate a logical send opcode for a surface message and return
- * the result.
- */
- fs_reg
- emit_send(const fs_builder &bld, enum opcode opcode,
- const fs_reg &addr, const fs_reg &src, const fs_reg &surface,
- unsigned dims, unsigned arg, unsigned rsize,
- brw_predicate pred = BRW_PREDICATE_NONE)
- {
- /* Reduce the dynamically uniform surface index to a single
- * scalar.
- */
- const fs_reg usurface = bld.emit_uniformize(surface);
- fs_reg srcs[SURFACE_LOGICAL_NUM_SRCS];
- srcs[SURFACE_LOGICAL_SRC_ADDRESS] = addr;
- srcs[SURFACE_LOGICAL_SRC_DATA] = src;
- srcs[SURFACE_LOGICAL_SRC_SURFACE] = usurface;
- srcs[SURFACE_LOGICAL_SRC_IMM_DIMS] = brw_imm_ud(dims);
- srcs[SURFACE_LOGICAL_SRC_IMM_ARG] = brw_imm_ud(arg);
-
- const fs_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD, rsize);
- fs_inst *inst = bld.emit(opcode, dst, srcs, ARRAY_SIZE(srcs));
-
- inst->size_written = rsize * dst.component_size(inst->exec_size);
- inst->predicate = pred;
- return dst;
- }
- }
-
- /**
- * Emit an untyped surface read opcode. \p dims determines the number
- * of components of the address and \p size the number of components of
- * the returned value.
- */
- fs_reg
- emit_untyped_read(const fs_builder &bld,
- const fs_reg &surface, const fs_reg &addr,
- unsigned dims, unsigned size,
- brw_predicate pred)
- {
- return emit_send(bld, SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL,
- addr, fs_reg(), surface, dims, size, size, pred);
- }
-
- /**
- * Emit an untyped surface write opcode. \p dims determines the number
- * of components of the address and \p size the number of components of
- * the argument.
- */
- void
- emit_untyped_write(const fs_builder &bld, const fs_reg &surface,
- const fs_reg &addr, const fs_reg &src,
- unsigned dims, unsigned size,
- brw_predicate pred)
- {
- emit_send(bld, SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL,
- addr, src, surface, dims, size, 0, pred);
- }
-
- /**
- * Emit an untyped surface atomic opcode. \p dims determines the number
- * of components of the address and \p rsize the number of components of
- * the returned value (either zero or one).
- */
- fs_reg
- emit_untyped_atomic(const fs_builder &bld,
- const fs_reg &surface, const fs_reg &addr,
- const fs_reg &src0, const fs_reg &src1,
- unsigned dims, unsigned rsize, unsigned op,
- brw_predicate pred)
- {
- /* FINISHME: Factor out this frequently recurring pattern into a
- * helper function.
- */
- const unsigned n = (src0.file != BAD_FILE) + (src1.file != BAD_FILE);
- const fs_reg srcs[] = { src0, src1 };
- const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, n);
- bld.LOAD_PAYLOAD(tmp, srcs, n, 0);
-
- return emit_send(bld, SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL,
- addr, tmp, surface, dims, op, rsize, pred);
- }
-
- /**
- * Emit an untyped surface atomic float opcode. \p dims determines the
- * number of components of the address and \p rsize the number of
- * components of the returned value (either zero or one).
- */
- fs_reg
- emit_untyped_atomic_float(const fs_builder &bld,
- const fs_reg &surface, const fs_reg &addr,
- const fs_reg &src0, const fs_reg &src1,
- unsigned dims, unsigned rsize, unsigned op,
- brw_predicate pred)
- {
- /* FINISHME: Factor out this frequently recurring pattern into a
- * helper function.
- */
- const unsigned n = (src0.file != BAD_FILE) + (src1.file != BAD_FILE);
- const fs_reg srcs[] = { src0, src1 };
- const fs_reg tmp = bld.vgrf(src0.type, n);
- bld.LOAD_PAYLOAD(tmp, srcs, n, 0);
-
- return emit_send(bld, SHADER_OPCODE_UNTYPED_ATOMIC_FLOAT_LOGICAL,
- addr, tmp, surface, dims, op, rsize, pred);
- }
-
- /**
- * Emit a typed surface read opcode. \p dims determines the number of
- * components of the address and \p size the number of components of the
- * returned value.
- */
- fs_reg
- emit_typed_read(const fs_builder &bld, const fs_reg &surface,
- const fs_reg &addr, unsigned dims, unsigned size)
- {
- return emit_send(bld, SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL,
- addr, fs_reg(), surface, dims, size, size);
- }
-
- /**
- * Emit a typed surface write opcode. \p dims determines the number of
- * components of the address and \p size the number of components of the
- * argument.
- */
- void
- emit_typed_write(const fs_builder &bld, const fs_reg &surface,
- const fs_reg &addr, const fs_reg &src,
- unsigned dims, unsigned size)
- {
- emit_send(bld, SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL,
- addr, src, surface, dims, size, 0);
- }
-
- /**
- * Emit a typed surface atomic opcode. \p dims determines the number of
- * components of the address and \p rsize the number of components of
- * the returned value (either zero or one).
- */
- fs_reg
- emit_typed_atomic(const fs_builder &bld, const fs_reg &surface,
- const fs_reg &addr,
- const fs_reg &src0, const fs_reg &src1,
- unsigned dims, unsigned rsize, unsigned op,
- brw_predicate pred)
- {
- /* FINISHME: Factor out this frequently recurring pattern into a
- * helper function.
- */
- const unsigned n = (src0.file != BAD_FILE) + (src1.file != BAD_FILE);
- const fs_reg srcs[] = { src0, src1 };
- const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, n);
- bld.LOAD_PAYLOAD(tmp, srcs, n, 0);
-
- return emit_send(bld, SHADER_OPCODE_TYPED_ATOMIC_LOGICAL,
- addr, tmp, surface, dims, op, rsize);
- }
-
- fs_reg
- emit_byte_scattered_read(const fs_builder &bld,
- const fs_reg &surface, const fs_reg &addr,
- unsigned dims, unsigned size,
- unsigned bit_size, brw_predicate pred)
- {
- return emit_send(bld, SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL,
- addr, fs_reg(), surface, dims, bit_size, size, pred);
- }
-
- void
- emit_byte_scattered_write(const fs_builder &bld, const fs_reg &surface,
- const fs_reg &addr, const fs_reg &src,
- unsigned dims,
- unsigned bit_size, brw_predicate pred)
- {
- emit_send(bld, SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
- addr, src, surface, dims, bit_size, 0, pred);
- }
- }
-}
projects / mesa.git / commitdiff