struct radeon_bo *bo,
intptr_t offset,
gl_format mesa_format,
+ unsigned pitch,
unsigned width,
unsigned height)
{
r300_emit_cb_setup(r300, bo, offset, mesa_format,
_mesa_get_format_bytes(mesa_format),
- _mesa_format_row_stride(mesa_format, width));
+ _mesa_format_row_stride(mesa_format, pitch));
BEGIN_BATCH_NO_AUTOSTATE(5);
OUT_BATCH_REGSEQ(R300_SC_SCISSORS_TL, 2);
struct radeon_bo *dst_bo,
intptr_t dst_offset,
gl_format dst_mesaformat,
+ unsigned dst_pitch,
unsigned dst_width,
unsigned dst_height)
{
- //assert(src_width == dst_width);
- //assert(src_height == dst_height);
-
if (src_bo == dst_bo) {
return GL_FALSE;
}
- //return GL_FALSE;
-
if (0) {
fprintf(stderr, "src: width %d, height %d, pitch %d vs %d, format %s\n",
src_width, src_height, src_pitch,
emit_pvs_setup(r300, r300->blit.vp_code.body.d, 2);
emit_vap_setup(r300, dst_width, dst_height);
- emit_cb_setup(r300, dst_bo, dst_offset, dst_mesaformat, dst_width, dst_height);
+ emit_cb_setup(r300, dst_bo, dst_offset, dst_mesaformat, dst_pitch, dst_width, dst_height);
emit_draw_packet(r300, dst_width, dst_height);
r300EmitCacheFlush(r300);
radeonFlush(r300->radeon.glCtx);
- //r300ResetHwState(r300);
return GL_TRUE;
}
\ No newline at end of file
assert(timg->mt->bo);
assert(timg->base.Width >= dstx + width);
assert(timg->base.Height >= dsty + height);
- //assert(tobj->mt == timg->mt);
intptr_t src_offset = rrb->draw_offset + x * rrb->cpp + y * rrb->pitch;
intptr_t dst_offset = radeon_miptree_image_offset(timg->mt, _mesa_tex_target_to_face(target), level);
/* blit from src buffer to texture */
return r300_blit(r300, rrb->bo, src_offset, rrb->base.Format, rrb->pitch,
rrb->base.Width, rrb->base.Height, timg->mt->bo ? timg->mt->bo : timg->bo, dst_offset,
- timg->base.TexFormat, width, height);
+ timg->base.TexFormat, timg->base.Width, width, height);
}
static void