r600: move non-surface related cb state to general state

diff --git a/src/mesa/drivers/dri/r600/r700_chip.c b/src/mesa/drivers/dri/r600/r700_chip.c
index 083b9973ac1d442719bb29f25a6703adcb751a67..9bb3fcd68fdae6ea4767a7d1f55e06c161801e25 100644 (file)
--- a/src/mesa/drivers/dri/r600/r700_chip.c
+++ b/src/mesa/drivers/dri/r600/r700_chip.c
@@ -487,6 +487,18 @@ GLboolean r700SendContextStates(context_t *context)
     for(ui = 0; ui < R700_MAX_SHADER_EXPORTS; ui++)
            R600_OUT_BATCH(r700->SPI_PS_INPUT_CNTL[ui].u32All);
     END_BATCH();
+
+    if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
+           for (ui = 0; ui < R700_MAX_RENDER_TARGETS; ui++) {
+                   if (r700->render_target[ui].enabled) {
+                           BEGIN_BATCH_NO_AUTOSTATE(3);
+                           R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * ui),
+                                                 r700->render_target[ui].CB_BLEND0_CONTROL.u32All);
+                           END_BATCH();
+                   }
+           }
+    }
+
     COMMIT_BATCH();
 
     return GL_TRUE;
@@ -567,12 +579,6 @@ GLboolean r700SendRenderTargetState(context_t *context, int id)
        R600_OUT_BATCH_REGVAL(CB_COLOR0_MASK + (4 * id), r700->render_target[id].CB_COLOR0_MASK.u32All);
         END_BATCH();
 
-       if (context->radeon.radeonScreen->chip_family > CHIP_FAMILY_R600) {
-               BEGIN_BATCH_NO_AUTOSTATE(3);
-               R600_OUT_BATCH_REGVAL(CB_BLEND0_CONTROL + (4 * id), r700->render_target[id].CB_BLEND0_CONTROL.u32All);
-               END_BATCH();
-       }
-
        COMMIT_BATCH();
 
        r700SyncSurf(context, rrb->bo, 0, RADEON_GEM_DOMAIN_VRAM,