build/xilinx/XilinxMultiRegImpl: fix n=0 case

diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py
index dffe5872c60b355844fac8546feac3a9d778caf7..8848d85c549c9c4f0ef3d623bea238bc4c0c0e63 100644 (file)
--- a/litex/build/xilinx/common.py
+++ b/litex/build/xilinx/common.py
@@ -78,7 +78,8 @@ class XilinxMultiRegImpl(MultiRegImpl):
         if not hasattr(i, "attr"):
             i0, i = i, Signal()
             self.comb += i.eq(i0)
-        self.regs[0].attr.add("mr_ff")
+        if len(self.regs):
+            self.regs[0].attr.add("mr_ff")
         for r in self.regs:
             r.attr.add("async_reg")
             r.attr.add("no_shreg_extract")