sim: VCD generation

diff --git a/examples/basic_sim.py b/examples/basic_sim.py
index 55db802cd0f720fbd5568cc1333c39b60a11de7b..1786072350f3254d90d1780a59592c1324feee26 100644 (file)
--- a/examples/basic_sim.py
+++ b/examples/basic_sim.py
@@ -1,5 +1,5 @@
 from migen.fhdl.structure import *
-from migen.sim.generic import Simulator
+from migen.sim.generic import Simulator, TopLevel
 from migen.sim.icarus import Runner
 
 class Counter:
@@ -21,7 +21,7 @@ class Counter:
 
 def main():
        dut = Counter()
-       sim = Simulator(dut.get_fragment(), Runner())
+       sim = Simulator(dut.get_fragment(), Runner(), TopLevel("my.vcd"))
        sim.run(10)
 
 main()

diff --git a/migen/sim/generic.py b/migen/sim/generic.py
index db9978a6fc36b4b3a60c10352004b93eb4b2a86a..79607b24fe9e2514899552594e4cf2ca0d6e42f3 100644 (file)
--- a/migen/sim/generic.py
+++ b/migen/sim/generic.py
@@ -3,8 +3,11 @@ from migen.fhdl import verilog
 from migen.sim.ipc import *
 
 class TopLevel:
-       def __init__(self, top_name="top", dut_type="dut", dut_name="dut", clk_name="sys_clk", 
-         clk_period=10, rst_name="sys_rst"):
+       def __init__(self, vcd_name=None, vcd_level=1,
+         top_name="top", dut_type="dut", dut_name="dut",
+         clk_name="sys_clk", clk_period=10, rst_name="sys_rst"):
+               self.vcd_name = vcd_name
+               self.vcd_level = vcd_level
                self.top_name = top_name
                self.dut_type = dut_type
                self.dut_name = dut_name
@@ -13,7 +16,9 @@ class TopLevel:
                self.rst_name = rst_name
        
        def get(self, sockaddr):
-               template = """module {top_name}();
+               template1 = """`timescale 1ns / 1ps
+
+module {top_name}();
 
 reg {clk_name};
 reg {rst_name};
@@ -38,16 +43,26 @@ end
 
 initial $migensim_connect("{sockaddr}");
 always @(posedge {clk_name}) $migensim_tick;
-
-endmodule
 """
-               return template.format(top_name=self.top_name,
+               template2 = """
+initial begin
+       $dumpfile("{vcd_name}");
+       $dumpvars({vcd_level}, {dut_name});
+end
+"""
+               r = template1.format(top_name=self.top_name,
                        dut_type=self.dut_type,
                        dut_name=self.dut_name,
                        clk_name=self.clk_name,
                        hclk_period=str(self.clk_period/2),
                        rst_name=self.rst_name,
                        sockaddr=sockaddr)
+               if self.vcd_name is not None:
+                       r += template2.format(vcd_name=self.vcd_name,
+                               vcd_level=str(self.vcd_level),
+                               dut_name=self.dut_name)
+               r += "\nendmodule"
+               return r
 
 class Simulator:
        def __init__(self, fragment, sim_runner, top_level=None, sockaddr="simsocket"):