It needs be set to R/W only when using certain messages via DP render cache.
Since we only use RT wrties with the render cache, we never need to set it.
}
ilo_gpe_init_view_surface_for_buffer(builder->dev, buf, bo_offset,
- so->buffer_size, struct_size, elem_format, false, true, &surf);
+ so->buffer_size, struct_size, elem_format, false, &surf);
return gen6_SURFACE_STATE(builder, &surf, false);
}
unsigned offset, unsigned size,
unsigned struct_size,
enum pipe_format elem_format,
- bool is_rt, bool render_cache_rw,
+ bool is_rt,
struct ilo_view_surface *surf);
void
unsigned offset, unsigned size,
unsigned struct_size,
enum pipe_format elem_format,
- bool is_rt, bool render_cache_rw,
- struct ilo_view_surface *surf)
+ bool is_rt, struct ilo_view_surface *surf)
{
const int elem_size = util_format_get_blocksize(elem_format);
int width, height, depth, pitch;
dw[0] = GEN6_SURFTYPE_BUFFER << GEN6_SURFACE_DW0_TYPE__SHIFT |
surface_format << GEN6_SURFACE_DW0_FORMAT__SHIFT;
- if (render_cache_rw)
- dw[0] |= GEN6_SURFACE_DW0_RENDER_CACHE_RW;
dw[1] = offset;
GEN6_SURFACE_DW0_CUBE_FACE_ENABLES__MASK;
}
- if (is_rt)
- dw[0] |= GEN6_SURFACE_DW0_RENDER_CACHE_RW;
-
dw[1] = 0;
dw[2] = (height - 1) << GEN6_SURFACE_DW2_HEIGHT__SHIFT |
unsigned offset, unsigned size,
unsigned struct_size,
enum pipe_format elem_format,
- bool is_rt, bool render_cache_rw,
- struct ilo_view_surface *surf)
+ bool is_rt, struct ilo_view_surface *surf)
{
const bool typed = (elem_format != PIPE_FORMAT_NONE);
const bool structured = (!typed && struct_size > 1);
dw[0] = surface_type << GEN7_SURFACE_DW0_TYPE__SHIFT |
surface_format << GEN7_SURFACE_DW0_FORMAT__SHIFT;
- if (render_cache_rw)
- dw[0] |= GEN7_SURFACE_DW0_RENDER_CACHE_RW;
if (ilo_dev_gen(dev) >= ILO_GEN(8)) {
dw[8] = offset;
dw[0] |= GEN7_SURFACE_DW0_ARYSPC_FULL;
}
- if (is_rt)
- dw[0] |= GEN7_SURFACE_DW0_RENDER_CACHE_RW;
-
if (surface_type == GEN6_SURFTYPE_CUBE && !is_rt)
dw[0] |= GEN7_SURFACE_DW0_CUBE_FACE_ENABLES__MASK;
unsigned offset, unsigned size,
unsigned struct_size,
enum pipe_format elem_format,
- bool is_rt, bool render_cache_rw,
+ bool is_rt,
struct ilo_view_surface *surf)
{
if (ilo_dev_gen(dev) >= ILO_GEN(7)) {
view_init_for_buffer_gen7(dev, buf, offset, size,
- struct_size, elem_format, is_rt, render_cache_rw, surf);
+ struct_size, elem_format, is_rt, surf);
} else {
view_init_for_buffer_gen6(dev, buf, offset, size,
- struct_size, elem_format, is_rt, render_cache_rw, surf);
+ struct_size, elem_format, is_rt, surf);
}
/* do not increment reference count */
session->input->buffer_offset,
session->input->buffer_size,
1, PIPE_FORMAT_NONE,
- false, false, &view);
+ false, &view);
assert(count == 1 && session->input->buffer);
surface_state[base] = gen6_SURFACE_STATE(r->builder, &view, false);
assert(bindings[i].resource->target == PIPE_BUFFER);
ilo_gpe_init_view_surface_for_buffer(r->dev, buf, 0, buf->bo_size,
- 1, PIPE_FORMAT_NONE, true, true, &view);
+ 1, PIPE_FORMAT_NONE, true, &view);
surface_state[i] =
gen6_SURFACE_STATE(r->builder, &view, true);
} else {
ilo_buffer(cbuf->cso[i].resource),
offset, cbuf->cso[i].user_buffer_size,
util_format_get_blocksize(elem_format), elem_format,
- false, false, &cbuf->cso[i].surface);
+ false, &cbuf->cso[i].surface);
ilo->state_vector.dirty |= ILO_DIRTY_CBUF;
}
ilo_buffer(buf[i].buffer),
buf[i].buffer_offset, buf[i].buffer_size,
util_format_get_blocksize(elem_format), elem_format,
- false, false, &cso->surface);
+ false, &cso->surface);
cso->user_buffer = NULL;
cso->user_buffer_size = 0;
ilo_gpe_init_view_surface_for_buffer(dev, ilo_buffer(res),
first_elem * elem_size, num_elems * elem_size,
- elem_size, templ->format, false, false, &view->surface);
+ elem_size, templ->format, false, &view->surface);
}
else {
struct ilo_texture *tex = ilo_texture(res);
/* relax this? */
assert(tex->base.target != PIPE_BUFFER);
- /*
- * classic i965 sets render_cache_rw for constant buffers and sol
- * surfaces but not render buffers. Why?
- */
ilo_gpe_init_view_surface_for_image(dev,
&tex->image, tex->base.target,
templ->format, templ->u.tex.level, 1,