Added english language description, spaces and brackets for ldux instruction

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 2ff1a3b0bd88398f41e3d56519481a0bdfee5af3..5ef607cd4aed734d0e9324bbaf00ea02e611944c 100644 (file)
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -568,6 +568,16 @@ Pseudo-code:
     RT <- MEM(EA, 8)
     RA <- EA
 
+Description:
+
+    Let the effective address (EA) be the sum (RA)+ (RB).
+    The doubleword in storage addressed by EA is loaded
+    into RT.
+
+    EA is placed into register RA.
+
+    If RA=0 or RA=RT, the instruction form is invalid.
+
 Special Registers Altered:
 
     None