radeonsi/gfx10: use the new scan converter when binning is disabled

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index c63837e89fa1a16fc7101b43ff6191aa2c8d1bf8..d04e7e155fce5552187f954ac611b3c7cc65b40d 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -674,6 +674,7 @@ struct si_framebuffer {
        ubyte                           color_is_int10;
        ubyte                           dirty_cbufs;
        ubyte                           dcc_overwrite_combiner_watermark;
+       ubyte                           min_bytes_per_pixel;
        bool                            dirty_zsbuf;
        bool                            any_dst_linear;
        bool                            CB_has_shader_readable_metadata;

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 5220152e62c3dd6c807785dcf06710f5533ac963..1de54885ce7bdd9c6b1a99a7627c9aac9d38dc05 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2977,6 +2977,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
        sctx->framebuffer.CB_has_shader_readable_metadata = false;
        sctx->framebuffer.DB_has_shader_readable_metadata = false;
        sctx->framebuffer.all_DCC_pipe_aligned = true;
+       sctx->framebuffer.min_bytes_per_pixel = 0;
 
        for (i = 0; i < state->nr_cbufs; i++) {
                if (!state->cbufs[i])
@@ -3041,6 +3042,11 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
                        sctx->framebuffer.compressed_cb_mask |= 1 << i;
                        vi_separate_dcc_start_query(sctx, tex);
                }
+
+               /* Update the minimum but don't keep 0. */
+               if (!sctx->framebuffer.min_bytes_per_pixel ||
+                   tex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
+                       sctx->framebuffer.min_bytes_per_pixel = tex->surface.bpe;
        }
 
        /* For optimal DCC performance. */
@@ -3064,6 +3070,11 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
                        sctx->framebuffer.DB_has_shader_readable_metadata = true;
 
                si_context_add_resource_size(sctx, surf->base.texture);
+
+               /* Update the minimum but don't keep 0. */
+               if (!sctx->framebuffer.min_bytes_per_pixel ||
+                   zstex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
+                       sctx->framebuffer.min_bytes_per_pixel = zstex->surface.bpe;
        }
 
        si_update_ps_colorbuf0_slot(sctx);

diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c b/src/gallium/drivers/radeonsi/si_state_binning.c
index 5f280ae7ec1ded77053f52f27e59a3ecff272282..4d884316a612cfab0a2dd1453adf75655cf08c59 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_binning.c
+++ b/src/gallium/drivers/radeonsi/si_state_binning.c
@@ -312,10 +312,32 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
 {
        unsigned initial_cdw = sctx->gfx_cs->current.cdw;
 
-       radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0,
-               SI_TRACKED_PA_SC_BINNER_CNTL_0,
-               S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
-               S_028C44_DISABLE_START_OF_PRIM(1));
+       if (sctx->chip_class >= GFX10) {
+               struct uvec2 bin_size = {};
+               struct uvec2 bin_size_extend = {};
+
+               bin_size.x = 128;
+               bin_size.y = sctx->framebuffer.min_bytes_per_pixel <= 4 ? 128 : 64;
+
+               if (bin_size.x >= 32)
+                       bin_size_extend.x = util_logbase2(bin_size.x) - 5;
+               if (bin_size.y >= 32)
+                       bin_size_extend.y = util_logbase2(bin_size.y) - 5;
+
+               radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0,
+                       SI_TRACKED_PA_SC_BINNER_CNTL_0,
+                       S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
+                       S_028C44_BIN_SIZE_X(bin_size.x == 16) |
+                       S_028C44_BIN_SIZE_Y(bin_size.y == 16) |
+                       S_028C44_BIN_SIZE_X_EXTEND(bin_size_extend.x) |
+                       S_028C44_BIN_SIZE_Y_EXTEND(bin_size_extend.y) |
+                       S_028C44_DISABLE_START_OF_PRIM(1));
+       } else {
+               radeon_opt_set_context_reg(sctx, R_028C44_PA_SC_BINNER_CNTL_0,
+                       SI_TRACKED_PA_SC_BINNER_CNTL_0,
+                       S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
+                       S_028C44_DISABLE_START_OF_PRIM(1));
+       }
 
        unsigned db_dfsm_control = sctx->chip_class >= GFX10 ? R_028038_DB_DFSM_CONTROL
                                                             : R_028060_DB_DFSM_CONTROL;