projects / openpower-isa.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 1a112a5)
fix wrong register in docs
authorJacob Lifshay <programmerjake@gmail.com>
Wed, 27 Sep 2023 01:56:03 +0000 (18:56 -0700)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 22 Dec 2023 19:26:20 +0000 (19:26 +0000)
src/openpower/test/bigint/bigint_cases.py patch | blob | history

diff --git a/src/openpower/test/bigint/bigint_cases.py b/src/openpower/test/bigint/bigint_cases.py
index 98ad5fda53c0319150c7de8e97dea9d1d290fd69..2944ad431e586dca1b572f4be4c1a9c7a3e82e89 100644 (file)
--- a/src/openpower/test/bigint/bigint_cases.py
+++ b/src/openpower/test/bigint/bigint_cases.py
@@ -163,7 +163,7 @@ class SVP64BigIntCases(TestAccumulatorBase):
         0x0000_0000_0500_0000 0x2800_0800_0800_0800 0x1fff_ffff_ffff_ffff
 
         with the 4-bit part that drops out of the 4 LSBs of r16 ending up
-        in r0
+        in r5
         """
         prog = Program(list(SVP64Asm(["sv.dsrd/mrr *16,*16,3,5"])), False)
         gprs = [0] * 32