intel/iris: Always initialize CCS to 0

Previously, we were initializing the CCS to 0xFF for MCS+CCS due to a
misunderstanding of the following lines in the bspec:

    The following are the general SW requirements for MCS buffer clear
    functionality:
        ...
         - If Software wants to enable Color Compression without Fast
           clear, Software needs to initialize MCS with zeros.
         - Lossless compression and CCS initialized to all F (using HW
           Fast Clear or SW direct Clear) on the same surface is not
           supported.

The first line does not refer to the CCS as the comment author supposed
but refers to the MCS as the comment says.  It means that if you want to
use MCS compression without a fast-clear, you should initialize the MCS
to 0x00.  This is because the value 0x00 in the MCS means "all data is
in plane 0" which is a perfectly valid non-fast-clear initialization.
It's also the value the MCS should be in if you do a RECTLIST slow-clear
where the primitive fully covers each pixel such that the same value is
written to all samples.

The second line in the above quote seems to imply that CCS fast-clear is
incompatible with MCS fast-clear.  In particular, MCS+CCS fast-clear
uses a 0xff value in the MCS (like on Gen7-11) and leaves the CCS in
either the compressed or the pass-through state.  Therefore, we should
initialize the CCS to 0x00 even for MCS+CCS surfaces.

Reviewed-by: Sagar Ghuge<sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4074>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4074>

diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c
index 6f182c6cc0c33f6d2eb0cd087dc2f44e1ae46482..8a3a9a87f7a1f7d3c3002aab8783e8124059b56c 100644 (file)
--- a/src/gallium/drivers/iris/iris_resource.c
+++ b/src/gallium/drivers/iris/iris_resource.c
@@ -668,20 +668,8 @@ iris_resource_init_aux_buf(struct iris_resource *res, uint32_t alloc_flags,
                 res->aux.surf.size_B);
       }
 
-      /* Bspec section titled : MCS/CCS Buffers for Render Target(s) states:
-       *    - If Software wants to enable Color Compression without Fast clear,
-       *      Software needs to initialize MCS with zeros.
-       *    - Lossless compression and CCS initialized to all F (using HW Fast
-       *      Clear or SW direct Clear)
-       *
-       * We think, the first bullet point above is referring to CCS aux
-       * surface. Since we initialize the MCS in the clear state, we also
-       * initialize the CCS in the clear state (via SW direct clear) to keep
-       * the two in sync.
-       */
       memset((char*)map + res->aux.extra_aux.offset,
-             isl_aux_usage_has_mcs(res->aux.usage) ? 0xFF : 0,
-             res->aux.extra_aux.surf.size_B);
+             0, res->aux.extra_aux.surf.size_B);
 
       /* Zero the indirect clear color to match ::fast_clear_color. */
       memset((char *)map + res->aux.clear_color_offset, 0,

diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index 3643dab97904ed5ccc273748f13632e297fa9fb4..f3cb1751ea95704acfe063402ecb4ec0ec84aa48 100644 (file)
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -644,6 +644,10 @@ enum isl_aux_usage {
    ISL_AUX_USAGE_HIZ_CCS,
 
    /** The auxiliary surface is an MCS and CCS is also enabled
+    *
+    * In this mode, we have fused MCS+CCS compression where the MCS is used
+    * for fast-clears and "identical samples" compression just like on Gen7-11
+    * but each plane is then CCS compressed.
     *
     * @invariant isl_surf::samples > 1
     */