Add tests/various/abc9.{v,ys} with SCC test

diff --git a/tests/various/abc9.v b/tests/various/abc9.v
new file mode 100644 (file)
index 0000000..8271cd2
--- /dev/null
+++ b/tests/various/abc9.v
@@ -0,0 +1,5 @@
+module abc9_test027(output reg o);
+initial o = 1'b0;
+always @*
+    o <= ~o;
+endmodule

diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
new file mode 100644 (file)
index 0000000..922f700
--- /dev/null
+++ b/tests/various/abc9.ys
@@ -0,0 +1,14 @@
+read_verilog abc9.v
+proc
+design -save gold
+
+abc9 -lut 4
+check
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter
+