TimingInfo: index by (port_name,offset)

diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h
index e2af4d51a0c6c8be17325809e84d5f0e7b3c3dd0..8d090417584aefba602c2e7dcceadfcefb981c21 100644 (file)
--- a/kernel/timinginfo.h
+++ b/kernel/timinginfo.h
@@ -25,17 +25,27 @@
 
 YOSYS_NAMESPACE_BEGIN
 
-typedef std::pair<RTLIL::SigBit,RTLIL::SigBit> BitBit;
-
-struct ModuleTiming
-{
-       RTLIL::IdString type;
-       dict<BitBit, int> comb;
-       dict<RTLIL::SigBit, int> arrival, required;
-};
-
 struct TimingInfo
 {
+       struct NameBit
+       {
+               RTLIL::IdString name;
+               int offset;
+               NameBit() {}
+               NameBit(const RTLIL::SigBit &b) : name(b.wire->name), offset(b.offset) {}
+               bool operator==(const NameBit& nb) const { return nb.name == name && nb.offset == offset; }
+               bool operator!=(const NameBit& nb) const { return !operator==(nb); }
+               unsigned int hash() const { return mkhash_add(name.hash(), offset); }
+       };
+       typedef std::pair<NameBit,NameBit> BitBit;
+
+       struct ModuleTiming
+       {
+               RTLIL::IdString type;
+               dict<BitBit, int> comb;
+               dict<NameBit, int> arrival, required;
+       };
+
        dict<RTLIL::IdString, ModuleTiming> data;
 
        TimingInfo()

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index f7097fadb8c0339fbcf861e1acba3c0bc1af94dd..e5de2bcc4cf21cb185d5e90e1348d70cc16d8c76 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -473,11 +473,11 @@ void prep_lut(RTLIL::Design *design, int maxlut)
 
                auto &t = timing.setup_module(module);
 
-               SigBit o;
+               TimingInfo::NameBit o;
                std::vector<int> specify;
                for (const auto &i : t.comb) {
                        auto &d = i.first.second;
-                       if (o == SigBit())
+                       if (o == TimingInfo::NameBit())
                                o = d;
                        else if (o != d)
                                log_error("(* abc9_lut *) module '%s' with has more than one output.\n", log_id(module));
@@ -581,7 +581,8 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
                                                first = false;
                                        else
                                                ss << " ";
-                                       auto it = t.find(wire);
+                                       log_assert(GetSize(wire) == 1);
+                                       auto it = t.find(SigBit(wire,0));
                                        if (it == t.end())
                                                // Assume that no setup time means zero
                                                ss << 0;