[rs6000] Replace vsx_xvcdpsp by vsx_xvcvdpsp

2019-11-01  Kewen Lin  <linkw@gcc.gnu.org>

    * config/rs6000/vsx.md (vsx_xvcdpsp): Remove define_insn.
    (UNSPEC_VSX_XVCDPSP): Remove.
    * config/rs6000/rs6000.c (rs6000_generate_float2_double_code):
    Replace gen_vsx_xvcdpsp by gen_vsx_xvcvdpsp.

From-SVN: r277706

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 08d3ba0232c050263a057d18684610ec95a52cd4..7b1645e499ed160b4b6505c17533d0c7b4991ed0 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2019-11-01  Kewen Lin  <linkw@gcc.gnu.org>
+
+       * config/rs6000/vsx.md (vsx_xvcdpsp): Remove define_insn.
+       (UNSPEC_VSX_XVCDPSP): Remove.
+       * config/rs6000/rs6000.c (rs6000_generate_float2_double_code):
+       Replace gen_vsx_xvcdpsp by gen_vsx_xvcvdpsp.
+
 2019-11-01  Tobias Burnus  <tobias@codesourcery.com>
 
        * hooks.c (hook_tree_tree_bool_null): New.

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 9ed51515b2e15f6265780af4ee9878b0297549bd..d9d275b01c04f509875ad3aa5dbf601582703425 100644 (file)
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -26079,8 +26079,8 @@ rs6000_generate_float2_double_code (rtx dst, rtx src1, rtx src2)
   rtx_tmp2 = gen_reg_rtx (V4SFmode);
   rtx_tmp3 = gen_reg_rtx (V4SFmode);
 
-  emit_insn (gen_vsx_xvcdpsp (rtx_tmp2, rtx_tmp0));
-  emit_insn (gen_vsx_xvcdpsp (rtx_tmp3, rtx_tmp1));
+  emit_insn (gen_vsx_xvcvdpsp (rtx_tmp2, rtx_tmp0));
+  emit_insn (gen_vsx_xvcvdpsp (rtx_tmp3, rtx_tmp1));
 
   if (BYTES_BIG_ENDIAN)
     emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index a0b2e7b1fc016a76b365b43308d3ea46e7a26178..7b29c7f258e4a08a1b81027245cb06689cafec17 100644 (file)
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -301,7 +301,6 @@
    UNSPEC_VSX_XVCVSXDDP
    UNSPEC_VSX_XVCVUXDDP
    UNSPEC_VSX_XVCVDPSXDS
-   UNSPEC_VSX_XVCDPSP
    UNSPEC_VSX_XVCVDPUXDS
    UNSPEC_VSX_SIGN_EXTEND
    UNSPEC_VSX_XVCVSPSXWS
@@ -2375,14 +2374,6 @@
   "xvcvuxdsp %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
-(define_insn "vsx_xvcdpsp"
-  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
-       (unspec:V4SF [(match_operand:V2DF 1 "vsx_register_operand" "wa")]
-                    UNSPEC_VSX_XVCDPSP))]
-  "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvdpsp %x0,%x1"
-  [(set_attr "type" "vecdouble")])
-
 ;; Convert from 32-bit to 64-bit types
 ;; Provide both vector and scalar targets
 (define_insn "vsx_xvcvsxwdp"