lasmicon: better management of optional bandwidth module (automatically inserted...

diff --git a/misoclib/mem/sdram/core/lasmicon/multiplexer.py b/misoclib/mem/sdram/core/lasmicon/multiplexer.py
index cb1fe53f70c84cb07d7b623f3e29171baf1de435..4627e673d8612f232c38539190068a9b7b8c3c31 100644 (file)
--- a/misoclib/mem/sdram/core/lasmicon/multiplexer.py
+++ b/misoclib/mem/sdram/core/lasmicon/multiplexer.py
@@ -90,13 +90,13 @@ class _Steerer(Module):
 
 class Multiplexer(Module, AutoCSR):
        def __init__(self, phy, geom_settings, timing_settings, bank_machines, refresher, dfi, lasmic,
-                       with_bandwidth_measurement=False):
+                       with_bandwidth=False):
                assert(phy.settings.nphases == len(dfi.phases))
 
                # Command choosing
                requests = [bm.cmd for bm in bank_machines]
-               choose_cmd = _CommandChooser(requests)
-               choose_req = _CommandChooser(requests)
+               self.submodules.choose_cmd = choose_cmd = _CommandChooser(requests)
+               self.submodules.choose_req = choose_req = _CommandChooser(requests)
                self.comb += [
                        choose_cmd.want_reads.eq(0),
                        choose_cmd.want_writes.eq(0)
@@ -106,7 +106,6 @@ class Multiplexer(Module, AutoCSR):
                                choose_cmd.want_cmds.eq(1),
                                choose_req.want_cmds.eq(1)
                        ]
-               self.submodules += choose_cmd, choose_req
 
                # Command steering
                nop = CommandRequest(geom_settings.mux_a, geom_settings.bank_a)
@@ -212,5 +211,11 @@ class Multiplexer(Module, AutoCSR):
                fsm.finalize()
                self.comb += refresher.ack.eq(fsm.state == fsm.encoding["REFRESH"])
 
-               if with_bandwidth_measurement:
-                       self.submodules.bandwidth = Bandwidth(choose_req.cmd)
+               self.with_bandwidth = with_bandwidth
+
+       def add_bandwidth(self):
+               self.with_bandwidth = True
+
+       def do_finalize(self):
+               if self.with_bandwidth:
+                       self.submodules.bandwidth = Bandwidth(self.choose_req.cmd)

diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
index 4fbfb73daa3cc03aac74ddc9c5f108fec2305463..ac4024c34332bca3bb9cfdd8fa0f64eb0367eb99 100644 (file)
--- a/misoclib/soc/sdram.py
+++ b/misoclib/soc/sdram.py
@@ -19,7 +19,8 @@ class SDRAMSoC(SoC):
        def __init__(self, platform, clk_freq,
                        ramcon_type="lasmicon",
                        with_l2=True, l2_size=8192,
-                       with_memtest=False,
+                       with_bandwidth=False,   # specific to LASMICON,
+                       with_memtest=False,     # ignored for MINICON
                        **kwargs):
                SoC.__init__(self, platform, clk_freq, **kwargs)
                self.ramcon_type = ramcon_type
@@ -28,6 +29,7 @@ class SDRAMSoC(SoC):
                self.l2_size = l2_size
 
                self.with_memtest = with_memtest
+               self.with_bandwidth = with_bandwidth or with_memtest
 
                self._sdram_phy_registered = False
 
@@ -41,6 +43,9 @@ class SDRAMSoC(SoC):
 
                # LASMICON frontend
                if self.ramcon_type == "lasmicon":
+                       if self.with_bandwidth:
+                               self.sdram.controller.multiplexer.add_bandwidth()
+
                        if self.with_memtest:
                                self.submodules.memtest_w = memtest.MemtestWriter(self.sdram.crossbar.get_master())
                                self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master())