if (igbe->regs.rdtr.delay()) {
DPRINTF(EthernetSM, "RXS: Scheduling DTR for %d\n",
igbe->regs.rdtr.delay() * igbe->intClock());
- if (igbe->rdtrEvent.scheduled())
- igbe->rdtrEvent.reschedule(curTick + igbe->regs.rdtr.delay() *
- igbe->intClock());
- else
- igbe->rdtrEvent.schedule(curTick + igbe->regs.rdtr.delay() *
- igbe->intClock());
+ igbe->rdtrEvent.reschedule(curTick + igbe->regs.rdtr.delay() *
+ igbe->intClock(),true);
}
if (igbe->regs.radv.idv() && igbe->regs.rdtr.delay()) {
DPRINTF(EthernetDesc, "Descriptor had IDE set\n");
if (igbe->regs.tidv.idv()) {
DPRINTF(EthernetDesc, "setting tidv\n");
- if (igbe->tidvEvent.scheduled())
- igbe->tidvEvent.reschedule(curTick + igbe->regs.tidv.idv() *
- igbe->intClock());
- else
- igbe->tidvEvent.schedule(curTick + igbe->regs.tidv.idv() *
- igbe->intClock());
+ igbe->tidvEvent.reschedule(curTick + igbe->regs.tidv.idv() *
+ igbe->intClock(), true);
}
if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) {
else if (backoffTime < device->maxBackoffDelay)
backoffTime <<= 1;
- if (backoffEvent.scheduled())
- backoffEvent.reschedule(curTick + backoffTime);
- else
- backoffEvent.schedule(curTick + backoffTime);
+ backoffEvent.reschedule(curTick + backoffTime, true);
DPRINTF(DMA, "Backoff time set to %d ticks\n", backoffTime);
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
- if (txEvent.scheduled())
- txEvent.reschedule(curTick + cycles(1));
- else
- txEvent.schedule(curTick + cycles(1));
+ txEvent.reschedule(curTick + cycles(1), true);
}
bool
DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
- if (txEvent.scheduled())
- txEvent.reschedule(curTick + cycles(1));
- else
- txEvent.schedule(curTick + cycles(1));
+ txEvent.reschedule(curTick + cycles(1), true);
}
bool
void schedule(Tick t);
/// Reschedule the event with the current priority
- void reschedule(Tick t);
+ // always parameter means to schedule if not already scheduled
+ void reschedule(Tick t, bool always = false);
/// Remove the event from the current schedule
void deschedule();
}
inline void
-Event::reschedule(Tick t)
+Event::reschedule(Tick t, bool always)
{
- assert(scheduled());
- clearFlags(Squashed);
+ assert(scheduled() || always);
#if TRACING_ON
when_scheduled = curTick;
#endif
_when = t;
- queue->reschedule(this);
+
+ if (scheduled()) {
+ clearFlags(Squashed);
+ queue->reschedule(this);
+ } else {
+ setFlags(Scheduled);
+ queue->schedule(this);
+ }
}
inline void
Tick resume = curTick + Clock::Int::ns * ns;
- if (quiesceEvent->scheduled())
- quiesceEvent->reschedule(resume);
- else
- quiesceEvent->schedule(resume);
+ quiesceEvent->reschedule(resume, true);
DPRINTF(Quiesce, "%s: quiesceNs(%d) until %d\n",
tc->getCpuPtr()->name(), ns, resume);
Tick resume = curTick + tc->getCpuPtr()->cycles(cycles);
- if (quiesceEvent->scheduled())
- quiesceEvent->reschedule(resume);
- else
- quiesceEvent->schedule(resume);
+ quiesceEvent->reschedule(resume, true);
DPRINTF(Quiesce, "%s: quiesceCycles(%d) until %d\n",
tc->getCpuPtr()->name(), cycles, resume);