* config/sparc/sol2.h: Don't include sys/mman.h.
* config/sparc/sparc.c (arith_operand): Use SMALL_INT32.
(arith_4096_operand): Don't throw high bits away.
(const64_operand): Take sign extension of CONST_INTs into account.
(const64_high_operand, sparc_emit_set_const32): Likewise.
(GEN_HIGHINT64): Likewise.
(sparc_emit_set_const64_quick1): Likewise.
(const64_is_2insns): Likewise.
(print_operand): Use trunc_int_for_mode for sign extension.
* config/sparc/sparc.h (SMALL_INT32): Likewise.
* config/sparc/sparc.md (movqi): Sign-extend CONST_DOUBLE
chars. Assume CONST_INT is already properly sign-extended.
(movdi split): Sign-extend each SImode part.
(andsi3 split): Don't mask high bits off, so that result
remains properly sign-extend.
(iorsi3 split): Likewise.
(xorsi3 split): Likewise.
From-SVN: r49970
+2002-02-22 Alexandre Oliva <aoliva@redhat.com>
+
+ * config/sparc/sol2.h: Don't include sys/mman.h.
+ * config/sparc/sparc.c (arith_operand): Use SMALL_INT32.
+ (arith_4096_operand): Don't throw high bits away.
+ (const64_operand): Take sign extension of CONST_INTs into account.
+ (const64_high_operand, sparc_emit_set_const32): Likewise.
+ (GEN_HIGHINT64): Likewise.
+ (sparc_emit_set_const64_quick1): Likewise.
+ (const64_is_2insns): Likewise.
+ (print_operand): Use trunc_int_for_mode for sign extension.
+ * config/sparc/sparc.h (SMALL_INT32): Likewise.
+ * config/sparc/sparc.md (movqi): Sign-extend CONST_DOUBLE
+ chars. Assume CONST_INT is already properly sign-extended.
+ (movdi split): Sign-extend each SImode part.
+ (andsi3 split): Don't mask high bits off, so that result
+ remains properly sign-extend.
+ (iorsi3 split): Likewise.
+ (xorsi3 split): Likewise.
+
2002-02-22 Richard Sandiford <rsandifo@redhat.com>
* fold-const.c (fold): Fix typo in comments.
/* This declares mprotect (used in TRANSFER_FROM_TRAMPOLINE) for
libgcc2.c. */
-#ifdef L_trampoline
+/* We don't want to include this because sys/mman.h is not present on
+ some non-Solaris configurations that use sol2.h. */
+#if 0 /* def L_trampoline */
#include <sys/mman.h>
#endif
rtx op;
enum machine_mode mode;
{
- int val;
if (register_operand (op, mode))
return 1;
if (GET_CODE (op) != CONST_INT)
return 0;
- val = INTVAL (op) & 0xffffffff;
- return SPARC_SIMM13_P (val);
+ return SMALL_INT32 (op);
}
/* Return true if OP is a constant 4096 */
int val;
if (GET_CODE (op) != CONST_INT)
return 0;
- val = INTVAL (op) & 0xffffffff;
return val == 4096;
}
&& SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
&& (CONST_DOUBLE_HIGH (op) ==
((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
- (HOST_WIDE_INT)0xffffffff : 0)))
+ (HOST_WIDE_INT)-1 : 0)))
#endif
);
}
enum machine_mode mode ATTRIBUTE_UNUSED;
{
return ((GET_CODE (op) == CONST_INT
- && (INTVAL (op) & 0xfffffc00) != 0
+ && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
&& SPARC_SETHI_P (INTVAL (op))
#if HOST_BITS_PER_WIDE_INT != 64
/* Must be positive on non-64bit host else the
)
|| (GET_CODE (op) == CONST_DOUBLE
&& CONST_DOUBLE_HIGH (op) == 0
- && (CONST_DOUBLE_LOW (op) & 0xfffffc00) != 0
+ && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
&& SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
}
&& (INTVAL (op1) & 0x80000000) != 0)
emit_insn (gen_rtx_SET
(VOIDmode, temp,
- gen_rtx_CONST_DOUBLE (VOIDmode, INTVAL (op1) & 0xfffffc00,
+ gen_rtx_CONST_DOUBLE (VOIDmode,
+ INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
0)));
else
emit_insn (gen_rtx_SET (VOIDmode, temp,
- GEN_INT (INTVAL (op1) & 0xfffffc00)));
+ GEN_INT (INTVAL (op1)
+ & ~(HOST_WIDE_INT)0x3ff)));
emit_insn (gen_rtx_SET (VOIDmode,
op0,
static rtx gen_safe_XOR64 PARAMS ((rtx, HOST_WIDE_INT));
#if HOST_BITS_PER_WIDE_INT == 64
-#define GEN_HIGHINT64(__x) GEN_INT ((__x) & 0xfffffc00)
+#define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
#define GEN_INT64(__x) GEN_INT (__x)
#else
#define GEN_HIGHINT64(__x) \
- gen_rtx_CONST_DOUBLE (VOIDmode, (__x) & 0xfffffc00, 0)
+ gen_rtx_CONST_DOUBLE (VOIDmode, (__x) & ~(HOST_WIDE_INT)0x3ff, 0)
#define GEN_INT64(__x) \
gen_rtx_CONST_DOUBLE (VOIDmode, (__x) & 0xffffffff, \
((__x) & 0x80000000 \
- ? 0xffffffff : 0))
+ ? -1 : 0))
#endif
/* The optimizer is not to assume anything about exactly
{
emit_insn (gen_rtx_SET (VOIDmode, op0,
gen_safe_XOR64 (temp,
- (-0x400 | (low_bits & 0x3ff)))));
+ (-(HOST_WIDE_INT)0x400
+ | (low_bits & 0x3ff)))));
}
}
}
int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
if (high_bits == 0
- || high_bits == 0xffffffff)
+ || high_bits == -1)
return 1;
analyze_64bit_constant (high_bits, low_bits,
case 'b':
{
/* Print a sign-extended character. */
- int i = INTVAL (x) & 0xff;
- if (i & 0x80)
- i |= 0xffffff00;
+ int i = trunc_int_for_mode (INTVAL (x), QImode);
fprintf (file, "%d", i);
return;
}
SMALL_INT is used throughout the port so we continue to use it. */
#define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X)))
/* 13 bit immediate, considering only the low 32 bits */
-#define SMALL_INT32(X) (SPARC_SIMM13_P ((int)INTVAL (X) & 0xffffffff))
+#define SMALL_INT32(X) (SPARC_SIMM13_P (trunc_int_for_mode \
+ (INTVAL (X), SImode)))
#define SPARC_SETHI_P(X) \
(((unsigned HOST_WIDE_INT) (X) & \
(TARGET_ARCH64 ? ~(unsigned HOST_WIDE_INT) 0xfffffc00 : 0x3ff)) == 0)
a double if needed. */
if (GET_CODE (operands[1]) == CONST_DOUBLE)
{
- operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xff);
- }
- else if (GET_CODE (operands[1]) == CONST_INT)
- {
- /* And further, we know for all QI cases that only the
- low byte is significant, which we can always process
- in a single insn. So mask it now. */
- operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff);
+ operands[1] = GEN_INT (trunc_int_for_mode
+ (CONST_DOUBLE_LOW (operands[1]), QImode));
}
/* Handle sets of MEM first. */
#else
unsigned int low, high;
- low = INTVAL (operands[1]) & 0xffffffff;
- high = (INTVAL (operands[1]) >> 32) & 0xffffffff;
+ low = trunc_int_for_mode (INTVAL (operands[1]), SImode);
+ high = trunc_int_for_mode (INTVAL (operands[1]) >> 32, SImode);
emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), GEN_INT (high)));
/* Slick... but this trick loses if this subreg constant part
(set (match_dup 0) (and:SI (not:SI (match_dup 3)) (match_dup 1)))]
"
{
- operands[4] = GEN_INT (~INTVAL (operands[2]) & 0xffffffff);
+ operands[4] = GEN_INT (~INTVAL (operands[2]));
}")
;; Split DImode logical operations requiring two instructions.
(set (match_dup 0) (ior:SI (not:SI (match_dup 3)) (match_dup 1)))]
"
{
- operands[4] = GEN_INT (~INTVAL (operands[2]) & 0xffffffff);
+ operands[4] = GEN_INT (~INTVAL (operands[2]));
}")
(define_insn "*or_not_di_sp32"
(set (match_dup 0) (not:SI (xor:SI (match_dup 3) (match_dup 1))))]
"
{
- operands[4] = GEN_INT (~INTVAL (operands[2]) & 0xffffffff);
+ operands[4] = GEN_INT (~INTVAL (operands[2]));
}")
(define_split
(set (match_dup 0) (xor:SI (match_dup 3) (match_dup 1)))]
"
{
- operands[4] = GEN_INT (~INTVAL (operands[2]) & 0xffffffff);
+ operands[4] = GEN_INT (~INTVAL (operands[2]));
}")
;; xnor patterns. Note that (a ^ ~b) == (~a ^ b) == ~(a ^ b).