+2015-07-08 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
+
+ * defaults.h: Provide default for WORD_REGISTER_OPERATIONS.
+ * config/alpha/alpha.h: Define WORD_REGISTER_OPERATIONS to 1.
+ * config/arc/arc.h: Likewise.
+ * config/arm/arm.h: Likewise.
+ * config/bfin/bfin.h: Likewise.
+ * config/epiphany/epiphany.h: Likewise.
+ * config/frv/frv.h: Likewise.
+ * config/ia64/ia64.h: Likewise.
+ * config/iq2000/iq2000.h: Likewise.
+ * config/lm32/lm32.h: Likewise.
+ * config/m32r/m32r.h: Likewise.
+ * config/mcore/mcore.h: Likewise.
+ * config/mep/mep.h: Likewise.
+ * config/microblaze/microblaze.h: Likewise.
+ * config/mips/mips.h: Likewise.
+ * config/mmix/mmix.h: Likewise.
+ * config/mn10300/mn10300.h: Likewise.
+ * config/nds32/nds32.h: Likewise.
+ * config/nios2/nios2.h: Likewise.
+ * config/pa/pa.h: Likewise.
+ * config/rl78/rl78.h: Likewise.
+ * config/sh/sh.h: Likewise.
+ * config/sparc/sparc.h: Likewise.
+ * config/stormy16/stormy16.h: Likewise.
+ * config/tilegx/tilegx.h: Likewise.
+ * config/tilepro/tilepro.h: Likewise.
+ * config/v850/v850.h: Likewise.
+ * config/xtensa/xtensa.h: Likewise.
+ * doc/tm.texi: Regenerate.
+ * doc/tm.texi.in: Adjust.
+ * combine.c (simplify_set): Likewise.
+ (simplify_comparison): Likewise.
+ * expr.c (store_constructor): Likewise.
+ * internal-fn.c (expand_arith_overflow): Likewise.
+ * reload.c (push_reload): Likewise.
+ (find_reloads): Likewise.
+ (find_reloads_subreg_address): Likewise.
+ * reload1.c (eliminate_regs_1): Likewise.
+ * rtlanal.c (nonzero_bits1): Likewise.
+ (num_sign_bit_copies1): Likewise.
+ * simplify-rtx.c (simplify_truncation): Likewise.
+
2015-07-08 Trevor Saunders <tbsaunde+gcc@tbsaunde.org>
* auto-inc-dec.c (pass_inc_dec::execute): Don't check the value
/ UNITS_PER_WORD)
== ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
+ (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
-#ifndef WORD_REGISTER_OPERATIONS
- && (GET_MODE_SIZE (GET_MODE (src))
- < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
-#endif
+ && (WORD_REGISTER_OPERATIONS
+ || (GET_MODE_SIZE (GET_MODE (src))
+ < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
#ifdef CANNOT_CHANGE_MODE_CLASS
&& ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
&& REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
/* Try a few ways of applying the same transformation to both operands. */
while (1)
{
-#ifndef WORD_REGISTER_OPERATIONS
+#if !WORD_REGISTER_OPERATIONS
/* The test below this one won't handle SIGN_EXTENDs on these machines,
so check specially. */
if (code != GTU && code != GEU && code != LTU && code != LEU
However, if we commute the AND inside the SUBREG then
they no longer have defined values and the meaning of
the code has been changed. */
- && (0
-#ifdef WORD_REGISTER_OPERATIONS
- || (mode_width > GET_MODE_PRECISION (tmode)
- && mode_width <= BITS_PER_WORD)
-#endif
+ && ((WORD_REGISTER_OPERATIONS
+ && mode_width > GET_MODE_PRECISION (tmode)
+ && mode_width <= BITS_PER_WORD)
|| (mode_width <= GET_MODE_PRECISION (tmode)
&& subreg_lowpart_p (XEXP (op0, 0))))
&& CONST_INT_P (XEXP (op0, 1))
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified.
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
*/
/* Evaluates to true if A and B are mac flags that can be used
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
/* Define this macro if operations between registers with integral mode smaller
than a word are always performed on the entire register. Most RISC machines
have this property and most CISC machines do not. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define this macro to be a C expression indicating when insns that read
memory in MODE, an integral mode narrower than a word, set the bits outside
/* Define this macro if operations between registers with integral mode smaller
than a word are always performed on the entire register. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define this macro to be a C expression indicating when insns that read
memory in MODE, an integral mode narrower than a word, set the bits outside
#define CASE_VECTOR_MODE SImode
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
#define CASE_VECTOR_MODE Pmode
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
and another. All register moves are cheap. */
#define REGISTER_MOVE_COST(MODE, SRCCLASS, DSTCLASS) 2
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Assembler output control. */
#define ASM_COMMENT_START "\t//"
#define CASE_VECTOR_MODE SImode
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
#define SHORT_IMMEDIATES_SIGN_EXTEND 1
&& TYPE_MODE (TREE_TYPE (TYPE)) == QImode) \
&& (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN))
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* When in 64-bit mode, move insns will sign extend SImode and CCmode
moves. All other references are zero extended. */
#define CASE_VECTOR_MODE DImode
#define CASE_VECTOR_PC_RELATIVE 0
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* We have a choice, which makes this yet another parameter to tweak. The
gut feeling is currently that SIGN_EXTEND wins; "int" is more frequent
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
/* Define this macro if operations between registers with integral mode
smaller than a word are always performed on the entire register. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* A C expression indicating when insns that read memory in mem_mode,
an integral mode narrower than a word, set the bits outside of mem_mode
#define LOAD_EXTEND_OP(MODE) (ZERO_EXTEND)
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
#endif /* GCC_NIOS2_H */
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
#define POINTERS_EXTEND_UNSIGNED 1
#define FUNCTION_MODE HImode
#define CASE_VECTOR_MODE Pmode
-#define WORD_REGISTER_OPERATIONS 0
+#define WORD_REGISTER_OPERATIONS 1
#define HAS_LONG_COND_BRANCH 0
#define HAS_LONG_UNCOND_BRANCH 0
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
/* Define if operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
will either zero-extend or sign-extend. The value of this macro should
#define CASE_VECTOR_MODE SImode
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
#define CLEAR_RATIO(speed) ((speed) ? 15 : TILEGX_CALL_RATIO)
#define SET_RATIO(speed) ((speed) ? 15 : TILEGX_CALL_RATIO)
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
#define LOAD_EXTEND_OP(MODE) ((MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
#define CLEAR_RATIO(speed) ((speed) ? 15 : TILEPRO_CALL_RATIO)
#define SET_RATIO(speed) ((speed) ? 15 : TILEPRO_CALL_RATIO)
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
#define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE,PREFIX,NUM,TABLE) \
ASM_OUTPUT_ALIGN ((FILE), (TARGET_BIG_SWITCH ? 2 : 1));
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Byte and short loads sign extend the value to a word. */
#define LOAD_EXTEND_OP(MODE) SIGN_EXTEND
/* Operations between registers always perform the operation
on the full register even if a narrower mode is specified. */
-#define WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 1
/* Xtensa loads are zero-extended by default. */
#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
#define SHORT_IMMEDIATES_SIGN_EXTEND 0
#endif
+#ifndef WORD_REGISTER_OPERATIONS
+#define WORD_REGISTER_OPERATIONS 0
+#endif
+
#ifdef GCC_INSN_FLAGS_H
/* Dependent default target macro definitions
@end deftypefn
@defmac WORD_REGISTER_OPERATIONS
-Define this macro if operations between registers with integral mode
+Define this macro to 1 if operations between registers with integral mode
smaller than a word are always performed on the entire register.
Most RISC machines have this property and most CISC machines do not.
@end defmac
@hook TARGET_CASE_VALUES_THRESHOLD
@defmac WORD_REGISTER_OPERATIONS
-Define this macro if operations between registers with integral mode
+Define this macro to 1 if operations between registers with integral mode
smaller than a word are always performed on the entire register.
Most RISC machines have this property and most CISC machines do not.
@end defmac
store_constructor (tree exp, rtx target, int cleared, HOST_WIDE_INT size)
{
tree type = TREE_TYPE (exp);
-#ifdef WORD_REGISTER_OPERATIONS
HOST_WIDE_INT exp_size = int_size_in_bytes (type);
-#endif
switch (TREE_CODE (type))
{
highest_pow2_factor (offset));
}
-#ifdef WORD_REGISTER_OPERATIONS
/* If this initializes a field that is smaller than a
word, at the start of a word, try to widen it to a full
word. This special case allows us to output C++ member
function initializations in a form that the optimizers
can understand. */
- if (REG_P (target)
+ if (WORD_REGISTER_OPERATIONS
+ && REG_P (target)
&& bitsize < BITS_PER_WORD
&& bitpos % BITS_PER_WORD == 0
&& GET_MODE_CLASS (mode) == MODE_INT
bitsize = BITS_PER_WORD;
mode = word_mode;
}
-#endif
if (MEM_P (to_rtx) && !MEM_KEEP_ALIAS_SET_P (to_rtx)
&& DECL_NONADDRESSABLE_P (field))
return;
}
-#ifdef WORD_REGISTER_OPERATIONS
/* For sub-word operations, if target doesn't have them, start
with precres widening right away, otherwise do it only
if the most simple cases can't be used. */
- if (orig_precres == precres && precres < BITS_PER_WORD)
+ if (WORD_REGISTER_OPERATIONS
+ && orig_precres == precres
+ && precres < BITS_PER_WORD)
;
- else
-#endif
- if ((uns0_p && uns1_p && unsr_p && prec0 <= precres && prec1 <= precres)
+ else if ((uns0_p && uns1_p && unsr_p && prec0 <= precres
+ && prec1 <= precres)
|| ((!uns0_p || !uns1_p) && !unsr_p
&& prec0 + uns0_p <= precres
&& prec1 + uns1_p <= precres))
/* For sub-word operations, retry with a wider type first. */
if (orig_precres == precres && precop <= BITS_PER_WORD)
{
-#ifdef WORD_REGISTER_OPERATIONS
+#if WORD_REGISTER_OPERATIONS
int p = BITS_PER_WORD;
#else
int p = precop;
&& INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (in)))
&& LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (in))) != UNKNOWN)
#endif
-#ifdef WORD_REGISTER_OPERATIONS
+#if WORD_REGISTER_OPERATIONS
|| ((GET_MODE_PRECISION (inmode)
< GET_MODE_PRECISION (GET_MODE (SUBREG_REG (in))))
&& ((GET_MODE_SIZE (inmode) - 1) / UNITS_PER_WORD ==
#endif
inloc = &SUBREG_REG (in);
in = *inloc;
-#if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS)
- if (MEM_P (in))
+#if ! defined (LOAD_EXTEND_OP)
+ if (!WORD_REGISTER_OPERATIONS
+ && MEM_P (in))
/* This is supposed to happen only for paradoxical subregs made by
combine.c. (SUBREG (MEM)) isn't supposed to occur other ways. */
gcc_assert (GET_MODE_SIZE (GET_MODE (in)) <= GET_MODE_SIZE (inmode));
|| MEM_P (SUBREG_REG (out)))
&& ((GET_MODE_PRECISION (outmode)
> GET_MODE_PRECISION (GET_MODE (SUBREG_REG (out))))
-#ifdef WORD_REGISTER_OPERATIONS
+#if WORD_REGISTER_OPERATIONS
|| ((GET_MODE_PRECISION (outmode)
< GET_MODE_PRECISION (GET_MODE (SUBREG_REG (out))))
&& ((GET_MODE_SIZE (outmode) - 1) / UNITS_PER_WORD ==
#endif
outloc = &SUBREG_REG (out);
out = *outloc;
-#if ! defined (LOAD_EXTEND_OP) && ! defined (WORD_REGISTER_OPERATIONS)
- gcc_assert (!MEM_P (out)
+ gcc_assert (WORD_REGISTER_OPERATIONS || !MEM_P (out)
|| GET_MODE_SIZE (GET_MODE (out))
<= GET_MODE_SIZE (outmode));
-#endif
outmode = GET_MODE (out);
}
|| ((MEM_P (operand)
|| (REG_P (operand)
&& REGNO (operand) >= FIRST_PSEUDO_REGISTER))
-#ifndef WORD_REGISTER_OPERATIONS
+#if !WORD_REGISTER_OPERATIONS
&& (((GET_MODE_BITSIZE (GET_MODE (operand))
< BIGGEST_ALIGNMENT)
&& (GET_MODE_SIZE (operand_mode[i])
if (paradoxical_subreg_p (x))
return NULL;
-#ifdef WORD_REGISTER_OPERATIONS
- if (GET_MODE_SIZE (outer_mode) < GET_MODE_SIZE (inner_mode)
+ if (WORD_REGISTER_OPERATIONS
+ && GET_MODE_SIZE (outer_mode) < GET_MODE_SIZE (inner_mode)
&& ((GET_MODE_SIZE (outer_mode) - 1) / UNITS_PER_WORD
== (GET_MODE_SIZE (inner_mode) - 1) / UNITS_PER_WORD))
return NULL;
-#endif
/* Since we don't attempt to handle paradoxical subregs, we can just
call into simplify_subreg, which will handle all remaining checks
if (MEM_P (new_rtx)
&& ((x_size < new_size
-#ifdef WORD_REGISTER_OPERATIONS
+#if WORD_REGISTER_OPERATIONS
/* On these machines, combine can create rtl of the form
(set (subreg:m1 (reg:m2 R) 0) ...)
where m1 < m2, and expects something interesting to
just return the mode mask. Those tests will then be false. */
return nonzero;
-#ifndef WORD_REGISTER_OPERATIONS
/* If MODE is wider than X, but both are a single word for both the host
and target machines, we can compute this from which bits of the
object might be nonzero in its own mode, taking into account the fact
causes the high-order bits to become undefined. So they are
not known to be zero. */
- if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
+ if (!WORD_REGISTER_OPERATIONS
+ && GET_MODE (x) != VOIDmode
+ && GET_MODE (x) != mode
&& GET_MODE_PRECISION (GET_MODE (x)) <= BITS_PER_WORD
&& GET_MODE_PRECISION (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
&& GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (GET_MODE (x)))
nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
return nonzero;
}
-#endif
code = GET_CODE (x);
switch (code)
nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode,
known_x, known_mode, known_ret);
-#if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
+#if WORD_REGISTER_OPERATIONS && defined (LOAD_EXTEND_OP)
/* If this is a typical RISC machine, we only have to worry
about the way loads are extended. */
if ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND
if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_PRECISION (GET_MODE (x)))
{
-#ifndef WORD_REGISTER_OPERATIONS
/* If this machine does not do all register operations on the entire
register and MODE is wider than the mode of X, we can say nothing
at all about the high-order bits. */
- return 1;
-#else
+ if (!WORD_REGISTER_OPERATIONS)
+ return 1;
+
/* Likewise on machines that do, if the mode of the object is smaller
than a word and loads of that size don't sign extend, we can say
nothing about the high order bits. */
#endif
)
return 1;
-#endif
}
switch (code)
- bitwidth)));
}
-#ifdef WORD_REGISTER_OPERATIONS
#ifdef LOAD_EXTEND_OP
/* For paradoxical SUBREGs on machines where all register operations
affect the entire register, just look inside. Note that we are
then we lose all sign bit copies that existed before the store
to the stack. */
- if (paradoxical_subreg_p (x)
+ if (WORD_REGISTER_OPERATIONS
+ && paradoxical_subreg_p (x)
&& LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
&& MEM_P (SUBREG_REG (x)))
return cached_num_sign_bit_copies (SUBREG_REG (x), mode,
known_x, known_mode, known_ret);
-#endif
#endif
break;
the truncation, i.e. simplify (truncate:QI (op:SI (x:SI) (y:SI))) into
(op:QI (truncate:QI (x:SI)) (truncate:QI (y:SI))). */
if (1
-#ifdef WORD_REGISTER_OPERATIONS
- && precision >= BITS_PER_WORD
-#endif
+ && (!WORD_REGISTER_OPERATIONS || precision >= BITS_PER_WORD)
&& (GET_CODE (op) == PLUS
|| GET_CODE (op) == MINUS
|| GET_CODE (op) == MULT))
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