aco: add new addr64 bit to MUBUF instructions on GFX6-GFX7

According to the different ISA docs (and to LLVM), this bit seems
to only exists on GFX6-GFX7.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3432>

diff --git a/src/amd/compiler/aco_assembler.cpp b/src/amd/compiler/aco_assembler.cpp
index dc341e59de0cb1238309feb08cc41eeeb7fb9045..241e3d443097868ee27c64ec31f05f7cfb5f7eec 100644 (file)
--- a/src/amd/compiler/aco_assembler.cpp
+++ b/src/amd/compiler/aco_assembler.cpp
@@ -311,6 +311,9 @@ void emit_instruction(asm_context& ctx, std::vector<uint32_t>& out, Instruction*
       encoding |= (mubuf->lds ? 1 : 0) << 16;
       encoding |= (mubuf->glc ? 1 : 0) << 14;
       encoding |= (mubuf->idxen ? 1 : 0) << 13;
+      assert(!mubuf->addr64 || ctx.chip_class <= GFX7);
+      if (ctx.chip_class == GFX6 || ctx.chip_class == GFX7)
+         encoding |= (mubuf->addr64 ? 1 : 0) << 15;
       encoding |= (mubuf->offen ? 1 : 0) << 12;
       if (ctx.chip_class == GFX8 || ctx.chip_class == GFX9) {
          assert(!mubuf->dlc); /* Device-level coherent is not supported on GFX9 and lower */

diff --git a/src/amd/compiler/aco_ir.h b/src/amd/compiler/aco_ir.h
index 4239e5ffaf88042227444bbbc469face72b72d37..5fa9e1cb869ee7e7744e5735bc08df549287c1a2 100644 (file)
--- a/src/amd/compiler/aco_ir.h
+++ b/src/amd/compiler/aco_ir.h
@@ -786,6 +786,7 @@ struct MUBUF_instruction : public Instruction {
    uint16_t offset : 12; /* Unsigned byte offset - 12 bit */
    bool offen : 1; /* Supply an offset from VGPR (VADDR) */
    bool idxen : 1; /* Supply an index from VGPR (VADDR) */
+   bool addr64 : 1; /* SI, CIK: Address size is 64-bit */
    bool glc : 1; /* globally coherent */
    bool dlc : 1; /* NAVI: device level coherent */
    bool slc : 1; /* system level coherent */

diff --git a/src/amd/compiler/aco_opcodes.py b/src/amd/compiler/aco_opcodes.py
index 17520b7209f7c141077f23f9b6cb799ecaea5a2b..db4a349bcb932a7f0d2e5c883f112064dc608081 100644 (file)
--- a/src/amd/compiler/aco_opcodes.py
+++ b/src/amd/compiler/aco_opcodes.py
@@ -91,6 +91,7 @@ class Format(Enum):
          return [('unsigned', 'offset', None),
                  ('bool', 'offen', None),
                  ('bool', 'idxen', 'false'),
+                 ('bool', 'addr64', 'false'),
                  ('bool', 'disable_wqm', 'false'),
                  ('bool', 'glc', 'false'),
                  ('bool', 'dlc', 'false'),

diff --git a/src/amd/compiler/aco_print_ir.cpp b/src/amd/compiler/aco_print_ir.cpp
index 780980a8c69cfb2dbcebfd0d6d563bcc2c8e7400..81711a278c90a65f4ac31b0a9380109b18e89e1e 100644 (file)
--- a/src/amd/compiler/aco_print_ir.cpp
+++ b/src/amd/compiler/aco_print_ir.cpp
@@ -236,6 +236,8 @@ static void print_instr_format_specific(struct Instruction *instr, FILE *output)
          fprintf(output, " offen");
       if (mubuf->idxen)
          fprintf(output, " idxen");
+      if (mubuf->addr64)
+         fprintf(output, " addr64");
       if (mubuf->glc)
          fprintf(output, " glc");
       if (mubuf->dlc)