interconnect/axi: remove Record inheritance on AXIInterface/AXILiteInterface.

diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py
index 64d88ff33872d7798447b8891dd19810c03477cc..af4196da1d9551f41d54d7265df1591ced3ba32f 100644 (file)
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@@ -55,7 +55,7 @@ def r_description(data_width, id_width):
         ("id",   id_width)
     ]
 
-class AXIInterface(Record):
+class AXIInterface:
     def __init__(self, data_width=32, address_width=32, id_width=1, clock_domain="sys"):
         self.data_width    = data_width
         self.address_width = address_width
@@ -88,7 +88,7 @@ def r_lite_description(data_width):
         ("data", data_width)
     ]
 
-class AXILiteInterface(Record):
+class AXILiteInterface:
     def __init__(self, data_width=32, address_width=32, clock_domain="sys"):
         self.data_width    = data_width
         self.address_width = address_width