switch (step) {
case 0:
if (reg >= REG_XPR0 && reg <= REG_XPR31) {
+ unsigned int i = 0;
+ if (reg == S0) {
+ gs.dr_write32(i++, csrr(S0, CSR_DSCRATCH));
+ }
if (gs.xlen == 32) {
- gs.dr_write32(0, sw(reg - REG_XPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
+ gs.dr_write32(i++, sw(reg - REG_XPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
} else {
- gs.dr_write32(0, sd(reg - REG_XPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
+ gs.dr_write32(i++, sd(reg - REG_XPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
}
- gs.dr_write_jump(1);
+ gs.dr_write_jump(i);
} else if (reg == REG_PC) {
gs.start_packet();
if (gs.xlen == 32) {