cpu/static_inst.cc
cpu/sampler/sampler.cc
+ mem/request.cc
mem/connector.cc
mem/mem_object.cc
mem/physical.cc
Fault
-AlphaTLB::checkCacheability(CpuRequestPtr &req)
+AlphaTLB::checkCacheability(RequestPtr &req)
{
// in Alpha, cacheability is controlled by upper-level bits of the
// physical address
#if ALPHA_TLASER
- if (req->paddr & PAddrUncachedBit39) {
+ if (req->getPaddr() & PAddrUncachedBit39) {
#else
- if (req->paddr & PAddrUncachedBit43) {
+ if (req->getPaddr() & PAddrUncachedBit43) {
#endif
// IPR memory space not implemented
- if (PAddrIprSpace(req->paddr)) {
+ if (PAddrIprSpace(req->getPaddr())) {
return new UnimpFault("IPR memory space not implemented!");
} else {
// mark request as uncacheable
- req->flags |= UNCACHEABLE;
+ req->setFlags(req->getFlags() | UNCACHEABLE);
#if !ALPHA_TLASER
// Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
- req->paddr &= PAddrUncachedMask;
+ req->setPaddr(req->getPaddr() & PAddrUncachedMask);
#endif
}
}
Fault
-AlphaITB::translate(CpuRequestPtr &req, ExecContext *xc) const
+AlphaITB::translate(RequestPtr &req, ExecContext *xc) const
{
- if (AlphaISA::PcPAL(req->vaddr)) {
+ if (AlphaISA::PcPAL(req->getVaddr())) {
// strip off PAL PC marker (lsb is 1)
- req->paddr = (req->vaddr & ~3) & PAddrImplMask;
+ req->setPaddr((req->getVaddr() & ~3) & PAddrImplMask);
hits++;
return NoFault;
}
- if (req->flags & PHYSICAL) {
- req->paddr = req->vaddr;
+ if (req->getFlags() & PHYSICAL) {
+ req->setPaddr(req->getVaddr());
} else {
// verify that this is a good virtual address
- if (!validVirtualAddress(req->vaddr)) {
+ if (!validVirtualAddress(req->getVaddr())) {
acv++;
- return new ItbAcvFault(req->vaddr);
+ return new ItbAcvFault(req->getVaddr());
}
// VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
#if ALPHA_TLASER
if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
- VAddrSpaceEV5(req->vaddr) == 2) {
+ VAddrSpaceEV5(req->getVaddr()) == 2) {
#else
- if (VAddrSpaceEV6(req->vaddr) == 0x7e) {
+ if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
#endif
// only valid in kernel mode
if (ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM)) !=
AlphaISA::mode_kernel) {
acv++;
- return new ItbAcvFault(req->vaddr);
+ return new ItbAcvFault(req->getVaddr());
}
- req->paddr = req->vaddr & PAddrImplMask;
+ req->setPaddr(req->getVaddr() & PAddrImplMask);
#if !ALPHA_TLASER
// sign extend the physical address properly
- if (req->paddr & PAddrUncachedBit40)
- req->paddr |= ULL(0xf0000000000);
+ if (req->getPaddr() & PAddrUncachedBit40)
+ req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
else
- req->paddr &= ULL(0xffffffffff);
+ req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
#endif
} else {
// not a physical address: need to look up pte
int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
- AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(),
+ AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
asn);
if (!pte) {
misses++;
- return new ItbPageFault(req->vaddr);
+ return new ItbPageFault(req->getVaddr());
}
- req->paddr = (pte->ppn << AlphaISA::PageShift) +
- (AlphaISA::VAddr(req->vaddr).offset() & ~3);
+ req->setPaddr((pte->ppn << AlphaISA::PageShift) +
+ (AlphaISA::VAddr(req->getVaddr()).offset()
+ & ~3));
// check permissions for this access
if (!(pte->xre &
(1 << ICM_CM(xc->readMiscReg(AlphaISA::IPR_ICM))))) {
// instruction access fault
acv++;
- return new ItbAcvFault(req->vaddr);
+ return new ItbAcvFault(req->getVaddr());
}
hits++;
}
// check that the physical address is ok (catch bad physical addresses)
- if (req->paddr & ~PAddrImplMask)
+ if (req->getPaddr() & ~PAddrImplMask)
return genMachineCheckFault();
return checkCacheability(req);
}
Fault
-AlphaDTB::translate(CpuRequestPtr &req, ExecContext *xc, bool write) const
+AlphaDTB::translate(RequestPtr &req, ExecContext *xc, bool write) const
{
Addr pc = xc->readPC();
/**
* Check for alignment faults
*/
- if (req->vaddr & (req->size - 1)) {
- DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr,
- req->size);
+ if (req->getVaddr() & (req->getSize() - 1)) {
+ DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->getVaddr(),
+ req->getSize());
uint64_t flags = write ? MM_STAT_WR_MASK : 0;
- return new DtbAlignmentFault(req->vaddr, req->flags, flags);
+ return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
}
if (pc & 0x1) {
- mode = (req->flags & ALTMODE) ?
+ mode = (req->getFlags() & ALTMODE) ?
(AlphaISA::mode_type)ALT_MODE_AM(
xc->readMiscReg(AlphaISA::IPR_ALT_MODE))
: AlphaISA::mode_kernel;
}
- if (req->flags & PHYSICAL) {
- req->paddr = req->vaddr;
+ if (req->getFlags() & PHYSICAL) {
+ req->setPaddr(req->getVaddr());
} else {
// verify that this is a good virtual address
- if (!validVirtualAddress(req->vaddr)) {
+ if (!validVirtualAddress(req->getVaddr())) {
if (write) { write_acv++; } else { read_acv++; }
uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
MM_STAT_BAD_VA_MASK |
MM_STAT_ACV_MASK;
- return new DtbPageFault(req->vaddr, req->flags, flags);
+ return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
}
// Check for "superpage" mapping
#if ALPHA_TLASER
if ((MCSR_SP(xc->readMiscReg(AlphaISA::IPR_MCSR)) & 2) &&
- VAddrSpaceEV5(req->vaddr) == 2) {
+ VAddrSpaceEV5(req->getVaddr()) == 2) {
#else
- if (VAddrSpaceEV6(req->vaddr) == 0x7e) {
+ if (VAddrSpaceEV6(req->getVaddr()) == 0x7e) {
#endif
// only valid in kernel mode
if (write) { write_acv++; } else { read_acv++; }
uint64_t flags = ((write ? MM_STAT_WR_MASK : 0) |
MM_STAT_ACV_MASK);
- return new DtbAcvFault(req->vaddr, req->flags, flags);
+ return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
}
- req->paddr = req->vaddr & PAddrImplMask;
+ req->setPaddr(req->getVaddr() & PAddrImplMask);
#if !ALPHA_TLASER
// sign extend the physical address properly
- if (req->paddr & PAddrUncachedBit40)
- req->paddr |= ULL(0xf0000000000);
+ if (req->getPaddr() & PAddrUncachedBit40)
+ req->setPaddr(req->getPaddr() | ULL(0xf0000000000));
else
- req->paddr &= ULL(0xffffffffff);
+ req->setPaddr(req->getPaddr() & ULL(0xffffffffff));
#endif
} else {
int asn = DTB_ASN_ASN(xc->readMiscReg(AlphaISA::IPR_DTB_ASN));
// not a physical address: need to look up pte
- AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->vaddr).vpn(),
+ AlphaISA::PTE *pte = lookup(AlphaISA::VAddr(req->getVaddr()).vpn(),
asn);
if (!pte) {
if (write) { write_misses++; } else { read_misses++; }
uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
MM_STAT_DTB_MISS_MASK;
- return (req->flags & VPTE) ?
- (Fault)(new PDtbMissFault(req->vaddr, req->flags,
+ return (req->getFlags() & VPTE) ?
+ (Fault)(new PDtbMissFault(req->getVaddr(), req->getFlags(),
flags)) :
- (Fault)(new NDtbMissFault(req->vaddr, req->flags,
+ (Fault)(new NDtbMissFault(req->getVaddr(), req->getFlags(),
flags));
}
- req->paddr = (pte->ppn << AlphaISA::PageShift) +
- AlphaISA::VAddr(req->vaddr).offset();
+ req->setPaddr((pte->ppn << AlphaISA::PageShift) +
+ AlphaISA::VAddr(req->getVaddr()).offset());
if (write) {
if (!(pte->xwe & MODE2MASK(mode))) {
uint64_t flags = MM_STAT_WR_MASK |
MM_STAT_ACV_MASK |
(pte->fonw ? MM_STAT_FONW_MASK : 0);
- return new DtbPageFault(req->vaddr, req->flags, flags);
+ return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
}
if (pte->fonw) {
write_acv++;
uint64_t flags = MM_STAT_WR_MASK |
MM_STAT_FONW_MASK;
- return new DtbPageFault(req->vaddr, req->flags, flags);
+ return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
}
} else {
if (!(pte->xre & MODE2MASK(mode))) {
read_acv++;
uint64_t flags = MM_STAT_ACV_MASK |
(pte->fonr ? MM_STAT_FONR_MASK : 0);
- return new DtbAcvFault(req->vaddr, req->flags, flags);
+ return new DtbAcvFault(req->getVaddr(), req->getFlags(), flags);
}
if (pte->fonr) {
read_acv++;
uint64_t flags = MM_STAT_FONR_MASK;
- return new DtbPageFault(req->vaddr, req->flags, flags);
+ return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
}
}
}
}
// check that the physical address is ok (catch bad physical addresses)
- if (req->paddr & ~PAddrImplMask)
+ if (req->getPaddr() & ~PAddrImplMask)
return genMachineCheckFault();
return checkCacheability(req);
return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
}
- static Fault checkCacheability(CpuRequestPtr &req);
+ static Fault checkCacheability(RequestPtr &req);
// Checkpointing
virtual void serialize(std::ostream &os);
AlphaITB(const std::string &name, int size);
virtual void regStats();
- Fault translate(CpuRequestPtr &req, ExecContext *xc) const;
+ Fault translate(RequestPtr &req, ExecContext *xc) const;
};
class AlphaDTB : public AlphaTLB
AlphaDTB(const std::string &name, int size);
virtual void regStats();
- Fault translate(CpuRequestPtr &req, ExecContext *xc, bool write) const;
+ Fault translate(RequestPtr &req, ExecContext *xc, bool write) const;
};
#endif // __ALPHA_MEMORY_HH__
int getInstAsid() { return regs.instAsid(); }
int getDataAsid() { return regs.dataAsid(); }
- Fault translateInstReq(CpuRequestPtr &req)
+ Fault translateInstReq(RequestPtr &req)
{
return itb->translate(req, proxy);
}
- Fault translateDataReadReq(CpuRequestPtr &req)
+ Fault translateDataReadReq(RequestPtr &req)
{
return dtb->translate(req, proxy, false);
}
- Fault translateDataWriteReq(CpuRequestPtr &req)
+ Fault translateDataWriteReq(RequestPtr &req)
{
return dtb->translate(req, proxy, true);
}
int getInstAsid() { return asid; }
int getDataAsid() { return asid; }
- Fault translateInstReq(CpuRequestPtr &req)
+ Fault translateInstReq(RequestPtr &req)
{
return process->pTable->translate(req);
}
- Fault translateDataReadReq(CpuRequestPtr &req)
+ Fault translateDataReadReq(RequestPtr &req)
{
return process->pTable->translate(req);
}
- Fault translateDataWriteReq(CpuRequestPtr &req)
+ Fault translateDataWriteReq(RequestPtr &req)
{
return process->pTable->translate(req);
}
/*
template <class T>
- Fault read(CpuRequestPtr &req, T &data)
+ Fault read(RequestPtr &req, T &data)
{
#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
if (req->flags & LOCKED) {
}
template <class T>
- Fault write(CpuRequestPtr &req, T &data)
+ Fault write(RequestPtr &req, T &data)
{
#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
ExecContext *xc;
inst = new_inst;
}
- Fault instRead(CpuRequestPtr &req)
+ Fault instRead(RequestPtr &req)
{
panic("instRead not implemented");
// return funcPhysMem->read(req, inst);
virtual int getInstAsid() = 0;
virtual int getDataAsid() = 0;
- virtual Fault translateInstReq(CpuRequestPtr &req) = 0;
+ virtual Fault translateInstReq(RequestPtr &req) = 0;
- virtual Fault translateDataReadReq(CpuRequestPtr &req) = 0;
+ virtual Fault translateDataReadReq(RequestPtr &req) = 0;
- virtual Fault translateDataWriteReq(CpuRequestPtr &req) = 0;
+ virtual Fault translateDataWriteReq(RequestPtr &req) = 0;
// Also somewhat obnoxious. Really only used for the TLB fault.
// However, may be quite useful in SPARC.
int getInstAsid() { return actualXC->getInstAsid(); }
int getDataAsid() { return actualXC->getDataAsid(); }
- Fault translateInstReq(CpuRequestPtr &req)
+ Fault translateInstReq(RequestPtr &req)
{ return actualXC->translateInstReq(req); }
- Fault translateDataReadReq(CpuRequestPtr &req)
+ Fault translateDataReadReq(RequestPtr &req)
{ return actualXC->translateDataReadReq(req); }
- Fault translateDataWriteReq(CpuRequestPtr &req)
+ Fault translateDataWriteReq(RequestPtr &req)
{ return actualXC->translateDataWriteReq(req); }
// @todo: Do I need this?
xcProxy = cpuXC->getProxy();
#if SIMPLE_CPU_MEM_ATOMIC || SIMPLE_CPU_MEM_IMMEDIATE
- ifetch_req = new CpuRequest;
- ifetch_req->asid = 0;
- ifetch_req->size = sizeof(MachInst);
+ ifetch_req = new Request(true);
+ ifetch_req->setAsid(0);
+ ifetch_req->setSize(sizeof(MachInst));
ifetch_pkt = new Packet;
ifetch_pkt->cmd = Read;
ifetch_pkt->data = (uint8_t *)&inst;
ifetch_pkt->req = ifetch_req;
ifetch_pkt->size = sizeof(MachInst);
- data_read_req = new CpuRequest;
- data_read_req->asid = 0;
+ data_read_req = new Request(true);
+ data_read_req->setAsid(0);
data_read_pkt = new Packet;
data_read_pkt->cmd = Read;
data_read_pkt->data = new uint8_t[8];
data_read_pkt->req = data_read_req;
- data_write_req = new CpuRequest;
- data_write_req->asid = 0;
+ data_write_req = new Request(true);
+ data_write_req->setAsid(0);
data_write_pkt = new Packet;
data_write_pkt->cmd = Write;
data_write_pkt->req = data_write_req;
// memReq->reset(addr, sizeof(T), flags);
#if SIMPLE_CPU_MEM_TIMING
- CpuRequest *data_read_req = new CpuRequest;
+ CpuRequest *data_read_req = new Request(true);
#endif
- data_read_req->vaddr = addr;
- data_read_req->size = sizeof(T);
- data_read_req->flags = flags;
- data_read_req->time = curTick;
+ data_read_req->setVaddr(addr);
+ data_read_req->setSize(sizeof(T));
+ data_read_req->setFlags(flags);
+ data_read_req->setTime(curTick);
// translate to physical address
Fault fault = cpuXC->translateDataReadReq(data_read_req);
data_read_pkt->req = data_read_req;
data_read_pkt->data = new uint8_t[8];
#endif
- data_read_pkt->addr = data_read_req->paddr;
+ data_read_pkt->addr = data_read_req->getPaddr();
data_read_pkt->size = sizeof(T);
sendDcacheRequest(data_read_pkt);
}
*/
// This will need a new way to tell if it has a dcache attached.
- if (data_read_req->flags & UNCACHEABLE)
+ if (data_read_req->getFlags() & UNCACHEABLE)
recordEvent("Uncached Read");
return fault;
Fault
SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
- data_write_req->vaddr = addr;
- data_write_req->time = curTick;
- data_write_req->size = sizeof(T);
- data_write_req->flags = flags;
+ data_write_req->setVaddr(addr);
+ data_write_req->setTime(curTick);
+ data_write_req->setSize(sizeof(T));
+ data_write_req->setFlags(flags);
// translate to physical address
Fault fault = cpuXC->translateDataWriteReq(data_write_req);
#else
data_write_pkt->data = (uint8_t *)&data;
#endif
- data_write_pkt->addr = data_write_req->paddr;
+ data_write_pkt->addr = data_write_req->getPaddr();
data_write_pkt->size = sizeof(T);
sendDcacheRequest(data_write_pkt);
*res = data_write_pkt->result;
// This will need a new way to tell if it's hooked up to a cache or not.
- if (data_write_req->flags & UNCACHEABLE)
+ if (data_write_req->getFlags() & UNCACHEABLE)
recordEvent("Uncached Write");
// If the write needs to have a fault on the access, consider calling
#if SIMPLE_CPU_MEM_TIMING
CpuRequest *ifetch_req = new CpuRequest();
- ifetch_req->size = sizeof(MachInst);
+ ifetch_req->setSize(sizeof(MachInst));
#endif
- ifetch_req->vaddr = cpuXC->readPC() & ~3;
- ifetch_req->time = curTick;
+ ifetch_req->setVaddr(cpuXC->readPC() & ~3);
+ ifetch_req->setTime(curTick);
/* memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
IFETCH_FLAGS(xc->regs.pc));
ifetch_pkt->req = ifetch_req;
ifetch_pkt->size = sizeof(MachInst);
#endif
- ifetch_pkt->addr = ifetch_req->paddr;
+ ifetch_pkt->addr = ifetch_req->getPaddr();
sendIcacheRequest(ifetch_pkt);
#if SIMPLE_CPU_MEM_TIMING || SIMPLE_CPU_MEM_ATOMIC
#if SIMPLE_CPU_MEM_TIMING
Packet *retry_pkt;
#elif SIMPLE_CPU_MEM_ATOMIC || SIMPLE_CPU_MEM_IMMEDIATE
- CpuRequest *ifetch_req;
- Packet *ifetch_pkt;
- CpuRequest *data_read_req;
- Packet *data_read_pkt;
- CpuRequest *data_write_req;
- Packet *data_write_pkt;
+ Request *ifetch_req;
+ Packet *ifetch_pkt;
+ Request *data_read_req;
+ Packet *data_read_pkt;
+ Request *data_write_req;
+ Packet *data_write_pkt;
#endif
// Pointer to the sampler that is telling us to switchover.
PioPort::recvTiming(Packet &pkt)
{
device->recvAtomic(pkt);
- sendTiming(pkt, pkt.time-pkt.req->time);
+ sendTiming(pkt, pkt.time-pkt.req->getTime());
return Success;
}
int prevSize = 0;
Packet basePkt;
- Request baseReq;
+ Request baseReq(false);
basePkt.flags = 0;
basePkt.coherence = NULL;
basePkt.cmd = cmd;
basePkt.result = Unknown;
basePkt.req = NULL;
- baseReq.nicReq = true;
- baseReq.time = curTick;
+// baseReq.nicReq = true;
+ baseReq.setTime(curTick);
completionEvent = event;
pkt->addr = gen.addr();
pkt->size = gen.size();
pkt->req = req;
- pkt->req->paddr = pkt->addr;
- pkt->req->size = pkt->size;
+ pkt->req->setPaddr(pkt->addr);
+ pkt->req->setSize(pkt->size);
// Increment the data pointer on a write
pkt->data = data ? data + prevSize : NULL ;
prevSize += pkt->size;
transmitList.push_back(&packet);
} else if (state == Atomic) {*/
sendAtomic(pkt);
- completionEvent->schedule(pkt.time - pkt.req->time);
+ completionEvent->schedule(pkt.time - pkt.req->getTime());
completionEvent = NULL;
/* } else if (state == Functional) {
sendFunctional(pkt);
Fault
-PageTable::translate(CpuRequestPtr &req)
+PageTable::translate(RequestPtr &req)
{
- assert(pageAlign(req->vaddr + req->size - 1) == pageAlign(req->vaddr));
- if (!translate(req->vaddr, req->paddr)) {
+ Addr paddr;
+ assert(pageAlign(req->getVaddr() + req->getSize() - 1)
+ == pageAlign(req->getVaddr()));
+ if (!translate(req->getVaddr(), paddr)) {
return genMachineCheckFault();
}
- return page_check(req->paddr, req->size);
+ req->setPaddr(paddr);
+ return page_check(req->getPaddr(), req->getSize());
}
* field of mem_req.
* @param req The memory request.
*/
- Fault translate(CpuRequestPtr &req);
+ Fault translate(RequestPtr &req);
};
void
Port::blobHelper(Addr addr, uint8_t *p, int size, Command cmd)
{
- Request req;
+ Request req(false);
Packet pkt;
pkt.req = &req;
pkt.cmd = cmd;
for (ChunkGenerator gen(addr, size, peerBlockSize());
!gen.done(); gen.next()) {
- pkt.addr = req.paddr = gen.addr();
- pkt.size = req.size = gen.size();
+ req.setPaddr(pkt.addr = gen.addr());
+ req.setSize(pkt.size = gen.size());
pkt.data = p;
sendFunctional(pkt);
p += gen.size();
#include "arch/isa_traits.hh"
class Request;
-class CpuRequest;
typedef Request* RequestPtr;
-typedef CpuRequest* CpuRequestPtr;
/** The request is a Load locked/store conditional. */
const unsigned LOCKED = 0x001;
{
//@todo Make Accesor functions, make these private.
public:
+ /** Cunstructor, needs a bool to signify if it is/isn't Cpu Request. */
+ Request(bool isCpu);
+
+//First non-cpu request fields
+ private:
/** The physical address of the request. */
Addr paddr;
-
- /** whether this req came from the CPU or not **DO we need this??***/
- bool nicReq;
+ /** Wether or not paddr is valid (has been written yet). */
+ bool validPaddr;
/** The size of the request. */
int size;
+ /** Wether or not size is valid (has been written yet). */
+ bool validSize;
/** The time this request was started. Used to calculate latencies. */
Tick time;
+ /** Wether or not time is valid (has been written yet). */
+ bool validTime;
/** Destination address if this is a block copy. */
Addr copyDest;
+ /** Wether or not copyDest is valid (has been written yet). */
+ bool validCopyDest;
+ /** Flag structure for the request. */
uint32_t flags;
-};
+ /** Wether or not flags is valid (has been written yet). */
+ bool validFlags;
-class CpuRequest : public Request
-{
- //@todo Make Accesor functions, make these private.
+//Accsesors for non-cpu request fields
public:
+ /** Accesor for paddr. */
+ Addr getPaddr();
+ /** Accesor for paddr. */
+ void setPaddr(Addr _paddr);
+
+ /** Accesor for size. */
+ int getSize();
+ /** Accesor for size. */
+ void setSize(int _size);
+
+ /** Accesor for time. */
+ Tick getTime();
+ /** Accesor for time. */
+ void setTime(Tick _time);
+
+ /** Accesor for copy dest. */
+ Addr getCopyDest();
+ /** Accesor for copy dest. */
+ void setCopyDest(Addr _copyDest);
+
+ /** Accesor for flags. */
+ uint32_t getFlags();
+ /** Accesor for paddr. */
+ void setFlags(uint32_t _flags);
+
+//Now cpu-request fields
+ private:
+ /** Bool to signify if this is a cpuRequest. */
+ bool cpuReq;
+
/** The virtual address of the request. */
Addr vaddr;
+ /** Wether or not the vaddr is valid. */
+ bool validVaddr;
/** The address space ID. */
int asid;
+ /** Wether or not the asid is valid. */
+ bool validAsid;
/** The return value of store conditional. */
uint64_t scResult;
+ /** Wether or not the sc result is valid. */
+ bool validScResult;
/** The cpu number for statistics. */
int cpuNum;
+ /** Wether or not the cpu number is valid. */
+ bool validCpuNum;
/** The requesting thread id. */
int threadNum;
+ /** Wether or not the thread id is valid. */
+ bool validThreadNum;
/** program counter of initiating access; for tracing/debugging */
Addr pc;
+ /** Wether or not the pc is valid. */
+ bool validPC;
+
+//Accessor Functions for cpu request fields
+ public:
+ /** Accesor function to determine if this is a cpu request or not.*/
+ bool isCpuRequest();
+
+ /** Accesor function for vaddr.*/
+ Addr getVaddr();
+ /** Accesor function for vaddr.*/
+ void setVaddr(Addr _vaddr);
+
+ /** Accesor function for asid.*/
+ int getAsid();
+ /** Accesor function for asid.*/
+ void setAsid(int _asid);
+
+ /** Accesor function for store conditional return value.*/
+ uint64_t getScResult();
+ /** Accesor function for store conditional return value.*/
+ void setScResult(uint64_t _scResult);
+
+ /** Accesor function for cpu number.*/
+ int getCpuNum();
+ /** Accesor function for cpu number.*/
+ void setCpuNum(int _cpuNum);
+
+ /** Accesor function for thread number.*/
+ int getThreadNum();
+ /** Accesor function for thread number.*/
+ void setThreadNum(int _threadNum);
+
+ /** Accesor function for pc.*/
+ Addr getPC();
+ /** Accesor function for pc.*/
+ void setPC(Addr _pc);
+
};
#endif // __MEM_REQUEST_HH__
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