arm.md (mulsidi3adddi, [...]): New patterns for long long multiply-accumulate.

	* config/arm/arm.md (mulsidi3adddi, umulsidi3adddi): New patterns
	for long long multiply-accumulate.

From-SVN: r30919

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 62f07341c1100e847ac59f67a39be7d1ad745e15..da2ec92664549c0d9bbdd498a868926c577837aa 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+Tue Dec 14 08:37:27 CST 1999 Clinton Popetz  <cpopetz@cygnus.com>
+
+       * config/arm/arm.md (mulsidi3adddi, umulsidi3adddi): New patterns
+       for long long multiply-accumulate.
+
 Tue Dec 14 13:51:38 MET 1999  Jan Hubicka  <hubicka@freesoft.cz>
 
        * regclass.c (scan_one_insn): Set loop_cost to 1 when

diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 91795c2c4aa19f1a323993c62e4b8dfed50025cc..6d760d53926ce66e4b49153c88c47533e401fd5c 100644 (file)
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -965,6 +965,20 @@
 [(set_attr "conds" "set")
  (set_attr "type" "mult")])
 
+;; Unnamed template to match long long multiply-accumlate (smlal)
+
+(define_insn "*mulsidi3adddi"
+  [(set (match_operand:DI 0 "s_register_operand" "=&r,&r,&r")
+       (plus:DI
+         (mult:DI (sign_extend:DI
+                   (match_operand:SI 2 "s_register_operand" "r,0,1"))
+                  (sign_extend:DI
+                   (match_operand:SI 1 "s_register_operand" "%r,r,r")))
+         (match_dup 0)))]
+  "arm_fast_multiply"
+  "smlal%?\\t%Q0, %R0, %1, %2"
+[(set_attr "type" "mult")])
+
 (define_insn "mulsidi3"
   [(set (match_operand:DI 0 "s_register_operand" "=&r")
       (mult:DI (sign_extend:DI
@@ -985,6 +999,20 @@
   "umull%?\\t%Q0, %R0, %1, %2"
 [(set_attr "type" "mult")])
 
+;; Unnamed template to match long long unsigned multiply-accumlate (umlal)
+
+(define_insn "*umulsidi3adddi"
+  [(set (match_operand:DI 0 "s_register_operand" "=&r,&r,&r")
+       (plus:DI
+         (mult:DI (zero_extend:DI
+                   (match_operand:SI 2 "s_register_operand" "r,0,1"))
+                  (zero_extend:DI
+                   (match_operand:SI 1 "s_register_operand" "%r,r,r")))
+         (match_dup 0)))]
+  "arm_fast_multiply"
+  "umlal%?\\t%Q0, %R0, %1, %2"
+[(set_attr "type" "mult")])
+
 (define_insn "smulsi3_highpart"
   [(set (match_operand:SI 0 "s_register_operand" "=&r,&r")
        (truncate:SI