[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing/simerr
+Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jun 6 2010 03:04:38
-M5 revision ba1a0193c050 7448 default tip
-M5 started Jun 6 2010 03:24:00
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:52:05
M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
+Exiting @ tick 169506496500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 217525 # Simulator instruction rate (inst/s)
-host_mem_usage 207124 # Number of bytes of host memory used
-host_seconds 2599.94 # Real time elapsed on the host
-host_tick_rate 64460403 # Simulator tick rate (ticks/s)
+host_inst_rate 178555 # Simulator instruction rate (inst/s)
+host_mem_usage 207544 # Number of bytes of host memory used
+host_seconds 3167.39 # Real time elapsed on the host
+host_tick_rate 53516139 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 565552443 # Number of instructions simulated
-sim_seconds 0.167593 # Number of seconds simulated
-sim_ticks 167593085500 # Number of ticks simulated
+sim_seconds 0.169506 # Number of seconds simulated
+sim_ticks 169506496500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 63922842 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 71487962 # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect 180 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 4121924 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 70504427 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 76440051 # Number of BP lookups
-system.cpu.BPredUnit.usedRAS 1674270 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.BTBHits 64068954 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 71556079 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 188 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 4120910 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 70589657 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 76519042 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 1672225 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 62547159 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 18448626 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 19702213 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 323575021 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 1.860023 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 2.297815 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 327417755 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.838193 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 2.277454 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 107931872 33.36% 33.36% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 101513205 31.37% 64.73% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 37265964 11.52% 76.25% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 10166735 3.14% 79.39% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 11290718 3.49% 82.88% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 21721468 6.71% 89.59% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 12702626 3.93% 93.52% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 2533807 0.78% 94.30% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 18448626 5.70% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 105871733 32.34% 32.34% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 108541066 33.15% 65.49% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 36996526 11.30% 76.79% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 11988281 3.66% 80.45% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 10398233 3.18% 83.62% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 21777635 6.65% 90.27% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 9735285 2.97% 93.25% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 2406783 0.74% 93.98% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 19702213 6.02% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 323575021 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 327417755 # Number of insts commited each cycle
system.cpu.commit.COM:count 601856963 # Number of instructions committed
system.cpu.commit.COM:loads 115049510 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 154862033 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 4121096 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 4120073 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 61591802 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 63088611 # The number of squashed insts skipped by commit
system.cpu.committedInsts 565552443 # Number of Instructions Simulated
system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
-system.cpu.cpi 0.592670 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.592670 # CPI: Total CPI of All Threads
+system.cpu.cpi 0.599437 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.599437 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 113443216 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 19248.740390 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7746.370369 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 112634831 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 15560393000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.007126 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 808385 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 590181 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1690289000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.001923 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 218204 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_accesses 116877204 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 19511.922037 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7693.277195 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 116024078 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 16646128000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.007299 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 853126 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 634854 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1679227000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.001868 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 218272 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 32797.392555 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35638.802347 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 37116231 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 76584863381 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.059189 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 2335090 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1996724 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 12058958995 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.008577 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 338366 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 6528.414634 # average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_avg_miss_latency 31935.176109 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34419.628617 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 37146976 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 73589663391 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.058410 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 2304345 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1968193 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 11570226999 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.008521 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 336152 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 7088.486726 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 21363.636364 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 316.462124 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 123 # number of cycles access was blocked
+system.cpu.dcache.avg_refs 323.627554 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 113 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 802995 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 800999 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 235000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 152894537 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 29313.182507 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 24703.537731 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 149751062 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 92145256381 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.020560 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 3143475 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 2586905 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 13749247995 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.003640 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 556570 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 156328525 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 28578.502032 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 23897.692017 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 153171054 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 90235791391 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.020198 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 3157471 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 2603047 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 13249453999 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.003547 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 554424 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.999563 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4094.208277 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 152894537 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 29313.182507 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 24703.537731 # average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.999568 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4094.232018 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 156328525 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 28578.502032 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 23897.692017 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 149751062 # number of overall hits
-system.cpu.dcache.overall_miss_latency 92145256381 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.020560 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 3143475 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 2586905 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 13749247995 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.003640 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 556570 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 153171054 # number of overall hits
+system.cpu.dcache.overall_miss_latency 90235791391 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.020198 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 3157471 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 2603047 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 13249453999 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.003547 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 554424 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 470982 # number of replacements
-system.cpu.dcache.sampled_refs 475078 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 471007 # number of replacements
+system.cpu.dcache.sampled_refs 475103 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4094.208277 # Cycle average of tags in use
-system.cpu.dcache.total_refs 150344193 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 126612000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 335213 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 51119249 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 861 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 4177292 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 689843810 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 144051375 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 122990983 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 9853353 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 3386 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 5413414 # Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses 163070578 # DTB accesses
+system.cpu.dcache.tagsinuse 4094.232018 # Cycle average of tags in use
+system.cpu.dcache.total_refs 153756422 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 126427000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 336082 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 53096224 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 870 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 4174977 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 691367918 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 145684312 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 123209609 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 10007520 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 3007 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 5427610 # Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses 163170180 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_hits 163012019 # DTB hits
-system.cpu.dtb.data_misses 58559 # DTB misses
+system.cpu.dtb.data_hits 163108618 # DTB hits
+system.cpu.dtb.data_misses 61562 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 122259759 # DTB read accesses
+system.cpu.dtb.read_accesses 122378622 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 122237048 # DTB read hits
-system.cpu.dtb.read_misses 22711 # DTB read misses
-system.cpu.dtb.write_accesses 40810819 # DTB write accesses
+system.cpu.dtb.read_hits 122354151 # DTB read hits
+system.cpu.dtb.read_misses 24471 # DTB read misses
+system.cpu.dtb.write_accesses 40791558 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 40774971 # DTB write hits
-system.cpu.dtb.write_misses 35848 # DTB write misses
-system.cpu.fetch.Branches 76440051 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 65631744 # Number of cache lines fetched
-system.cpu.fetch.Cycles 195845469 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 1315609 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 699070033 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 4181068 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.228053 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 65631744 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 65597112 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 2.085617 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 333428374 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.096612 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.077342 # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.write_hits 40754467 # DTB write hits
+system.cpu.dtb.write_misses 37091 # DTB write misses
+system.cpu.fetch.Branches 76519042 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 65743933 # Number of cache lines fetched
+system.cpu.fetch.Cycles 196171036 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 1323544 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 700543147 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 4180854 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.225711 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 65743933 # Number of cycles fetch is stalled on an Icache miss
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+system.cpu.fetch.rate 2.066420 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 337425275 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.076143 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 203214688 60.95% 60.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 10311898 3.09% 64.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 15894466 4.77% 68.81% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 13958250 4.19% 72.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 12033268 3.61% 76.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 13973782 4.19% 80.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 5916300 1.77% 82.57% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 3411105 1.02% 83.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 54714617 16.41% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 206998212 61.35% 61.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 10205574 3.02% 64.37% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 16013127 4.75% 69.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 13976667 4.14% 73.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 12062274 3.57% 76.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 13987466 4.15% 80.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 5886424 1.74% 82.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 3487900 1.03% 83.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 54807631 16.24% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 333428374 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses 65631744 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 36217.817562 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35518.743109 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 65630571 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 42483500 # number of ReadReq miss cycles
+system.cpu.fetch.rateDist::total 337425275 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 65743933 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 36198.392555 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35509.868421 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 65742751 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 42786500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 1173 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 266 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 32215500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_misses 1182 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 270 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 907 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses 912 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 72360.056229 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 72086.349781 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 65631744 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 36217.817562 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35518.743109 # average overall mshr miss latency
-system.cpu.icache.demand_hits 65630571 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 42483500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 65743933 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 36198.392555 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35509.868421 # average overall mshr miss latency
+system.cpu.icache.demand_hits 65742751 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 42786500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses
-system.cpu.icache.demand_misses 1173 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 266 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 32215500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_misses 1182 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 270 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 32385000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 907 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses 912 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.378038 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 774.221896 # Average occupied blocks per context
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-system.cpu.icache.overall_avg_miss_latency 36217.817562 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35518.743109 # average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.379446 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 777.105869 # Average occupied blocks per context
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 65630571 # number of overall hits
-system.cpu.icache.overall_miss_latency 42483500 # number of overall miss cycles
+system.cpu.icache.overall_hits 65742751 # number of overall hits
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system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses
-system.cpu.icache.overall_misses 1173 # number of overall misses
-system.cpu.icache.overall_mshr_hits 266 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 32215500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_misses 1182 # number of overall misses
+system.cpu.icache.overall_mshr_hits 270 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 907 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 35 # number of replacements
-system.cpu.icache.sampled_refs 907 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 36 # number of replacements
+system.cpu.icache.sampled_refs 912 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 774.221896 # Cycle average of tags in use
-system.cpu.icache.total_refs 65630571 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 777.105869 # Cycle average of tags in use
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 1757798 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 67441684 # Number of branches executed
-system.cpu.iew.EXEC:nop 43298534 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.787674 # Inst execution rate
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-system.cpu.iew.EXEC:stores 41206389 # Number of stores executed
+system.cpu.idleCycles 1587719 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 67446690 # Number of branches executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
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-system.cpu.iew.WB:count 596002683 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.810520 # average fanout of values written-back
+system.cpu.iew.WB:consumers 494218268 # num instructions consuming a value
+system.cpu.iew.WB:count 596241723 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.805354 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 396281024 # num instructions producing a value
-system.cpu.iew.WB:rate 1.778124 # insts written-back per cycle
-system.cpu.iew.WB:sent 597106328 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 4603784 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 2069078 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 126900612 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 3145838 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 43054897 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 663551547 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 122804301 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 6319339 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 599203767 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 4454 # Number of times the IQ has become full, causing a stall
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+system.cpu.iew.WB:rate 1.758758 # insts written-back per cycle
+system.cpu.iew.WB:sent 597367655 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 4601660 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 2251946 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 127252956 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 3156398 # Number of squashed instructions skipped by dispatch
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+system.cpu.iew.iewDispatchedInsts 665052109 # Number of instructions dispatched to IQ
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+system.cpu.iew.iewExecutedInsts 599454333 # Number of executed instructions
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 32589 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 9853353 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 86305 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 33854 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 10007520 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 83713 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 194 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 8787843 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 12289 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked 175 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 5470953 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 10609 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 89737 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 5921 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 11851102 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 3242374 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 89737 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 943709 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 3660075 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 1.687279 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.687279 # IPC: Total IPC of All Threads
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+system.cpu.iew.predictedTakenIncorrect 3657087 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 1.668232 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.668232 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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-system.cpu.iq.ISSUE:FU_type_0::IntMult 6669 0.00% 72.47% # Type of FU issued
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-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 29 0.00% 72.47% # Type of FU issued
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-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 72.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.47% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.47% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 605523106 # Type of FU issued
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-system.cpu.iq.ISSUE:fu_busy_rate 0.011779 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 605825667 # Type of FU issued
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+system.cpu.iq.ISSUE:fu_busy_rate 0.011435 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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-system.cpu.iq.ISSUE:fu_full::IntMult 49 0.00% 74.81% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 74.81% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 74.81% # attempts to use FU when none available
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-system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 74.81% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 74.81% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 74.81% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 74.81% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 1469402 20.60% 95.41% # attempts to use FU when none available
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+system.cpu.iq.ISSUE:fu_full::MemRead 1245764 17.98% 94.78% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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+system.cpu.iq.ISSUE:issued_per_cycle::mean 1.795437 # Number of insts issued each cycle
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system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 91844434 27.55% 27.55% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 66796624 20.03% 47.58% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 82026036 24.60% 72.18% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 37142853 11.14% 83.32% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 29318508 8.79% 92.11% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 13804488 4.14% 96.25% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 11015283 3.30% 99.56% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 983503 0.29% 99.85% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8 496645 0.15% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 95395357 28.27% 28.27% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 68329461 20.25% 48.52% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 80056631 23.73% 72.25% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 36910615 10.94% 83.19% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 31840128 9.44% 92.62% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 12299933 3.65% 96.27% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 10951663 3.25% 99.51% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 1050952 0.31% 99.82% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 590535 0.18% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 333428374 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 1.806528 # Inst issue rate
-system.cpu.iq.iqInstsAdded 620252984 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 605523106 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 53278148 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 39411 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 29138505 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total 337425275 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 1.787028 # Inst issue rate
+system.cpu.iq.iqInstsAdded 621764526 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 605825667 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 54809333 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 18475 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 31050369 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 65631783 # ITB accesses
+system.cpu.itb.fetch_accesses 65743973 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_hits 65631744 # ITB hits
-system.cpu.itb.fetch_misses 39 # ITB misses
+system.cpu.itb.fetch_hits 65743933 # ITB hits
+system.cpu.itb.fetch_misses 40 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 256875 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34263.188321 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31137.765450 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 8801356500 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 256875 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 7998513500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 256875 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 219110 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34284.038279 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31037.107304 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 183268 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1228808500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.163580 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 35842 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1112432000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.163580 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 35842 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 81505 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34131.924422 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31025.814367 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 2781922500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_accesses 256831 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34267.808951 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31149.097625 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits 12642 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 8367822000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.950777 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 244189 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 7606267000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.950777 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 244189 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 219184 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34300.593807 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31016.018663 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 183819 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1213040500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.161348 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 35365 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1096881500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.161348 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 35365 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 79334 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34139.271939 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31029.539668 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 2708405000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 81505 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2528759000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 79334 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2461697500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 81505 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 335213 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 335213 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5455.882353 # average number of cycles each access was blocked
+system.cpu.l2cache.UpgradeReq_mshr_misses 79334 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 336082 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 336082 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5312.500000 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 3.750936 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 68 # number of cycles access was blocked
+system.cpu.l2cache.avg_refs 3.798768 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs 371000 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 382500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 475985 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34265.741313 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31125.440272 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 183268 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 10030165000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.614971 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 292717 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 476015 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34271.956402 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31132.262461 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 196461 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 9580862500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.587280 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 279554 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 9110945500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.614971 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 292717 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 8703148500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.587280 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 279554 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.051123 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.447698 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 1675.210024 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 14670.153699 # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses 475985 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34265.741313 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31125.440272 # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0 0.052597 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.448200 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 1723.488326 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 14686.601231 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 476015 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34271.956402 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31132.262461 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 183268 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 10030165000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.614971 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 292717 # number of overall misses
+system.cpu.l2cache.overall_hits 196461 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 9580862500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.587280 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 279554 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 9110945500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.614971 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 292717 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 8703148500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.587280 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 279554 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 85307 # number of replacements
-system.cpu.l2cache.sampled_refs 100934 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 84626 # number of replacements
+system.cpu.l2cache.sampled_refs 100342 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 16345.363723 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 378597 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 16410.089557 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 381176 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 63240 # number of writebacks
-system.cpu.memDep0.conflictingLoads 18950859 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 15231969 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 126900612 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 43054897 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 335186172 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 14808263 # Number of cycles rename is blocking
+system.cpu.l2cache.writebacks 62683 # number of writebacks
+system.cpu.memDep0.conflictingLoads 23861424 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 18454491 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 127252956 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 43259984 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 339012994 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 14846495 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 34154270 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 151775927 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 2034435 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 82 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 895748431 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 680023810 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 518612424 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 115460168 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 9853353 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 41529646 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 54757535 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 1017 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:IQFullEvents 36228613 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 153406470 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 1884931 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 97 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 897942713 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 681539497 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 519842559 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 115704820 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 10007520 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 43459223 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 55987670 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 747 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 33 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 80752072 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts 87364721 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 33 # count of temporary serializing insts renamed
-system.cpu.timesIdled 42487 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.timesIdled 36935 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/gzip
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/gzip
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
+Redirecting stdout to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Feb 24 2010 23:12:40
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 02:27:06
-M5 executing on SC2B0619
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:59:22
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
+Exiting @ tick 777351681000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 1555765 # Simulator instruction rate (inst/s)
-host_mem_usage 191800 # Number of bytes of host memory used
-host_seconds 386.86 # Real time elapsed on the host
-host_tick_rate 2011092592 # Simulator tick rate (ticks/s)
+host_inst_rate 1386497 # Simulator instruction rate (inst/s)
+host_mem_usage 206712 # Number of bytes of host memory used
+host_seconds 434.08 # Real time elapsed on the host
+host_tick_rate 1790782589 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 601856964 # Number of instructions simulated
-sim_seconds 0.778004 # Number of seconds simulated
-sim_ticks 778003833000 # Number of ticks simulated
+sim_seconds 0.777352 # Number of seconds simulated
+sim_ticks 777351681000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 114514042 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 21095.452016 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18095.452016 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 21007.583287 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18007.583287 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 114312810 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_rate 0.001757 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 201232 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3641384000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.001757 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 201232 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.984797 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.984797 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 39122430 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 18417891000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.008337 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 328891 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 17431218000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.008337 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 328891 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 54405.858739 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51405.858739 # average WriteReq mshr miss latency
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 337.091905 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 153965363 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 42750.401322 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 153435240 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 22662971000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 21072602000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.003443 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 530123 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.999559 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4094.195523 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 153965363 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 42750.401322 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 39750.401322 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 153435240 # number of overall hits
-system.cpu.dcache.overall_miss_latency 22662971000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.003443 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 530123 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 21072602000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.003443 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 530123 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 451299 # number of replacements
system.cpu.dcache.sampled_refs 455395 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4094.195523 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4094.197079 # Cycle average of tags in use
system.cpu.dcache.total_refs 153509968 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 579204000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 325723 # number of writebacks
+system.cpu.dcache.warmup_cycle 578599000 # Cycle when the warmup percentage was hit.
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system.cpu.dtb.data_accesses 153970296 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 153965363 # DTB hits
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.328723 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 673.225223 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.328737 # Average percentage of cache occupancy
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system.cpu.icache.overall_accesses 601861898 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.replacements 24 # number of replacements
system.cpu.icache.sampled_refs 795 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 673.225223 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 673.252668 # Cycle average of tags in use
system.cpu.icache.total_refs 601861103 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 13216476000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 254163 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 10166520000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 254163 # number of ReadExReq MSHR misses
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+system.cpu.l2cache.ReadExReq_mshr_misses 241758 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 167236 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1809132000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.172210 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 34791 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1391640000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.172210 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 34791 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 74728 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51996.520715 # average UpgradeReq miss latency
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+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 3885596000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 3778580000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 74728 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2989120000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 74728 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 325723 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 325723 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_mshr_misses 72665 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 325740 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 3.519863 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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-system.cpu.l2cache.demand_miss_rate 0.633407 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 288954 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 11558160000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.633407 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 288954 # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.demand_mshr_misses 276128 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.050771 # Average percentage of cache occupancy
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-system.cpu.l2cache.occ_blocks::1 14679.879055 # Average occupied blocks per context
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system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 167236 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 15025608000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.633407 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 288954 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 11558160000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.633407 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 288954 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 11045120000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.605292 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 276128 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 84513 # number of replacements
-system.cpu.l2cache.sampled_refs 100134 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 83906 # number of replacements
+system.cpu.l2cache.sampled_refs 99616 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 16343.542372 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 352458 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 16400.814735 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 354013 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 63194 # number of writebacks
+system.cpu.l2cache.writebacks 62672 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1556007666 # number of cpu cycles simulated
+system.cpu.numCycles 1554703362 # number of cpu cycles simulated
system.cpu.num_insts 601856964 # Number of instructions executed
system.cpu.num_refs 154866966 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
egid=100
env=
errout=cerr
+Redirecting stdout to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Aug 24 2010 15:34:40
-M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
-M5 started Aug 24 2010 15:44:30
+M5 compiled Aug 26 2010 13:52:30
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:54:54
M5 executing on zizzer
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 808121048000 because target called exit()
+Exiting @ tick 807517408000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 1674821 # Simulator instruction rate (inst/s)
-host_mem_usage 210020 # Number of bytes of host memory used
-host_seconds 357.42 # Real time elapsed on the host
-host_tick_rate 2260963263 # Simulator tick rate (ticks/s)
+host_inst_rate 1492183 # Simulator instruction rate (inst/s)
+host_mem_usage 211112 # Number of bytes of host memory used
+host_seconds 401.17 # Real time elapsed on the host
+host_tick_rate 2012902303 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 598619824 # Number of instructions simulated
-sim_seconds 0.808121 # Number of seconds simulated
-sim_ticks 808121048000 # Number of ticks simulated
+sim_seconds 0.807517 # Number of seconds simulated
+sim_ticks 807517408000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 147793610 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 21168.913260 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18168.913260 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 21105.418688 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18105.418688 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 147603767 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4018770000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 4006716000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001285 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 189843 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3449241000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 3437187000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001285 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 189843 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 69418858 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 69110224 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 17283504000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.004446 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 308634 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 16357602000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.004446 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 308634 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 54322.323841 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51322.323841 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 69111608 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 16690534000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.004426 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 307250 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 15768784000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.004426 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 307250 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 495.382394 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 217212468 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 42734.717951 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 39734.717951 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 216713991 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 21302274000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.002295 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 498477 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 41636.575047 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 38636.575047 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 216715375 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 20697250000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.002289 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 497093 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 19806843000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.002295 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 498477 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 19205971000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.002289 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 497093 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.999571 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4094.243213 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.999572 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4094.246847 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 217212468 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 42734.717951 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 39734.717951 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 41636.575047 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 38636.575047 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 216713991 # number of overall hits
-system.cpu.dcache.overall_miss_latency 21302274000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.002295 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 498477 # number of overall misses
+system.cpu.dcache.overall_hits 216715375 # number of overall hits
+system.cpu.dcache.overall_miss_latency 20697250000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.002289 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 497093 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 19806843000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.002295 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 498477 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 19205971000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.002289 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 497093 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 433495 # number of replacements
system.cpu.dcache.sampled_refs 437591 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4094.243213 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4094.246847 # Cycle average of tags in use
system.cpu.dcache.total_refs 216774877 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 537993000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 305427 # number of writebacks
+system.cpu.dcache.warmup_cycle 537003000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 305501 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.282040 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 577.617873 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.282055 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 577.648910 # Average occupied blocks per context
system.cpu.icache.overall_accesses 570070553 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913 # average overall mshr miss latency
system.cpu.icache.replacements 12 # number of replacements
system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 577.617873 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 577.648910 # Cycle average of tags in use
system.cpu.icache.total_refs 570069910 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadExReq_accesses 247748 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 12882896000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 247748 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 9909920000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 247748 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits 12273 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 12244700000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.950462 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 235475 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 9419000000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.950462 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 235475 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 190486 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 157466 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1717040000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.173346 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 33020 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1320800000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173346 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 33020 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 60886 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_hits 157753 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1702116000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.171839 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 32733 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1309320000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.171839 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 32733 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 59502 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 3166072000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 3094104000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 60886 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2435440000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 59502 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2380080000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 60886 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 305427 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 305427 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_mshr_misses 59502 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 305501 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 305501 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 3.359132 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 3.379196 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 438234 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 157466 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 14599936000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.640681 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 280768 # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits 170026 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 13946816000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.612020 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 268208 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 11230720000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.640681 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 280768 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 10728320000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.612020 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 268208 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.049205 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.452726 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 1612.352730 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 14834.915268 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.050080 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.453180 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 1641.035711 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 14849.786647 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 438234 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 157466 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 14599936000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.640681 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 280768 # number of overall misses
+system.cpu.l2cache.overall_hits 170026 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 13946816000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.612020 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 268208 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 11230720000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.640681 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 280768 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 10728320000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.612020 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 268208 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 81265 # number of replacements
-system.cpu.l2cache.sampled_refs 96683 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 80841 # number of replacements
+system.cpu.l2cache.sampled_refs 96272 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 16447.267999 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 324771 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 16490.822357 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 325322 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 61092 # number of writebacks
+system.cpu.l2cache.writebacks 60805 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1616242096 # number of cpu cycles simulated
+system.cpu.numCycles 1615034816 # number of cpu cycles simulated
system.cpu.num_insts 598619824 # Number of instructions executed
system.cpu.num_refs 219174038 # Number of memory references
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
+cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
egid=100
env=
errout=cerr
-Redirecting stdout to build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing/simout
-Redirecting stderr to build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing/simerr
+Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simout
+Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jun 6 2010 04:01:36
-M5 revision ba1a0193c050 7448 default tip
-M5 started Jun 6 2010 04:02:01
+M5 compiled Aug 26 2010 13:03:41
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:05:09
M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/o3-timing
+command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 1088715493000 because target called exit()
+Exiting @ tick 1088441503500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 109148 # Simulator instruction rate (inst/s)
-host_mem_usage 208820 # Number of bytes of host memory used
-host_seconds 12878.07 # Real time elapsed on the host
-host_tick_rate 84540245 # Simulator tick rate (ticks/s)
+host_inst_rate 76473 # Simulator instruction rate (inst/s)
+host_mem_usage 212472 # Number of bytes of host memory used
+host_seconds 18380.70 # Real time elapsed on the host
+host_tick_rate 59216546 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1405618369 # Number of instructions simulated
-sim_seconds 1.088715 # Number of seconds simulated
-sim_ticks 1088715493000 # Number of ticks simulated
+sim_seconds 1.088442 # Number of seconds simulated
+sim_ticks 1088441503500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 173332559 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 194142411 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 173420048 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 194153919 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 81910123 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 251618660 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 251618660 # Number of BP lookups
+system.cpu.BPredUnit.condIncorrect 81907161 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 251603669 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 251603669 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 86248929 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 8014877 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 8072747 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 1942378796 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 0.766863 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.200662 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 1941955406 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.767030 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.200667 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 1072972593 55.24% 55.24% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 568760584 29.28% 84.52% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 118179777 6.08% 90.61% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 122167717 6.29% 96.90% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 27965504 1.44% 98.34% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 8603273 0.44% 98.78% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 11084471 0.57% 99.35% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 4630000 0.24% 99.59% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 8014877 0.41% 100.00% # Number of insts commited each cycle
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+system.cpu.commit.COM:committed_per_cycle::2 118066725 6.08% 90.59% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 122346784 6.30% 96.89% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 28028862 1.44% 98.34% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 8610798 0.44% 98.78% # Number of insts commited each cycle
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system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
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+system.cpu.commit.COM:committed_per_cycle::total 1941955406 # Number of insts commited each cycle
system.cpu.commit.COM:count 1489537512 # Number of instructions committed
system.cpu.commit.COM:loads 402517247 # Number of loads committed
system.cpu.commit.COM:membars 51356 # Number of memory barriers committed
system.cpu.commit.COM:refs 569375203 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 81910123 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 81907161 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1489537512 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 2243671 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 1349352602 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 1348785802 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1405618369 # Number of Instructions Simulated
system.cpu.committedInsts_total 1405618369 # Number of Instructions Simulated
-system.cpu.cpi 1.549091 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.549091 # CPI: Total CPI of All Threads
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-system.cpu.dcache.ReadReq_avg_miss_latency 14361.598866 # average ReadReq miss latency
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-system.cpu.dcache.ReadReq_miss_rate 0.002146 # miss rate for ReadReq accesses
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+system.cpu.cpi 1.548701 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.548701 # CPI: Total CPI of All Threads
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000565 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 238161 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses 238162 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_avg_miss_latency 38025 # average SwapReq miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35025 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency 1521000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency 1401000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_avg_miss_latency 38027.777778 # average SwapReq miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35027.777778 # average SwapReq mshr miss latency
+system.cpu.dcache.SwapReq_hits 1308 # number of SwapReq hits
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+system.cpu.dcache.SwapReq_miss_rate 0.013575 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses 18 # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency 630500 # number of SwapReq MSHR miss cycles
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+system.cpu.dcache.SwapReq_mshr_misses 18 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 166856630 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 37779.329951 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36098.948570 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 164660283 # number of WriteReq hits
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-system.cpu.dcache.WriteReq_misses 2196347 # number of WriteReq misses
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-system.cpu.dcache.WriteReq_mshr_miss_latency 12459516000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.002069 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 345149 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 36526.139631 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35067.237452 # average WriteReq mshr miss latency
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 1140.488307 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 1140.778331 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 588418863 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 30948.287394 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 24208.768922 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 585317975 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 95967173000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.005270 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 3100888 # number of demand (read+write) misses
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-system.cpu.dcache.demand_mshr_miss_latency 14121217000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000991 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 583310 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 588572453 # number of demand (read+write) accesses
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+system.cpu.dcache.demand_hits 585476295 # number of demand (read+write) hits
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999896 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4095.574437 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 588418863 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 30948.287394 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 24208.768922 # average overall mshr miss latency
+system.cpu.dcache.occ_blocks::0 4095.574913 # Average occupied blocks per context
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 585317975 # number of overall hits
-system.cpu.dcache.overall_miss_latency 95967173000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.005270 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 3100888 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 2517578 # number of overall MSHR hits
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-system.cpu.dcache.overall_mshr_miss_rate 0.000991 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 583310 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 509323 # number of replacements
-system.cpu.dcache.sampled_refs 513419 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 509328 # number of replacements
+system.cpu.dcache.sampled_refs 513424 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.574437 # Cycle average of tags in use
-system.cpu.dcache.total_refs 585548366 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 166128000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 341989 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 421912263 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 3394284142 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 753420072 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 764076323 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 233540433 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:UnblockCycles 2970138 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 251618660 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 350290492 # Number of cache lines fetched
-system.cpu.fetch.Cycles 1175688320 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 10057151 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 3685758924 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 87714492 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.115558 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 350290492 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 173332559 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.692710 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 2175919229 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.693886 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.844671 # Number of instructions fetched each cycle (Total)
+system.cpu.dcache.tagsinuse 4095.574913 # Cycle average of tags in use
+system.cpu.dcache.total_refs 585702974 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 165969000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 343309 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 421597556 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 3393767574 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 753336946 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 764050676 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 233579864 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:UnblockCycles 2970228 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 251603669 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 350205998 # Number of cache lines fetched
+system.cpu.fetch.Cycles 1175621134 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 10022642 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 3685217760 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 87763558 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.115580 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 350205998 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 173420048 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.692887 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 2175535270 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.693936 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.844478 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 1350521444 62.07% 62.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 247724506 11.38% 73.45% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 78785496 3.62% 77.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 36714251 1.69% 78.76% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 82505145 3.79% 82.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 39097939 1.80% 84.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 30045371 1.38% 85.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 19662444 0.90% 86.63% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 290862633 13.37% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 1350120177 62.06% 62.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 247723459 11.39% 73.45% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 78876862 3.63% 77.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 36715633 1.69% 78.76% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 82505940 3.79% 82.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 39095379 1.80% 84.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 30113044 1.38% 85.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 19663449 0.90% 86.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 290721327 13.36% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 2175919229 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses 350290492 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 33351.843100 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34801.230992 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 350288376 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 70572500 # number of ReadReq miss cycles
+system.cpu.fetch.rateDist::total 2175535270 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 350205998 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 33274.163131 # average ReadReq miss latency
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+system.cpu.icache.ReadReq_hits 350203877 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 70574500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 2116 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 735 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 48060500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_misses 2121 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 1381 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 253832.156522 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 253770.925362 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 350290492 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 33351.843100 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34801.230992 # average overall mshr miss latency
-system.cpu.icache.demand_hits 350288376 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 70572500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 350205998 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 33274.163131 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34791.817524 # average overall mshr miss latency
+system.cpu.icache.demand_hits 350203877 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses
-system.cpu.icache.demand_misses 2116 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 735 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 1381 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.icache.overall_avg_mshr_miss_latency 34801.230992 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 350288376 # number of overall hits
-system.cpu.icache.overall_miss_latency 70572500 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses
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-system.cpu.icache.overall_mshr_hits 735 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 1381 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements 223 # number of replacements
system.cpu.icache.sampled_refs 1380 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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-system.cpu.icache.total_refs 350288376 # Total number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
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-system.cpu.iew.lsq.thread.0.ignoredResponses 24118 # Number of memory responses ignored because the instruction is squashed
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system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
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system.cpu.iew.lsq.thread.0.rescheduledLoads 20 # Number of loads that were rescheduled
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-system.cpu.ipc_total 0.645540 # IPC: Total IPC of All Threads
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+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.957299 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 263508 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 239543 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34105.503131 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.510605 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 204890 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1181858000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.144663 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 34653 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1074330000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.144663 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 34653 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 68215 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34213.068973 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31021.842703 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 2333844500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 69939 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2169639000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 68215 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2116155000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 69939 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 341989 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 341989 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_mshr_misses 68215 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 343309 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 343309 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 4.064673 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 4.105608 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 514800 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34276.681695 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31146.590202 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 204503 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 10635951500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.602753 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 310297 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 514805 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34285.718119 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.754123 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 216644 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 10222664000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.579173 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 298161 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 9664693500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.602753 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 310297 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 9287940000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.579173 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 298161 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.056082 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.444448 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 1837.702550 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 14563.687199 # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses 514800 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34276.681695 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31146.590202 # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0 0.057090 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.444973 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 1870.709103 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 14580.888860 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 514805 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34285.718119 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.754123 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 204503 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 10635951500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.602753 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 310297 # number of overall misses
+system.cpu.l2cache.overall_hits 216644 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 10222664000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.579173 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 298161 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 9664693500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.602753 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 310297 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 9287940000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.579173 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 298161 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 84514 # number of replacements
-system.cpu.l2cache.sampled_refs 99965 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 83969 # number of replacements
+system.cpu.l2cache.sampled_refs 99434 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 16401.389748 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 406325 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 16451.597962 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 408237 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 61949 # number of writebacks
-system.cpu.memDep0.conflictingLoads 446168372 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 144446189 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 732453281 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 296886262 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 2177430987 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 18705831 # Number of cycles rename is blocking
+system.cpu.l2cache.writebacks 61561 # number of writebacks
+system.cpu.memDep0.conflictingLoads 445088392 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 142143895 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 732363888 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 296834010 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 2176883008 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 18665128 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1244779258 # Number of HB maps that are committed
-system.cpu.rename.RENAME:FullRegisterEvents 818 # Number of times there has been no free registers
-system.cpu.rename.RENAME:IQFullEvents 29460 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 816810065 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 24399902 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 4 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 4857699412 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 3052479029 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 2393152182 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 700108886 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 233540433 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 34052536 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 1148372924 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 372701478 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 21719371 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 176909620 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 21553732 # count of temporary serializing insts renamed
-system.cpu.timesIdled 44523 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:FullRegisterEvents 724 # Number of times there has been no free registers
+system.cpu.rename.RENAME:IQFullEvents 28925 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 816745640 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 24395596 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 7 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 4856285750 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 3051371057 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 2392375919 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 700064958 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 233579864 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 34053219 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 1147596661 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 372426461 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 21718962 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 176891245 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 21553313 # count of temporary serializing insts renamed
+system.cpu.timesIdled 41709 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
---------- End Simulation Statistics ----------
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
+cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/gzip
+executable=/dist/m5/cpu2000/binaries/sparc/linux/gzip
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Feb 25 2010 03:11:27
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:27:10
-M5 executing on SC2B0619
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/00.gzip/sparc/linux/simple-timing
+M5 compiled Aug 26 2010 13:03:41
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:04:04
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 2076000877000 because target called exit()
+Exiting @ tick 2075400743000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 933241 # Simulator instruction rate (inst/s)
-host_mem_usage 193388 # Number of bytes of host memory used
-host_seconds 1596.08 # Real time elapsed on the host
-host_tick_rate 1300690172 # Simulator tick rate (ticks/s)
+host_inst_rate 1385286 # Simulator instruction rate (inst/s)
+host_mem_usage 211532 # Number of bytes of host memory used
+host_seconds 1075.25 # Real time elapsed on the host
+host_tick_rate 1930162951 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1489523295 # Number of instructions simulated
-sim_seconds 2.076001 # Number of seconds simulated
-sim_ticks 2076000877000 # Number of ticks simulated
+sim_seconds 2.075401 # Number of seconds simulated
+sim_ticks 2075400743000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 402512844 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 21085.380854 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18085.380854 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 21012.879485 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18012.879485 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 402319358 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4079726000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 4065698000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000481 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 193486 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3499268000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 3485240000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 1326 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_hits 1286 # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_rate 0.030166 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_rate 0.030166 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_hits 1308 # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency 1008000 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate 0.013575 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses 18 # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency 954000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate 0.013575 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses 18 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 166846816 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.993742 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.993742 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 166527221 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 17897318000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.001915 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 319595 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 16938533000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.001915 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 319595 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 54403.143945 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51403.143945 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 166528617 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 17311026000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.001907 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 318199 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 16356429000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.001907 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 318199 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 569359660 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 42833.478535 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 39833.478535 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 568846579 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 21977044000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000901 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 513081 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 41777.116781 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 38777.116781 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 568847975 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 21376724000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000899 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 511685 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 20437801000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000901 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 513081 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 19841669000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000899 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 511685 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999812 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4095.229973 # Average occupied blocks per context
+system.cpu.dcache.occ_blocks::0 4095.231029 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 569359660 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 42833.478535 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 39833.478535 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 41777.116781 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 38777.116781 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 568846579 # number of overall hits
-system.cpu.dcache.overall_miss_latency 21977044000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000901 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 513081 # number of overall misses
+system.cpu.dcache.overall_hits 568847975 # number of overall hits
+system.cpu.dcache.overall_miss_latency 21376724000 # number of overall miss cycles
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 20437801000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000901 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 513081 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 19841669000 # number of overall MSHR miss cycles
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+system.cpu.dcache.overall_mshr_misses 511685 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 449125 # number of replacements
system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.229973 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4095.231029 # Cycle average of tags in use
system.cpu.dcache.total_refs 568907765 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 567696000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 316424 # number of writebacks
+system.cpu.dcache.warmup_cycle 567036000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 316439 # number of writebacks
system.cpu.icache.ReadReq_accesses 1485113012 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482 # average ReadReq mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.442585 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 906.413760 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.442593 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 906.429761 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482 # average overall mshr miss latency
system.cpu.icache.replacements 118 # number of replacements
system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 906.413760 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 906.429761 # Cycle average of tags in use
system.cpu.icache.total_refs 1485111905 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 13506220000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 259735 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 10389400000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 259735 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits 12098 # number of ReadExReq hits
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+system.cpu.l2cache.ReadExReq_misses 247637 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 9905480000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.953422 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 247637 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 160849 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1754688000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.173408 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 33744 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1349760000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.173408 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 33744 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 59900 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.263773 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadReq_hits 161183 # number of ReadReq hits
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+system.cpu.l2cache.ReadReq_miss_rate 0.171692 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 33410 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1336400000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.171692 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 33410 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 58482 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51998.221675 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 3114696000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 3040960000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 59900 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2396000000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 58482 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2339280000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 59900 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 316424 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 316424 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_mshr_misses 58482 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 316439 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 316439 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 3.428657 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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-system.cpu.l2cache.demand_miss_latency 15260908000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.645963 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 293479 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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-system.cpu.l2cache.demand_mshr_misses 293479 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.l2cache.occ_%::1 0.447022 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 1710.054315 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 14648.032371 # Average occupied blocks per context
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+system.cpu.l2cache.occ_%::1 0.447533 # Average percentage of cache occupancy
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system.cpu.l2cache.overall_accesses 454328 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 160849 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 15260908000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.645963 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 293479 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 11739160000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.645963 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 293479 # number of overall MSHR misses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 82908 # number of replacements
-system.cpu.l2cache.sampled_refs 98342 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 82461 # number of replacements
+system.cpu.l2cache.sampled_refs 97909 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 16358.086686 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 337181 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 16401.335462 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 337682 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 61864 # number of writebacks
+system.cpu.l2cache.writebacks 61551 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 4152001754 # number of cpu cycles simulated
+system.cpu.numCycles 4150801486 # number of cpu cycles simulated
system.cpu.num_insts 1489523295 # Number of instructions executed
system.cpu.num_refs 569365767 # Number of memory references
system.cpu.workload.PROG:num_syscalls 49 # Number of system calls
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
+cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
egid=100
env=
errout=cerr
+Redirecting stdout to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled May 2 2010 23:23:01
-M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
-M5 started May 2 2010 23:23:02
-M5 executing on burrito
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/00.gzip/x86/linux/simple-timing
+M5 compiled Aug 26 2010 13:20:12
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:33:02
+M5 executing on zizzer
+command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 1814725999000 because target called exit()
+Exiting @ tick 1814105620000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 1830893 # Simulator instruction rate (inst/s)
-host_mem_usage 225176 # Number of bytes of host memory used
-host_seconds 884.47 # Real time elapsed on the host
-host_tick_rate 2051770366 # Simulator tick rate (ticks/s)
+host_inst_rate 1308474 # Simulator instruction rate (inst/s)
+host_mem_usage 210192 # Number of bytes of host memory used
+host_seconds 1237.60 # Real time elapsed on the host
+host_tick_rate 1465826235 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1619366787 # Number of instructions simulated
-sim_seconds 1.814726 # Number of seconds simulated
-sim_ticks 1814725999000 # Number of ticks simulated
+sim_seconds 1.814106 # Number of seconds simulated
+sim_ticks 1814105620000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 419042125 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 20886.624165 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17886.624165 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 20817.236451 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17817.236451 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 418844799 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4121474000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 4107782000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 197326 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3529496000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 3515804000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 197326 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 187876653 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 17326624000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.001644 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 309404 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 16398412000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.001644 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 309404 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 54292.890290 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51292.890290 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 187878126 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 16718464000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.001636 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 307931 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 15794671000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.001636 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 307931 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 607228182 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 42326.481558 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 39326.481558 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 606721452 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 21448098000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000834 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 506730 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 41219.114233 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 38219.114233 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 606722925 # number of demand (read+write) hits
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+system.cpu.dcache.demand_miss_rate 0.000832 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 505257 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 19927908000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000834 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 506730 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 19310475000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000832 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 505257 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999732 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4094.901606 # Average occupied blocks per context
+system.cpu.dcache.occ_blocks::0 4094.903534 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 42326.481558 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 39326.481558 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 41219.114233 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 38219.114233 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 606721452 # number of overall hits
-system.cpu.dcache.overall_miss_latency 21448098000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000834 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 506730 # number of overall misses
+system.cpu.dcache.overall_hits 606722925 # number of overall hits
+system.cpu.dcache.overall_miss_latency 20826246000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000832 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 505257 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 19927908000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000834 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 506730 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 19310475000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000832 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 505257 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 437952 # number of replacements
system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4094.901606 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4094.903534 # Cycle average of tags in use
system.cpu.dcache.total_refs 606786134 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 779585000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 306191 # number of writebacks
+system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 306200 # number of writebacks
system.cpu.icache.ReadReq_accesses 1186516740 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.322346 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 660.164839 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.322353 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 660.178535 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.replacements 4 # number of replacements
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 660.164839 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 660.178535 # Cycle average of tags in use
system.cpu.icache.total_refs 1186516018 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadExReq_accesses 244722 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 12725544000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 244722 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 9788880000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 244722 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits 12516 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 12074712000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.948856 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 232206 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 9288240000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.948856 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 232206 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 198048 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 164971 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1720004000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.167015 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 33077 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1323080000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.167015 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 33077 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 64682 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_hits 165297 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1703052000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.165369 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 32751 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1310040000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165369 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 32751 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 63209 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 3363464000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 3286868000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 64682 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2587280000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 63209 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 2528360000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 64682 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 306191 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 306191 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_mshr_misses 63209 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 306200 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 306200 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 3.428492 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 3.450731 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 442770 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 164971 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 14445548000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.627412 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 277799 # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits 177813 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 13777764000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.598408 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 264957 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 11111960000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.627412 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 277799 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 10598280000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.598408 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 264957 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.052754 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.452175 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 1728.633036 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 14816.859075 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.053631 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.452717 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 1757.366037 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 14834.623829 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 164971 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 14445548000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.627412 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 277799 # number of overall misses
+system.cpu.l2cache.overall_hits 177813 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 13777764000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.598408 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 264957 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 11111960000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.627412 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 277799 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 10598280000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.598408 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 264957 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 81557 # number of replacements
-system.cpu.l2cache.sampled_refs 97073 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 81078 # number of replacements
+system.cpu.l2cache.sampled_refs 96612 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 16545.492111 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 332814 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 16591.989866 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 333382 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 61569 # number of writebacks
+system.cpu.l2cache.writebacks 61253 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 3629451998 # number of cpu cycles simulated
+system.cpu.numCycles 3628211240 # number of cpu cycles simulated
system.cpu.num_insts 1619366787 # Number of instructions executed
system.cpu.num_refs 607228182 # Number of memory references
system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/home/stever/m5/m5_system_2.0b3/binaries/console
+console=/dist/m5/system/binaries/console
init_param=0
-kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
+load_addr_mask=1099511627775
mem_mode=timing
-pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
+pal=/dist/m5/system/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
[system.disk0.image.child]
type=RawDiskImage
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.terminal]
+Redirecting stdout to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
+Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Aug 3 2010 18:29:42
-M5 revision 75205c286109 7549 default qtip tip ext/memorderviolation_uncached.patch
-M5 started Aug 3 2010 18:34:19
-M5 executing on harpertown2
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual
+M5 compiled Aug 26 2010 12:51:14
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 12:51:16
+M5 executing on zizzer
+command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /root/ali/dist/system/m5_system_2.0b3/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
+ 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-info: Launching CPU 1 @ 125751000
-Exiting @ tick 1908681362500 because m5_exit instruction encountered
+info: Launching CPU 1 @ 125480500
+Exiting @ tick 1906675009500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 149891 # Simulator instruction rate (inst/s)
-host_mem_usage 287008 # Number of bytes of host memory used
-host_seconds 374.37 # Real time elapsed on the host
-host_tick_rate 5098345411 # Simulator tick rate (ticks/s)
+host_inst_rate 96877 # Simulator instruction rate (inst/s)
+host_mem_usage 294552 # Number of bytes of host memory used
+host_seconds 589.85 # Real time elapsed on the host
+host_tick_rate 3232468675 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 56115151 # Number of instructions simulated
-sim_seconds 1.908681 # Number of seconds simulated
-sim_ticks 1908681362500 # Number of ticks simulated
+sim_insts 57142904 # Number of instructions simulated
+sim_seconds 1.906675 # Number of seconds simulated
+sim_ticks 1906675009500 # Number of ticks simulated
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.BTBHits 6470772 # Number of BTB hits
-system.cpu0.BPredUnit.BTBLookups 12459992 # Number of BTB lookups
-system.cpu0.BPredUnit.RASInCorrect 36652 # Number of incorrect RAS predictions.
-system.cpu0.BPredUnit.condIncorrect 761921 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.condPredicted 11628226 # Number of conditional branches predicted
-system.cpu0.BPredUnit.lookups 13936368 # Number of BP lookups
-system.cpu0.BPredUnit.usedRAS 988790 # Number of times the RAS was used to get a target.
-system.cpu0.commit.COM:branches 8127927 # Number of branches committed
-system.cpu0.commit.COM:bw_lim_events 948928 # number cycles where commit BW limit reached
+system.cpu0.BPredUnit.BTBHits 6037320 # Number of BTB hits
+system.cpu0.BPredUnit.BTBLookups 11351967 # Number of BTB lookups
+system.cpu0.BPredUnit.RASInCorrect 27838 # Number of incorrect RAS predictions.
+system.cpu0.BPredUnit.condIncorrect 689824 # Number of conditional branches incorrect
+system.cpu0.BPredUnit.condPredicted 10583458 # Number of conditional branches predicted
+system.cpu0.BPredUnit.lookups 12665096 # Number of BP lookups
+system.cpu0.BPredUnit.usedRAS 889173 # Number of times the RAS was used to get a target.
+system.cpu0.commit.COM:branches 7532122 # Number of branches committed
+system.cpu0.commit.COM:bw_lim_events 868474 # number cycles where commit BW limit reached
system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.commit.COM:committed_per_cycle::samples 96210525 # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::mean 0.559994 # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::stdev 1.324793 # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::samples 85531488 # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::mean 0.582160 # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::stdev 1.346009 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::0 73079830 75.96% 75.96% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::1 10159186 10.56% 86.52% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::2 5793964 6.02% 92.54% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::3 2862156 2.97% 95.51% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::4 1992019 2.07% 97.59% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::5 630403 0.66% 98.24% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::6 376031 0.39% 98.63% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::7 368008 0.38% 99.01% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::8 948928 0.99% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::0 64118131 74.96% 74.96% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::1 9419985 11.01% 85.98% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::2 5464530 6.39% 92.37% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::3 2511151 2.94% 95.30% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::4 1836761 2.15% 97.45% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::5 609168 0.71% 98.16% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::6 353146 0.41% 98.58% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::7 350142 0.41% 98.98% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::8 868474 1.02% 100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::total 96210525 # Number of insts commited each cycle
-system.cpu0.commit.COM:count 53877339 # Number of instructions committed
-system.cpu0.commit.COM:loads 8834098 # Number of loads committed
-system.cpu0.commit.COM:membars 219262 # Number of memory barriers committed
-system.cpu0.commit.COM:refs 14863142 # Number of memory references committed
+system.cpu0.commit.COM:committed_per_cycle::total 85531488 # Number of insts commited each cycle
+system.cpu0.commit.COM:count 49793044 # Number of instructions committed
+system.cpu0.commit.COM:loads 8087035 # Number of loads committed
+system.cpu0.commit.COM:membars 188923 # Number of memory barriers committed
+system.cpu0.commit.COM:refs 13499415 # Number of memory references committed
system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.branchMispredicts 723488 # The number of times a branch was mispredicted
-system.cpu0.commit.commitCommittedInsts 53877339 # The number of committed instructions
-system.cpu0.commit.commitNonSpecStalls 642718 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.commitSquashedInsts 8676299 # The number of squashed insts skipped by commit
-system.cpu0.committedInsts 50753913 # Number of Instructions Simulated
-system.cpu0.committedInsts_total 50753913 # Number of Instructions Simulated
-system.cpu0.cpi 2.598475 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.598475 # CPI: Total CPI of All Threads
-system.cpu0.dcache.LoadLockedReq_accesses::0 205122 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 205122 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15332.515478 # average LoadLockedReq miss latency
+system.cpu0.commit.branchMispredicts 656667 # The number of times a branch was mispredicted
+system.cpu0.commit.commitCommittedInsts 49793044 # The number of committed instructions
+system.cpu0.commit.commitNonSpecStalls 558254 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.commitSquashedInsts 7909295 # The number of squashed insts skipped by commit
+system.cpu0.committedInsts 46950766 # Number of Instructions Simulated
+system.cpu0.committedInsts_total 46950766 # Number of Instructions Simulated
+system.cpu0.cpi 2.557983 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.557983 # CPI: Total CPI of All Threads
+system.cpu0.dcache.LoadLockedReq_accesses::0 175325 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 175325 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 13891.838160 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11584.904538 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_hits::0 183317 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 183317 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_miss_latency 334325500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.106303 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses::0 21805 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 21805 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_mshr_hits 4992 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 194777000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.081966 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10378.791946 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_hits::0 156714 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 156714 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_miss_latency 258541000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.106151 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses::0 18611 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 18611 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_mshr_hits 3711 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 154644000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084985 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_misses 16813 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.ReadReq_accesses::0 8824783 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 8824783 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency::0 24295.121423 # average ReadReq miss latency
+system.cpu0.dcache.LoadLockedReq_mshr_misses 14900 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.ReadReq_accesses::0 8024582 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 8024582 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency::0 24823.193475 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23079.908159 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23777.445948 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_hits::0 7389262 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 7389262 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency 34876157000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate::0 0.162669 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses::0 1435521 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 1435521 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_hits 389370 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_miss_latency 24145069000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.118547 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_hits::0 6693712 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 6693712 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_latency 33036443500 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_rate::0 0.165849 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses::0 1330870 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 1330870 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_mshr_hits 349277 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_miss_latency 23339774500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122323 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses 1046151 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 922902000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.StoreCondReq_accesses::0 210601 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 210601 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 55488.433658 # average StoreCondReq miss latency
+system.cpu0.dcache.ReadReq_mshr_misses 981593 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 922661000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_accesses::0 183239 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 183239 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 47093.631014 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52488.433658 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_hits::0 182459 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 182459 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_latency 1561555500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_rate::0 0.133627 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_misses::0 28142 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 28142 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1477129500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.133627 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 44096.203773 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_hits::0 165905 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 165905 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_miss_latency 816321000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_rate::0 0.094598 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_misses::0 17334 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 17334 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency 764319500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.094592 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_misses 28142 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses::0 5803460 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 5803460 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency::0 48954.080777 # average WriteReq miss latency
+system.cpu0.dcache.StoreCondReq_mshr_misses 17333 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.WriteReq_accesses::0 5213801 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 5213801 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_avg_miss_latency::0 48517.051427 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 54100.546465 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53069.050136 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_hits::0 3719396 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 3719396 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency 102023437400 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate::0 0.359107 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses::0 2084064 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 2084064 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_hits 1707487 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_miss_latency 20373021486 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.064888 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_hits::0 3350446 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 3350446 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency 90404490361 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate::0 0.357389 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses::0 1863355 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 1863355 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_hits 1547991 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_miss_latency 16736067927 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.060486 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses 376577 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1266172497 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9947.496514 # average number of cycles each access was blocked
+system.cpu0.dcache.WriteReq_mshr_misses 315364 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1337193497 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9713.605174 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs 8.716740 # Average number of references to valid blocks.
-system.cpu0.dcache.blocked::no_mshrs 127068 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_mshrs 1264008487 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 150500 # number of cycles access was blocked
+system.cpu0.dcache.avg_refs 8.464502 # Average number of references to valid blocks.
+system.cpu0.dcache.blocked::no_mshrs 124903 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 6 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_mshrs 1213258427 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 129000 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.demand_accesses::0 14628243 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::0 13238383 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 14628243 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency::0 38896.516038 # average overall miss latency
+system.cpu0.dcache.demand_accesses::total 13238383 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency::0 38645.034041 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 31290.654634 # average overall mshr miss latency
-system.cpu0.dcache.demand_hits::0 11108658 # number of demand (read+write) hits
+system.cpu0.dcache.demand_avg_mshr_miss_latency 30899.900634 # average overall mshr miss latency
+system.cpu0.dcache.demand_hits::0 10044158 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 11108658 # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency 136899594400 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate::0 0.240602 # miss rate for demand accesses
+system.cpu0.dcache.demand_hits::total 10044158 # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency 123440933861 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate::0 0.241285 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu0.dcache.demand_misses::0 3519585 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::0 3194225 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 3519585 # number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits 2096857 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency 44518090486 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate::0 0.097259 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_misses::total 3194225 # number of demand (read+write) misses
+system.cpu0.dcache.demand_mshr_hits 1897268 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_miss_latency 40075842427 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate::0 0.097969 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses 1422728 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses 1296957 # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0 0.984997 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_%::1 -0.015306 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_blocks::0 504.318463 # Average occupied blocks per context
-system.cpu0.dcache.occ_blocks::1 -7.836780 # Average occupied blocks per context
-system.cpu0.dcache.overall_accesses::0 14628243 # number of overall (read+write) accesses
+system.cpu0.dcache.occ_%::0 0.975170 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_%::1 -0.005787 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_blocks::0 499.286946 # Average occupied blocks per context
+system.cpu0.dcache.occ_blocks::1 -2.962988 # Average occupied blocks per context
+system.cpu0.dcache.overall_accesses::0 13238383 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 14628243 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency::0 38896.516038 # average overall miss latency
+system.cpu0.dcache.overall_accesses::total 13238383 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency::0 38645.034041 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 31290.654634 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 30899.900634 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits::0 11108658 # number of overall hits
+system.cpu0.dcache.overall_hits::0 10044158 # number of overall hits
system.cpu0.dcache.overall_hits::1 0 # number of overall hits
-system.cpu0.dcache.overall_hits::total 11108658 # number of overall hits
-system.cpu0.dcache.overall_miss_latency 136899594400 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate::0 0.240602 # miss rate for overall accesses
+system.cpu0.dcache.overall_hits::total 10044158 # number of overall hits
+system.cpu0.dcache.overall_miss_latency 123440933861 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate::0 0.241285 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu0.dcache.overall_misses::0 3519585 # number of overall misses
+system.cpu0.dcache.overall_misses::0 3194225 # number of overall misses
system.cpu0.dcache.overall_misses::1 0 # number of overall misses
-system.cpu0.dcache.overall_misses::total 3519585 # number of overall misses
-system.cpu0.dcache.overall_mshr_hits 2096857 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency 44518090486 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate::0 0.097259 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_misses::total 3194225 # number of overall misses
+system.cpu0.dcache.overall_mshr_hits 1897268 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_miss_latency 40075842427 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate::0 0.097969 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses 1422728 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency 2189074497 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_misses 1296957 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_latency 2259854497 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.replacements 1343392 # number of replacements
-system.cpu0.dcache.sampled_refs 1343785 # Sample count of references to valid blocks.
+system.cpu0.dcache.replacements 1243005 # number of replacements
+system.cpu0.dcache.sampled_refs 1243517 # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse 500.400077 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 11713425 # Total number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 21394000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks 404610 # number of writebacks
-system.cpu0.decode.DECODE:BlockedCycles 46313195 # Number of cycles decode is blocked
-system.cpu0.decode.DECODE:BranchMispred 39259 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DECODE:BranchResolved 576703 # Number of times decode resolved a branch
-system.cpu0.decode.DECODE:DecodedInsts 69095576 # Number of instructions handled by decode
-system.cpu0.decode.DECODE:IdleCycles 36458125 # Number of cycles decode is idle
-system.cpu0.decode.DECODE:RunCycles 12314815 # Number of cycles decode is running
-system.cpu0.decode.DECODE:SquashCycles 1498947 # Number of cycles decode is squashing
-system.cpu0.decode.DECODE:SquashedInsts 124799 # Number of squashed instructions handled by decode
-system.cpu0.decode.DECODE:UnblockCycles 1124389 # Number of cycles decode is unblocking
-system.cpu0.dtb.data_accesses 818221 # DTB accesses
-system.cpu0.dtb.data_acv 799 # DTB access violations
-system.cpu0.dtb.data_hits 15815368 # DTB hits
-system.cpu0.dtb.data_misses 34536 # DTB misses
+system.cpu0.dcache.tagsinuse 497.305455 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 10525752 # Total number of references to valid blocks.
+system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.writebacks 379678 # number of writebacks
+system.cpu0.decode.DECODE:BlockedCycles 40702182 # Number of cycles decode is blocked
+system.cpu0.decode.DECODE:BranchMispred 33733 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DECODE:BranchResolved 526303 # Number of times decode resolved a branch
+system.cpu0.decode.DECODE:DecodedInsts 63705520 # Number of instructions handled by decode
+system.cpu0.decode.DECODE:IdleCycles 32342676 # Number of cycles decode is idle
+system.cpu0.decode.DECODE:RunCycles 11446881 # Number of cycles decode is running
+system.cpu0.decode.DECODE:SquashCycles 1370864 # Number of cycles decode is squashing
+system.cpu0.decode.DECODE:SquashedInsts 100557 # Number of squashed instructions handled by decode
+system.cpu0.decode.DECODE:UnblockCycles 1039748 # Number of cycles decode is unblocking
+system.cpu0.dtb.data_accesses 867376 # DTB accesses
+system.cpu0.dtb.data_acv 796 # DTB access violations
+system.cpu0.dtb.data_hits 14352894 # DTB hits
+system.cpu0.dtb.data_misses 32526 # DTB misses
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
-system.cpu0.dtb.read_accesses 609919 # DTB read accesses
-system.cpu0.dtb.read_acv 595 # DTB read access violations
-system.cpu0.dtb.read_hits 9601809 # DTB read hits
-system.cpu0.dtb.read_misses 28742 # DTB read misses
-system.cpu0.dtb.write_accesses 208302 # DTB write accesses
-system.cpu0.dtb.write_acv 204 # DTB write access violations
-system.cpu0.dtb.write_hits 6213559 # DTB write hits
-system.cpu0.dtb.write_misses 5794 # DTB write misses
-system.cpu0.fetch.Branches 13936368 # Number of branches that fetch encountered
-system.cpu0.fetch.CacheLines 8499965 # Number of cache lines fetched
-system.cpu0.fetch.Cycles 22177505 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.IcacheSquashes 429825 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.Insts 70536565 # Number of instructions fetch has processed
-system.cpu0.fetch.MiscStallCycles 1947 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.SquashCycles 890409 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.branchRate 0.105672 # Number of branch fetches per cycle
-system.cpu0.fetch.icacheStallCycles 8499965 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.predictedBranches 7459562 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.rate 0.534843 # Number of inst fetches per cycle
-system.cpu0.fetch.rateDist::samples 97709472 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.721901 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.017707 # Number of instructions fetched each cycle (Total)
+system.cpu0.dtb.read_accesses 645773 # DTB read accesses
+system.cpu0.dtb.read_acv 589 # DTB read access violations
+system.cpu0.dtb.read_hits 8766713 # DTB read hits
+system.cpu0.dtb.read_misses 26860 # DTB read misses
+system.cpu0.dtb.write_accesses 221603 # DTB write accesses
+system.cpu0.dtb.write_acv 207 # DTB write access violations
+system.cpu0.dtb.write_hits 5586181 # DTB write hits
+system.cpu0.dtb.write_misses 5666 # DTB write misses
+system.cpu0.fetch.Branches 12665096 # Number of branches that fetch encountered
+system.cpu0.fetch.CacheLines 7900913 # Number of cache lines fetched
+system.cpu0.fetch.Cycles 20614864 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.IcacheSquashes 378846 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.Insts 65028610 # Number of instructions fetch has processed
+system.cpu0.fetch.MiscStallCycles 1156 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.SquashCycles 811969 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.branchRate 0.105455 # Number of branch fetches per cycle
+system.cpu0.fetch.icacheStallCycles 7900913 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.predictedBranches 6926493 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.rate 0.541457 # Number of inst fetches per cycle
+system.cpu0.fetch.rateDist::samples 86902352 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.748295 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.044395 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 84062445 86.03% 86.03% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 970614 0.99% 87.03% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 1876169 1.92% 88.95% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 899130 0.92% 89.87% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 2879231 2.95% 92.81% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 630716 0.65% 93.46% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 762992 0.78% 94.24% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 1157633 1.18% 95.42% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4470542 4.58% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 74220009 85.41% 85.41% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 901339 1.04% 86.44% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 1804427 2.08% 88.52% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 827724 0.95% 89.47% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 2764395 3.18% 92.65% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 592140 0.68% 93.33% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 693087 0.80% 94.13% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 935405 1.08% 95.21% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4163826 4.79% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 97709472 # Number of instructions fetched each cycle (Total)
-system.cpu0.icache.ReadReq_accesses::0 8499965 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 8499965 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency::0 14903.591508 # average ReadReq miss latency
+system.cpu0.fetch.rateDist::total 86902352 # Number of instructions fetched each cycle (Total)
+system.cpu0.icache.ReadReq_accesses::0 7900913 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 7900913 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_avg_miss_latency::0 15047.285683 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11868.979380 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_hits::0 7487466 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 7487466 # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_latency 15089871498 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_rate::0 0.119118 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses::0 1012499 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 1012499 # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_hits 44617 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_miss_latency 11487771500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.113869 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12005.143233 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_hits::0 7053204 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 7053204 # number of ReadReq hits
+system.cpu0.icache.ReadReq_miss_latency 12755719499 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_rate::0 0.107293 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_misses::0 847709 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 847709 # number of ReadReq misses
+system.cpu0.icache.ReadReq_mshr_hits 37907 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_miss_latency 9721789000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.102495 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_misses 967882 # number of ReadReq MSHR misses
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 11795.081967 # average number of cycles each access was blocked
+system.cpu0.icache.ReadReq_mshr_misses 809802 # number of ReadReq MSHR misses
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 11235.849057 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs 7.736856 # Average number of references to valid blocks.
-system.cpu0.icache.blocked::no_mshrs 61 # number of cycles access was blocked
+system.cpu0.icache.avg_refs 8.711370 # Average number of references to valid blocks.
+system.cpu0.icache.blocked::no_mshrs 53 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_mshrs 719500 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_mshrs 595500 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.demand_accesses::0 8499965 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::0 7900913 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 8499965 # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency::0 14903.591508 # average overall miss latency
+system.cpu0.icache.demand_accesses::total 7900913 # number of demand (read+write) accesses
+system.cpu0.icache.demand_avg_miss_latency::0 15047.285683 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 11868.979380 # average overall mshr miss latency
-system.cpu0.icache.demand_hits::0 7487466 # number of demand (read+write) hits
+system.cpu0.icache.demand_avg_mshr_miss_latency 12005.143233 # average overall mshr miss latency
+system.cpu0.icache.demand_hits::0 7053204 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 7487466 # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency 15089871498 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate::0 0.119118 # miss rate for demand accesses
+system.cpu0.icache.demand_hits::total 7053204 # number of demand (read+write) hits
+system.cpu0.icache.demand_miss_latency 12755719499 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_rate::0 0.107293 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu0.icache.demand_misses::0 1012499 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::0 847709 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 1012499 # number of demand (read+write) misses
-system.cpu0.icache.demand_mshr_hits 44617 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency 11487771500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate::0 0.113869 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_misses::total 847709 # number of demand (read+write) misses
+system.cpu0.icache.demand_mshr_hits 37907 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_miss_latency 9721789000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_rate::0 0.102495 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses 967882 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses 809802 # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.occ_%::0 0.995784 # Average percentage of cache occupancy
-system.cpu0.icache.occ_blocks::0 509.841410 # Average occupied blocks per context
-system.cpu0.icache.overall_accesses::0 8499965 # number of overall (read+write) accesses
+system.cpu0.icache.occ_%::0 0.995703 # Average percentage of cache occupancy
+system.cpu0.icache.occ_blocks::0 509.799701 # Average occupied blocks per context
+system.cpu0.icache.overall_accesses::0 7900913 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 8499965 # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency::0 14903.591508 # average overall miss latency
+system.cpu0.icache.overall_accesses::total 7900913 # number of overall (read+write) accesses
+system.cpu0.icache.overall_avg_miss_latency::0 15047.285683 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 11868.979380 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 12005.143233 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits::0 7487466 # number of overall hits
+system.cpu0.icache.overall_hits::0 7053204 # number of overall hits
system.cpu0.icache.overall_hits::1 0 # number of overall hits
-system.cpu0.icache.overall_hits::total 7487466 # number of overall hits
-system.cpu0.icache.overall_miss_latency 15089871498 # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate::0 0.119118 # miss rate for overall accesses
+system.cpu0.icache.overall_hits::total 7053204 # number of overall hits
+system.cpu0.icache.overall_miss_latency 12755719499 # number of overall miss cycles
+system.cpu0.icache.overall_miss_rate::0 0.107293 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu0.icache.overall_misses::0 1012499 # number of overall misses
+system.cpu0.icache.overall_misses::0 847709 # number of overall misses
system.cpu0.icache.overall_misses::1 0 # number of overall misses
-system.cpu0.icache.overall_misses::total 1012499 # number of overall misses
-system.cpu0.icache.overall_mshr_hits 44617 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency 11487771500 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate::0 0.113869 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_misses::total 847709 # number of overall misses
+system.cpu0.icache.overall_mshr_hits 37907 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_miss_latency 9721789000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_rate::0 0.102495 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses 967882 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses 809802 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.replacements 967254 # number of replacements
-system.cpu0.icache.sampled_refs 967766 # Sample count of references to valid blocks.
+system.cpu0.icache.replacements 809144 # number of replacements
+system.cpu0.icache.sampled_refs 809655 # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse 509.841410 # Cycle average of tags in use
-system.cpu0.icache.total_refs 7487466 # Total number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 25290449000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.writebacks 0 # number of writebacks
-system.cpu0.idleCycles 34173281 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.iew.EXEC:branches 8768783 # Number of branches executed
-system.cpu0.iew.EXEC:nop 3557044 # number of nop insts executed
-system.cpu0.iew.EXEC:rate 0.415997 # Inst execution rate
-system.cpu0.iew.EXEC:refs 16085074 # number of memory reference insts executed
-system.cpu0.iew.EXEC:stores 6233455 # Number of stores executed
+system.cpu0.icache.tagsinuse 509.799701 # Cycle average of tags in use
+system.cpu0.icache.total_refs 7053204 # Total number of references to valid blocks.
+system.cpu0.icache.warmup_cycle 25253244000 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.writebacks 2 # number of writebacks
+system.cpu0.idleCycles 33196891 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.iew.EXEC:branches 8125364 # Number of branches executed
+system.cpu0.iew.EXEC:nop 3226641 # number of nop insts executed
+system.cpu0.iew.EXEC:rate 0.422366 # Inst execution rate
+system.cpu0.iew.EXEC:refs 14615271 # number of memory reference insts executed
+system.cpu0.iew.EXEC:stores 5604883 # Number of stores executed
system.cpu0.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu0.iew.WB:consumers 32865773 # num instructions consuming a value
-system.cpu0.iew.WB:count 54347309 # cumulative count of insts written-back
-system.cpu0.iew.WB:fanout 0.764091 # average fanout of values written-back
+system.cpu0.iew.WB:consumers 31032245 # num instructions consuming a value
+system.cpu0.iew.WB:count 50227097 # cumulative count of insts written-back
+system.cpu0.iew.WB:fanout 0.763961 # average fanout of values written-back
system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.iew.WB:producers 25112440 # num instructions producing a value
-system.cpu0.iew.WB:rate 0.412088 # insts written-back per cycle
-system.cpu0.iew.WB:sent 54432899 # cumulative count of insts sent to commit
-system.cpu0.iew.branchMispredicts 782239 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewBlockCycles 9442019 # Number of cycles IEW is blocking
-system.cpu0.iew.iewDispLoadInsts 10379600 # Number of dispatched load instructions
-system.cpu0.iew.iewDispNonSpecInsts 1744642 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewDispSquashedInsts 949306 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispStoreInsts 6581023 # Number of dispatched store instructions
-system.cpu0.iew.iewDispatchedInsts 62660146 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewExecLoadInsts 9851619 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 507857 # Number of squashed instructions skipped in execute
-system.cpu0.iew.iewExecutedInsts 54862889 # Number of executed instructions
-system.cpu0.iew.iewIQFullEvents 45824 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.WB:producers 23707433 # num instructions producing a value
+system.cpu0.iew.WB:rate 0.418213 # insts written-back per cycle
+system.cpu0.iew.WB:sent 50304093 # cumulative count of insts sent to commit
+system.cpu0.iew.branchMispredicts 713455 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewBlockCycles 9315247 # Number of cycles IEW is blocking
+system.cpu0.iew.iewDispLoadInsts 9510497 # Number of dispatched load instructions
+system.cpu0.iew.iewDispNonSpecInsts 1499135 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewDispSquashedInsts 880070 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispStoreInsts 5918886 # Number of dispatched store instructions
+system.cpu0.iew.iewDispatchedInsts 57821470 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewExecLoadInsts 9010388 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 501816 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewExecutedInsts 50725864 # Number of executed instructions
+system.cpu0.iew.iewIQFullEvents 38579 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewLSQFullEvents 5354 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.iewSquashCycles 1498947 # Number of cycles IEW is squashing
-system.cpu0.iew.iewUnblockCycles 539585 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewLSQFullEvents 5036 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.iewSquashCycles 1370864 # Number of cycles IEW is squashing
+system.cpu0.iew.iewUnblockCycles 530507 # Number of cycles IEW is unblocking
system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread.0.cacheBlocked 260747 # Number of times an access to memory failed due to the cache being blocked
-system.cpu0.iew.lsq.thread.0.forwLoads 417328 # Number of loads that had data forwarded from stores
-system.cpu0.iew.lsq.thread.0.ignoredResponses 12574 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread.0.cacheBlocked 262065 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread.0.forwLoads 407910 # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread.0.ignoredResponses 13281 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu0.iew.lsq.thread.0.memOrderViolation 44391 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread.0.rescheduledLoads 18291 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread.0.squashedLoads 1545502 # Number of loads squashed
-system.cpu0.iew.lsq.thread.0.squashedStores 551979 # Number of stores squashed
-system.cpu0.iew.memOrderViolationEvents 44391 # Number of memory order violations
-system.cpu0.iew.predictedNotTakenIncorrect 381079 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.predictedTakenIncorrect 401160 # Number of branches that were predicted taken incorrectly
-system.cpu0.ipc 0.384841 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.384841 # IPC: Total IPC of All Threads
-system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3316 0.01% 0.01% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntAlu 37941800 68.52% 68.53% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntMult 60296 0.11% 68.64% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15720 0.03% 68.67% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.67% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.67% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.67% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1656 0.00% 68.67% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.67% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::MemRead 10184712 18.39% 87.06% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::MemWrite 6276896 11.34% 98.40% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::IprAccess 886350 1.60% 100.00% # Type of FU issued
+system.cpu0.iew.lsq.thread.0.memOrderViolation 40793 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread.0.rescheduledLoads 18036 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread.0.squashedLoads 1423462 # Number of loads squashed
+system.cpu0.iew.lsq.thread.0.squashedStores 506506 # Number of stores squashed
+system.cpu0.iew.memOrderViolationEvents 40793 # Number of memory order violations
+system.cpu0.iew.predictedNotTakenIncorrect 332881 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.predictedTakenIncorrect 380574 # Number of branches that were predicted taken incorrectly
+system.cpu0.ipc 0.390933 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.390933 # IPC: Total IPC of All Threads
+system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3770 0.01% 0.01% # Type of FU issued
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+system.cpu0.iq.ISSUE:FU_type_0::IntMult 55798 0.11% 69.21% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 69.21% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15086 0.03% 69.24% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 69.24% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 69.24% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 69.24% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1884 0.00% 69.24% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 69.24% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::MemRead 9327899 18.21% 87.45% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5645566 11.02% 98.47% # Type of FU issued
+system.cpu0.iq.ISSUE:FU_type_0::IprAccess 782961 1.53% 100.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.ISSUE:FU_type_0::total 55370746 # Type of FU issued
-system.cpu0.iq.ISSUE:fu_busy_cnt 397277 # FU busy when requested
-system.cpu0.iq.ISSUE:fu_busy_rate 0.007175 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.ISSUE:FU_type_0::total 51227682 # Type of FU issued
+system.cpu0.iq.ISSUE:fu_busy_cnt 363911 # FU busy when requested
+system.cpu0.iq.ISSUE:fu_busy_rate 0.007104 # FU busy rate (busy events/executed inst)
system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IntAlu 49080 12.35% 12.35% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 12.35% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 12.35% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 12.35% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 12.35% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 12.35% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 12.35% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 12.35% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 12.35% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::MemRead 256090 64.46% 76.82% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:fu_full::MemWrite 92107 23.18% 100.00% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::IntAlu 39751 10.92% 10.92% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.92% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.92% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.92% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.92% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.92% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.92% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.92% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.92% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::MemRead 236746 65.06% 75.98% # attempts to use FU when none available
+system.cpu0.iq.ISSUE:fu_full::MemWrite 87414 24.02% 100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:issued_per_cycle::samples 97709472 # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.566688 # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.134817 # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::samples 86902352 # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.589486 # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.157706 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::0 70054320 71.70% 71.70% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::1 13865334 14.19% 85.89% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::2 6040088 6.18% 92.07% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::3 3813933 3.90% 95.97% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::4 2397035 2.45% 98.43% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::5 977877 1.00% 99.43% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::6 439666 0.45% 99.88% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::7 101836 0.10% 99.98% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::8 19383 0.02% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::0 61545337 70.82% 70.82% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::1 12554046 14.45% 85.27% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::2 5586431 6.43% 91.70% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::3 3486187 4.01% 95.71% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::4 2264793 2.61% 98.31% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::5 945170 1.09% 99.40% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::6 407098 0.47% 99.87% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::7 91717 0.11% 99.98% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::8 21573 0.02% 100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::total 97709472 # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:rate 0.419848 # Inst issue rate
-system.cpu0.iq.iqInstsAdded 57116410 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqInstsIssued 55370746 # Number of instructions issued
-system.cpu0.iq.iqNonSpecInstsAdded 1986692 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqSquashedInstsExamined 7999373 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedInstsIssued 32356 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedNonSpecRemoved 1343974 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.iqSquashedOperandsExamined 4128104 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.ISSUE:issued_per_cycle::total 86902352 # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:rate 0.426545 # Inst issue rate
+system.cpu0.iq.iqInstsAdded 52886391 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqInstsIssued 51227682 # Number of instructions issued
+system.cpu0.iq.iqNonSpecInstsAdded 1708438 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqSquashedInstsExamined 7322246 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedInstsIssued 33660 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedNonSpecRemoved 1150184 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.iqSquashedOperandsExamined 3910877 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_hits 0 # DTB hits
system.cpu0.itb.data_misses 0 # DTB misses
-system.cpu0.itb.fetch_accesses 1054719 # ITB accesses
-system.cpu0.itb.fetch_acv 886 # ITB acv
-system.cpu0.itb.fetch_hits 1025087 # ITB hits
-system.cpu0.itb.fetch_misses 29632 # ITB misses
+system.cpu0.itb.fetch_accesses 999568 # ITB accesses
+system.cpu0.itb.fetch_acv 893 # ITB acv
+system.cpu0.itb.fetch_hits 968847 # ITB hits
+system.cpu0.itb.fetch_misses 30721 # ITB misses
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu0.kern.callpal::wripir 98 0.05% 0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrmces 1 0.00% 0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrfen 1 0.00% 0.05% # number of callpals executed
-system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.05% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 3879 2.08% 2.14% # number of callpals executed
-system.cpu0.kern.callpal::tbi 51 0.03% 2.16% # number of callpals executed
-system.cpu0.kern.callpal::wrent 7 0.00% 2.17% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 170561 91.53% 93.70% # number of callpals executed
-system.cpu0.kern.callpal::rdps 6398 3.43% 97.13% # number of callpals executed
-system.cpu0.kern.callpal::wrkgp 1 0.00% 97.13% # number of callpals executed
-system.cpu0.kern.callpal::wrusp 3 0.00% 97.13% # number of callpals executed
-system.cpu0.kern.callpal::rdusp 9 0.00% 97.14% # number of callpals executed
-system.cpu0.kern.callpal::whami 2 0.00% 97.14% # number of callpals executed
-system.cpu0.kern.callpal::rti 4815 2.58% 99.72% # number of callpals executed
-system.cpu0.kern.callpal::callsys 381 0.20% 99.93% # number of callpals executed
-system.cpu0.kern.callpal::imb 136 0.07% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 186345 # number of callpals executed
+system.cpu0.kern.callpal::wripir 393 0.25% 0.25% # number of callpals executed
+system.cpu0.kern.callpal::wrmces 1 0.00% 0.25% # number of callpals executed
+system.cpu0.kern.callpal::wrfen 1 0.00% 0.25% # number of callpals executed
+system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.25% # number of callpals executed
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+system.cpu0.kern.callpal::wrent 7 0.00% 2.36% # number of callpals executed
+system.cpu0.kern.callpal::swpipl 144424 90.42% 92.78% # number of callpals executed
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+system.cpu0.kern.callpal::wrkgp 1 0.00% 96.79% # number of callpals executed
+system.cpu0.kern.callpal::wrusp 3 0.00% 96.79% # number of callpals executed
+system.cpu0.kern.callpal::rdusp 9 0.01% 96.79% # number of callpals executed
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+system.cpu0.kern.callpal::rti 4592 2.87% 99.67% # number of callpals executed
+system.cpu0.kern.callpal::callsys 391 0.24% 99.91% # number of callpals executed
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+system.cpu0.kern.callpal::total 159723 # number of callpals executed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.hwrei 201175 # number of hwrei instructions executed
-system.cpu0.kern.inst.quiesce 6392 # number of quiesce instructions executed
-system.cpu0.kern.ipl_count::0 72147 40.63% 40.63% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 239 0.13% 40.77% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1932 1.09% 41.86% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 7 0.00% 41.86% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 103229 58.14% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 177554 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 70781 49.24% 49.24% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 239 0.17% 49.41% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1932 1.34% 50.75% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 7 0.00% 50.76% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 70775 49.24% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 143734 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1865669134000 97.77% 97.77% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 102063500 0.01% 97.77% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 400489500 0.02% 97.79% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 4470500 0.00% 97.79% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 42089413000 2.21% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1908265570500 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.981066 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.hwrei 175260 # number of hwrei instructions executed
+system.cpu0.kern.inst.quiesce 6689 # number of quiesce instructions executed
+system.cpu0.kern.ipl_count::0 61186 40.39% 40.39% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21 239 0.16% 40.55% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22 1930 1.27% 41.82% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30 300 0.20% 42.02% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 87830 57.98% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 151485 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 60407 49.12% 49.12% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21 239 0.19% 49.31% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22 1930 1.57% 50.88% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30 300 0.24% 51.13% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 60108 48.87% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total 122984 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1866417310500 97.89% 97.89% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 97564500 0.01% 97.89% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 399841000 0.02% 97.91% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30 136212500 0.01% 97.92% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 39623165500 2.08% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1906674094000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.987268 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.685612 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.mode_good::kernel 1283
-system.cpu0.kern.mode_good::user 1283
+system.cpu0.kern.ipl_used::31 0.684368 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.mode_good::kernel 1353
+system.cpu0.kern.mode_good::user 1354
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch::kernel 7354 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1283 # number of protection mode switches
+system.cpu0.kern.mode_switch::kernel 7157 # number of protection mode switches
+system.cpu0.kern.mode_switch::user 1354 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
-system.cpu0.kern.mode_switch_good::kernel 0.174463 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.189046 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1906087309000 99.89% 99.89% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 2155018500 0.11% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::kernel 1904400738500 99.88% 99.88% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 2273347500 0.12% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3880 # number of times the context was actually changed
-system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed
-system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed
-system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed
-system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed
-system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed
-system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed
-system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed
-system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed
-system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed
-system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed
-system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed
-system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed
-system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed
-system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed
-system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed
-system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed
-system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed
-system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed
-system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed
-system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed
-system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed
-system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed
-system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed
-system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed
-system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed
-system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed
-system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed
-system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed
-system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed
-system.cpu0.kern.syscall::total 222 # number of syscalls executed
-system.cpu0.memDep0.conflictingLoads 2868331 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 2616560 # Number of conflicting stores.
-system.cpu0.memDep0.insertedLoads 10379600 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 6581023 # Number of stores inserted to the mem dependence unit.
-system.cpu0.numCycles 131882753 # number of cpu cycles simulated
-system.cpu0.rename.RENAME:BlockCycles 13878265 # Number of cycles rename is blocking
-system.cpu0.rename.RENAME:CommittedMaps 36623956 # Number of HB maps that are committed
-system.cpu0.rename.RENAME:IQFullEvents 1040563 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.RENAME:IdleCycles 38000902 # Number of cycles rename is idle
-system.cpu0.rename.RENAME:LSQFullEvents 2220107 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RENAME:ROBFullEvents 18213 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.RENAME:RenameLookups 79075810 # Number of register rename lookups that rename has made
-system.cpu0.rename.RENAME:RenamedInsts 65194392 # Number of instructions processed by rename
-system.cpu0.rename.RENAME:RenamedOperands 43691484 # Number of destination operands rename has renamed
-system.cpu0.rename.RENAME:RunCycles 11998481 # Number of cycles rename is running
-system.cpu0.rename.RENAME:SquashCycles 1498947 # Number of cycles rename is squashing
-system.cpu0.rename.RENAME:UnblockCycles 5027996 # Number of cycles rename is unblocking
-system.cpu0.rename.RENAME:UndoneMaps 7067528 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.RENAME:serializeStallCycles 27304879 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RENAME:serializingInsts 1597966 # count of serializing insts renamed
-system.cpu0.rename.RENAME:skidInsts 12274299 # count of insts added to the skid buffer
-system.cpu0.rename.RENAME:tempSerializingInsts 247715 # count of temporary serializing insts renamed
-system.cpu0.timesIdled 1299056 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.kern.swap_context 3320 # number of times the context was actually changed
+system.cpu0.kern.syscall::2 8 3.45% 3.45% # number of syscalls executed
+system.cpu0.kern.syscall::3 20 8.62% 12.07% # number of syscalls executed
+system.cpu0.kern.syscall::4 4 1.72% 13.79% # number of syscalls executed
+system.cpu0.kern.syscall::6 33 14.22% 28.02% # number of syscalls executed
+system.cpu0.kern.syscall::12 1 0.43% 28.45% # number of syscalls executed
+system.cpu0.kern.syscall::17 9 3.88% 32.33% # number of syscalls executed
+system.cpu0.kern.syscall::19 10 4.31% 36.64% # number of syscalls executed
+system.cpu0.kern.syscall::20 6 2.59% 39.22% # number of syscalls executed
+system.cpu0.kern.syscall::23 1 0.43% 39.66% # number of syscalls executed
+system.cpu0.kern.syscall::24 3 1.29% 40.95% # number of syscalls executed
+system.cpu0.kern.syscall::33 7 3.02% 43.97% # number of syscalls executed
+system.cpu0.kern.syscall::41 2 0.86% 44.83% # number of syscalls executed
+system.cpu0.kern.syscall::45 39 16.81% 61.64% # number of syscalls executed
+system.cpu0.kern.syscall::47 3 1.29% 62.93% # number of syscalls executed
+system.cpu0.kern.syscall::48 10 4.31% 67.24% # number of syscalls executed
+system.cpu0.kern.syscall::54 10 4.31% 71.55% # number of syscalls executed
+system.cpu0.kern.syscall::58 1 0.43% 71.98% # number of syscalls executed
+system.cpu0.kern.syscall::59 6 2.59% 74.57% # number of syscalls executed
+system.cpu0.kern.syscall::71 27 11.64% 86.21% # number of syscalls executed
+system.cpu0.kern.syscall::73 3 1.29% 87.50% # number of syscalls executed
+system.cpu0.kern.syscall::74 7 3.02% 90.52% # number of syscalls executed
+system.cpu0.kern.syscall::87 1 0.43% 90.95% # number of syscalls executed
+system.cpu0.kern.syscall::90 3 1.29% 92.24% # number of syscalls executed
+system.cpu0.kern.syscall::92 9 3.88% 96.12% # number of syscalls executed
+system.cpu0.kern.syscall::97 2 0.86% 96.98% # number of syscalls executed
+system.cpu0.kern.syscall::98 2 0.86% 97.84% # number of syscalls executed
+system.cpu0.kern.syscall::132 1 0.43% 98.28% # number of syscalls executed
+system.cpu0.kern.syscall::144 2 0.86% 99.14% # number of syscalls executed
+system.cpu0.kern.syscall::147 2 0.86% 100.00% # number of syscalls executed
+system.cpu0.kern.syscall::total 232 # number of syscalls executed
+system.cpu0.memDep0.conflictingLoads 2539862 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 2208172 # Number of conflicting stores.
+system.cpu0.memDep0.insertedLoads 9510497 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 5918886 # Number of stores inserted to the mem dependence unit.
+system.cpu0.numCycles 120099243 # number of cpu cycles simulated
+system.cpu0.rename.RENAME:BlockCycles 13446049 # Number of cycles rename is blocking
+system.cpu0.rename.RENAME:CommittedMaps 34012953 # Number of HB maps that are committed
+system.cpu0.rename.RENAME:IQFullEvents 1022261 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.RENAME:IdleCycles 33782009 # Number of cycles rename is idle
+system.cpu0.rename.RENAME:LSQFullEvents 1807708 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RENAME:ROBFullEvents 16757 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.RENAME:RenameLookups 73652966 # Number of register rename lookups that rename has made
+system.cpu0.rename.RENAME:RenamedInsts 60220724 # Number of instructions processed by rename
+system.cpu0.rename.RENAME:RenamedOperands 40595001 # Number of destination operands rename has renamed
+system.cpu0.rename.RENAME:RunCycles 11156910 # Number of cycles rename is running
+system.cpu0.rename.RENAME:SquashCycles 1370864 # Number of cycles rename is squashing
+system.cpu0.rename.RENAME:UnblockCycles 4406747 # Number of cycles rename is unblocking
+system.cpu0.rename.RENAME:UndoneMaps 6582046 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.RENAME:serializeStallCycles 22739771 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RENAME:serializingInsts 1403717 # count of serializing insts renamed
+system.cpu0.rename.RENAME:skidInsts 10900390 # count of insts added to the skid buffer
+system.cpu0.rename.RENAME:tempSerializingInsts 213877 # count of temporary serializing insts renamed
+system.cpu0.timesIdled 1182515 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.BTBHits 641418 # Number of BTB hits
-system.cpu1.BPredUnit.BTBLookups 1453120 # Number of BTB lookups
-system.cpu1.BPredUnit.RASInCorrect 4656 # Number of incorrect RAS predictions.
-system.cpu1.BPredUnit.condIncorrect 99987 # Number of conditional branches incorrect
-system.cpu1.BPredUnit.condPredicted 1369738 # Number of conditional branches predicted
-system.cpu1.BPredUnit.lookups 1655319 # Number of BP lookups
-system.cpu1.BPredUnit.usedRAS 114912 # Number of times the RAS was used to get a target.
-system.cpu1.commit.COM:branches 786729 # Number of branches committed
-system.cpu1.commit.COM:bw_lim_events 111651 # number cycles where commit BW limit reached
+system.cpu1.BPredUnit.BTBHits 1168869 # Number of BTB hits
+system.cpu1.BPredUnit.BTBLookups 2724358 # Number of BTB lookups
+system.cpu1.BPredUnit.RASInCorrect 8216 # Number of incorrect RAS predictions.
+system.cpu1.BPredUnit.condIncorrect 170435 # Number of conditional branches incorrect
+system.cpu1.BPredUnit.condPredicted 2536443 # Number of conditional branches predicted
+system.cpu1.BPredUnit.lookups 3058879 # Number of BP lookups
+system.cpu1.BPredUnit.usedRAS 214059 # Number of times the RAS was used to get a target.
+system.cpu1.commit.COM:branches 1536055 # Number of branches committed
+system.cpu1.commit.COM:bw_lim_events 205800 # number cycles where commit BW limit reached
system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.commit.COM:committed_per_cycle::samples 9662936 # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::mean 0.576830 # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::stdev 1.391062 # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::samples 19921603 # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::mean 0.539460 # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::stdev 1.350836 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::0 7270313 75.24% 75.24% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::1 1222307 12.65% 87.89% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::2 443469 4.59% 92.48% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::3 257393 2.66% 95.14% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::4 152904 1.58% 96.72% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::5 87632 0.91% 97.63% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::6 71404 0.74% 98.37% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::7 45863 0.47% 98.84% # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::8 111651 1.16% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::0 15476427 77.69% 77.69% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::1 2094576 10.51% 88.20% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::2 801789 4.02% 92.23% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::3 588293 2.95% 95.18% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::4 417407 2.10% 97.27% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::5 144338 0.72% 98.00% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::6 104661 0.53% 98.52% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::7 88312 0.44% 98.97% # Number of insts commited each cycle
+system.cpu1.commit.COM:committed_per_cycle::8 205800 1.03% 100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.COM:committed_per_cycle::total 9662936 # Number of insts commited each cycle
-system.cpu1.commit.COM:count 5573873 # Number of instructions committed
-system.cpu1.commit.COM:loads 1110708 # Number of loads committed
-system.cpu1.commit.COM:membars 18999 # Number of memory barriers committed
-system.cpu1.commit.COM:refs 1809440 # Number of memory references committed
+system.cpu1.commit.COM:committed_per_cycle::total 19921603 # Number of insts commited each cycle
+system.cpu1.commit.COM:count 10746901 # Number of instructions committed
+system.cpu1.commit.COM:loads 2021572 # Number of loads committed
+system.cpu1.commit.COM:membars 56653 # Number of memory barriers committed
+system.cpu1.commit.COM:refs 3430255 # Number of memory references committed
system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.branchMispredicts 95993 # The number of times a branch was mispredicted
-system.cpu1.commit.commitCommittedInsts 5573873 # The number of committed instructions
-system.cpu1.commit.commitNonSpecStalls 71139 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.commitSquashedInsts 1244666 # The number of squashed insts skipped by commit
-system.cpu1.committedInsts 5361238 # Number of Instructions Simulated
-system.cpu1.committedInsts_total 5361238 # Number of Instructions Simulated
-system.cpu1.cpi 2.006382 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 2.006382 # CPI: Total CPI of All Threads
-system.cpu1.dcache.LoadLockedReq_accesses::0 15265 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 15265 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 14429.127726 # average LoadLockedReq miss latency
+system.cpu1.commit.branchMispredicts 163240 # The number of times a branch was mispredicted
+system.cpu1.commit.commitCommittedInsts 10746901 # The number of committed instructions
+system.cpu1.commit.commitNonSpecStalls 172585 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.commitSquashedInsts 1766208 # The number of squashed insts skipped by commit
+system.cpu1.committedInsts 10192138 # Number of Instructions Simulated
+system.cpu1.committedInsts_total 10192138 # Number of Instructions Simulated
+system.cpu1.cpi 2.158157 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 2.158157 # CPI: Total CPI of All Threads
+system.cpu1.dcache.LoadLockedReq_accesses::0 48648 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 48648 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 10962.569444 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10666.666667 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_hits::0 13981 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 13981 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_miss_latency 18527000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.084114 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_misses::0 1284 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 1284 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_mshr_hits 240 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 11136000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.068392 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7807.164404 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_hits::0 41448 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 41448 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_miss_latency 78930500 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.148002 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_misses::0 7200 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 7200 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_mshr_hits 570 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 51761500 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.136285 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_misses 1044 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.ReadReq_accesses::0 1203979 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 1203979 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency::0 18427.853599 # average ReadReq miss latency
+system.cpu1.dcache.LoadLockedReq_mshr_misses 6630 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.ReadReq_accesses::0 2081061 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 2081061 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_avg_miss_latency::0 16526.110109 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13573.416201 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11960.136769 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_hits::0 1110045 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 1110045 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_latency 1731002000 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_rate::0 0.078020 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses::0 93934 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 93934 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_mshr_hits 53146 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_miss_latency 553632500 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.033878 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_hits::0 1891958 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 1891958 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_latency 3125137000 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_rate::0 0.090869 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses::0 189103 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 189103 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_mshr_hits 93175 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_miss_latency 1147312000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.046096 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_misses 40788 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 15686000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.StoreCondReq_accesses::0 14051 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 14051 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 45874.534161 # average StoreCondReq miss latency
+system.cpu1.dcache.ReadReq_mshr_misses 95928 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 16183000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.StoreCondReq_accesses::0 45890 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 45890 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 35468.138068 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 42893.537697 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_hits::0 11636 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 11636 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_miss_latency 110787000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_rate::0 0.171874 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_misses::0 2415 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 2415 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency 103545000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.171803 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 32471.951759 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_hits::0 36851 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 36851 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_miss_latency 320596500 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_rate::0 0.196971 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_misses::0 9039 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 9039 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency 293481500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.196949 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_misses 2414 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.WriteReq_accesses::0 679686 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 679686 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency::0 48846.469056 # average WriteReq miss latency
+system.cpu1.dcache.StoreCondReq_mshr_misses 9038 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.WriteReq_accesses::0 1356401 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 1356401 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_avg_miss_latency::0 48468.442060 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 52388.154254 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 50000.550136 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_hits::0 517989 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 517989 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_latency 7898327507 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_rate::0 0.237900 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses::0 161697 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 161697 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_mshr_hits 135111 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_miss_latency 1392791469 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.039115 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_hits::0 1038709 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 1038709 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_latency 15398036295 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_rate::0 0.234217 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses::0 317692 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 317692 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_mshr_hits 255162 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_miss_latency 3126534400 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.046100 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_misses 26586 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 309596000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12811.786863 # average number of cycles each access was blocked
+system.cpu1.dcache.WriteReq_mshr_misses 62530 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 383884000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11747.407108 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs 28.408620 # Average number of references to valid blocks.
-system.cpu1.dcache.blocked::no_mshrs 11875 # number of cycles access was blocked
+system.cpu1.dcache.avg_refs 23.303685 # Average number of references to valid blocks.
+system.cpu1.dcache.blocked::no_mshrs 12380 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_mshrs 152139969 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_mshrs 145432900 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.demand_accesses::0 1883665 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::0 3437462 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 1883665 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency::0 37668.864523 # average overall miss latency
+system.cpu1.dcache.demand_accesses::total 3437462 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency::0 36549.637023 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 28889.838350 # average overall mshr miss latency
-system.cpu1.dcache.demand_hits::0 1628034 # number of demand (read+write) hits
+system.cpu1.dcache.demand_avg_mshr_miss_latency 26971.477616 # average overall mshr miss latency
+system.cpu1.dcache.demand_hits::0 2930667 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 1628034 # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency 9629329507 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate::0 0.135709 # miss rate for demand accesses
+system.cpu1.dcache.demand_hits::total 2930667 # number of demand (read+write) hits
+system.cpu1.dcache.demand_miss_latency 18523173295 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_rate::0 0.147433 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu1.dcache.demand_misses::0 255631 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::0 506795 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 255631 # number of demand (read+write) misses
-system.cpu1.dcache.demand_mshr_hits 188257 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency 1946423969 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate::0 0.035768 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_misses::total 506795 # number of demand (read+write) misses
+system.cpu1.dcache.demand_mshr_hits 348337 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_miss_latency 4273846400 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_rate::0 0.046097 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses 67374 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses 158458 # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0 0.773778 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_blocks::0 396.174503 # Average occupied blocks per context
-system.cpu1.dcache.overall_accesses::0 1883665 # number of overall (read+write) accesses
+system.cpu1.dcache.occ_%::0 0.929332 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_blocks::0 475.817757 # Average occupied blocks per context
+system.cpu1.dcache.overall_accesses::0 3437462 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 1883665 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency::0 37668.864523 # average overall miss latency
+system.cpu1.dcache.overall_accesses::total 3437462 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_avg_miss_latency::0 36549.637023 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 28889.838350 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 26971.477616 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits::0 1628034 # number of overall hits
+system.cpu1.dcache.overall_hits::0 2930667 # number of overall hits
system.cpu1.dcache.overall_hits::1 0 # number of overall hits
-system.cpu1.dcache.overall_hits::total 1628034 # number of overall hits
-system.cpu1.dcache.overall_miss_latency 9629329507 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate::0 0.135709 # miss rate for overall accesses
+system.cpu1.dcache.overall_hits::total 2930667 # number of overall hits
+system.cpu1.dcache.overall_miss_latency 18523173295 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_rate::0 0.147433 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.dcache.overall_misses::0 255631 # number of overall misses
+system.cpu1.dcache.overall_misses::0 506795 # number of overall misses
system.cpu1.dcache.overall_misses::1 0 # number of overall misses
-system.cpu1.dcache.overall_misses::total 255631 # number of overall misses
-system.cpu1.dcache.overall_mshr_hits 188257 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency 1946423969 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate::0 0.035768 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_misses::total 506795 # number of overall misses
+system.cpu1.dcache.overall_mshr_hits 348337 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_miss_latency 4273846400 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_rate::0 0.046097 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_misses 67374 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_latency 325282000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_misses 158458 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_latency 400067000 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.replacements 58281 # number of replacements
-system.cpu1.dcache.sampled_refs 58793 # Sample count of references to valid blocks.
+system.cpu1.dcache.replacements 131481 # number of replacements
+system.cpu1.dcache.sampled_refs 131801 # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse 396.174503 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 1670228 # Total number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 1884260206000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks 26579 # number of writebacks
-system.cpu1.decode.DECODE:BlockedCycles 4231249 # Number of cycles decode is blocked
-system.cpu1.decode.DECODE:BranchMispred 4060 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DECODE:BranchResolved 70345 # Number of times decode resolved a branch
-system.cpu1.decode.DECODE:DecodedInsts 7846841 # Number of instructions handled by decode
-system.cpu1.decode.DECODE:IdleCycles 3945555 # Number of cycles decode is idle
-system.cpu1.decode.DECODE:RunCycles 1457789 # Number of cycles decode is running
-system.cpu1.decode.DECODE:SquashCycles 213951 # Number of cycles decode is squashing
-system.cpu1.decode.DECODE:SquashedInsts 12437 # Number of squashed instructions handled by decode
-system.cpu1.decode.DECODE:UnblockCycles 28342 # Number of cycles decode is unblocking
-system.cpu1.dtb.data_accesses 436826 # DTB accesses
-system.cpu1.dtb.data_acv 92 # DTB access violations
-system.cpu1.dtb.data_hits 2033744 # DTB hits
-system.cpu1.dtb.data_misses 11106 # DTB misses
+system.cpu1.dcache.tagsinuse 475.817757 # Cycle average of tags in use
+system.cpu1.dcache.total_refs 3071449 # Total number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle 1882597271000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.writebacks 66520 # number of writebacks
+system.cpu1.decode.DECODE:BlockedCycles 8690485 # Number of cycles decode is blocked
+system.cpu1.decode.DECODE:BranchMispred 7262 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DECODE:BranchResolved 129460 # Number of times decode resolved a branch
+system.cpu1.decode.DECODE:DecodedInsts 14175016 # Number of instructions handled by decode
+system.cpu1.decode.DECODE:IdleCycles 8601755 # Number of cycles decode is idle
+system.cpu1.decode.DECODE:RunCycles 2517670 # Number of cycles decode is running
+system.cpu1.decode.DECODE:SquashCycles 311026 # Number of cycles decode is squashing
+system.cpu1.decode.DECODE:SquashedInsts 21330 # Number of squashed instructions handled by decode
+system.cpu1.decode.DECODE:UnblockCycles 111692 # Number of cycles decode is unblocking
+system.cpu1.dtb.data_accesses 379731 # DTB accesses
+system.cpu1.dtb.data_acv 79 # DTB access violations
+system.cpu1.dtb.data_hits 3682802 # DTB hits
+system.cpu1.dtb.data_misses 10764 # DTB misses
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
-system.cpu1.dtb.read_accesses 315884 # DTB read accesses
-system.cpu1.dtb.read_acv 16 # DTB read access violations
-system.cpu1.dtb.read_hits 1299460 # DTB read hits
-system.cpu1.dtb.read_misses 8720 # DTB read misses
-system.cpu1.dtb.write_accesses 120942 # DTB write accesses
-system.cpu1.dtb.write_acv 76 # DTB write access violations
-system.cpu1.dtb.write_hits 734284 # DTB write hits
-system.cpu1.dtb.write_misses 2386 # DTB write misses
-system.cpu1.fetch.Branches 1655319 # Number of branches that fetch encountered
-system.cpu1.fetch.CacheLines 983571 # Number of cache lines fetched
-system.cpu1.fetch.Cycles 2495244 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.IcacheSquashes 54744 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.Insts 8005120 # Number of instructions fetch has processed
-system.cpu1.fetch.MiscStallCycles 124 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.SquashCycles 119648 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.branchRate 0.153887 # Number of branch fetches per cycle
-system.cpu1.fetch.icacheStallCycles 983571 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.predictedBranches 756330 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.rate 0.744199 # Number of inst fetches per cycle
-system.cpu1.fetch.rateDist::samples 9876887 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.810490 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.152603 # Number of instructions fetched each cycle (Total)
+system.cpu1.dtb.read_accesses 273464 # DTB read accesses
+system.cpu1.dtb.read_acv 11 # DTB read access violations
+system.cpu1.dtb.read_hits 2232523 # DTB read hits
+system.cpu1.dtb.read_misses 8601 # DTB read misses
+system.cpu1.dtb.write_accesses 106267 # DTB write accesses
+system.cpu1.dtb.write_acv 68 # DTB write access violations
+system.cpu1.dtb.write_hits 1450279 # DTB write hits
+system.cpu1.dtb.write_misses 2163 # DTB write misses
+system.cpu1.fetch.Branches 3058879 # Number of branches that fetch encountered
+system.cpu1.fetch.CacheLines 1688815 # Number of cache lines fetched
+system.cpu1.fetch.Cycles 4357354 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.IcacheSquashes 105751 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.Insts 14416907 # Number of instructions fetch has processed
+system.cpu1.fetch.MiscStallCycles 179 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.SquashCycles 193553 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.branchRate 0.139064 # Number of branch fetches per cycle
+system.cpu1.fetch.icacheStallCycles 1688815 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.predictedBranches 1382928 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.rate 0.655426 # Number of inst fetches per cycle
+system.cpu1.fetch.rateDist::samples 20232629 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.712557 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.050166 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 8372049 84.76% 84.76% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 99748 1.01% 85.77% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 205638 2.08% 87.86% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 130058 1.32% 89.17% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 234183 2.37% 91.54% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 78658 0.80% 92.34% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 103423 1.05% 93.39% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 71678 0.73% 94.11% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 581452 5.89% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 17569535 86.84% 86.84% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 215879 1.07% 87.90% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 322874 1.60% 89.50% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 192834 0.95% 90.45% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 374265 1.85% 92.30% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 129017 0.64% 92.94% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 159403 0.79% 93.73% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 272361 1.35% 95.07% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 996461 4.93% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 9876887 # Number of instructions fetched each cycle (Total)
-system.cpu1.icache.ReadReq_accesses::0 983571 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 983571 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_avg_miss_latency::0 14895.250407 # average ReadReq miss latency
+system.cpu1.fetch.rateDist::total 20232629 # Number of instructions fetched each cycle (Total)
+system.cpu1.icache.ReadReq_accesses::0 1688815 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 1688815 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_avg_miss_latency::0 14598.075134 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11864.081295 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_hits::0 879141 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 879141 # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_latency 1555511000 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_rate::0 0.106174 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses::0 104430 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 104430 # number of ReadReq misses
-system.cpu1.icache.ReadReq_mshr_hits 4006 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_miss_latency 1191438500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.102101 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11541.965319 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_hits::0 1410406 # number of ReadReq hits
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system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_misses 100424 # number of ReadReq MSHR misses
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system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs 8.759351 # Average number of references to valid blocks.
-system.cpu1.icache.blocked::no_mshrs 11 # number of cycles access was blocked
+system.cpu1.icache.avg_refs 5.214764 # Average number of references to valid blocks.
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system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_mshrs 73000 # number of cycles access was blocked
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system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.demand_accesses::0 983571 # number of demand (read+write) accesses
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system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses
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system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11864.081295 # average overall mshr miss latency
-system.cpu1.icache.demand_hits::0 879141 # number of demand (read+write) hits
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system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 879141 # number of demand (read+write) hits
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system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu1.icache.demand_misses::0 104430 # number of demand (read+write) misses
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system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 104430 # number of demand (read+write) misses
-system.cpu1.icache.demand_mshr_hits 4006 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_miss_latency 1191438500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate::0 0.102101 # mshr miss rate for demand accesses
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system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_misses 100424 # number of demand (read+write) MSHR misses
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system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.occ_%::0 0.866895 # Average percentage of cache occupancy
-system.cpu1.icache.occ_blocks::0 443.850090 # Average occupied blocks per context
-system.cpu1.icache.overall_accesses::0 983571 # number of overall (read+write) accesses
+system.cpu1.icache.occ_%::0 0.900098 # Average percentage of cache occupancy
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system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 983571 # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency::0 14895.250407 # average overall miss latency
+system.cpu1.icache.overall_accesses::total 1688815 # number of overall (read+write) accesses
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system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11864.081295 # average overall mshr miss latency
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system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits::0 879141 # number of overall hits
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system.cpu1.icache.overall_hits::1 0 # number of overall hits
-system.cpu1.icache.overall_hits::total 879141 # number of overall hits
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system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.icache.overall_misses::0 104430 # number of overall misses
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system.cpu1.icache.overall_misses::1 0 # number of overall misses
-system.cpu1.icache.overall_misses::total 104430 # number of overall misses
-system.cpu1.icache.overall_mshr_hits 4006 # number of overall MSHR hits
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+system.cpu1.icache.overall_misses::total 278409 # number of overall misses
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+system.cpu1.icache.overall_mshr_miss_latency 3122344000 # number of overall MSHR miss cycles
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system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_misses 100424 # number of overall MSHR misses
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system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.icache.replacements 99855 # number of replacements
-system.cpu1.icache.sampled_refs 100366 # Sample count of references to valid blocks.
+system.cpu1.icache.replacements 269955 # number of replacements
+system.cpu1.icache.sampled_refs 270464 # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse 443.850090 # Cycle average of tags in use
-system.cpu1.icache.total_refs 879141 # Total number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 1897353320500 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tagsinuse 460.849961 # Cycle average of tags in use
+system.cpu1.icache.total_refs 1410406 # Total number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 1902950008000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks 0 # number of writebacks
-system.cpu1.idleCycles 879803 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.iew.EXEC:branches 868251 # Number of branches executed
-system.cpu1.iew.EXEC:nop 253715 # number of nop insts executed
-system.cpu1.iew.EXEC:rate 0.554813 # Inst execution rate
-system.cpu1.iew.EXEC:refs 2051713 # number of memory reference insts executed
-system.cpu1.iew.EXEC:stores 739910 # Number of stores executed
+system.cpu1.idleCycles 1763601 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.iew.EXEC:branches 1647161 # Number of branches executed
+system.cpu1.iew.EXEC:nop 633873 # number of nop insts executed
+system.cpu1.iew.EXEC:rate 0.498846 # Inst execution rate
+system.cpu1.iew.EXEC:refs 3712298 # number of memory reference insts executed
+system.cpu1.iew.EXEC:stores 1459673 # Number of stores executed
system.cpu1.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu1.iew.WB:consumers 3750224 # num instructions consuming a value
-system.cpu1.iew.WB:count 5855863 # cumulative count of insts written-back
-system.cpu1.iew.WB:fanout 0.732329 # average fanout of values written-back
+system.cpu1.iew.WB:consumers 6255206 # num instructions consuming a value
+system.cpu1.iew.WB:count 10847139 # cumulative count of insts written-back
+system.cpu1.iew.WB:fanout 0.739229 # average fanout of values written-back
system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.iew.WB:producers 2746396 # num instructions producing a value
-system.cpu1.iew.WB:rate 0.544393 # insts written-back per cycle
-system.cpu1.iew.WB:sent 5874071 # cumulative count of insts sent to commit
-system.cpu1.iew.branchMispredicts 104878 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewBlockCycles 312048 # Number of cycles IEW is blocking
-system.cpu1.iew.iewDispLoadInsts 1391930 # Number of dispatched load instructions
-system.cpu1.iew.iewDispNonSpecInsts 267781 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewDispSquashedInsts 126811 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispStoreInsts 802099 # Number of dispatched store instructions
-system.cpu1.iew.iewDispatchedInsts 6897856 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewExecLoadInsts 1311803 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 68901 # Number of squashed instructions skipped in execute
-system.cpu1.iew.iewExecutedInsts 5967953 # Number of executed instructions
-system.cpu1.iew.iewIQFullEvents 3132 # Number of times the IQ has become full, causing a stall
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+system.cpu1.iew.WB:sent 10867556 # cumulative count of insts sent to commit
+system.cpu1.iew.branchMispredicts 177268 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewBlockCycles 332920 # Number of cycles IEW is blocking
+system.cpu1.iew.iewDispLoadInsts 2358529 # Number of dispatched load instructions
+system.cpu1.iew.iewDispNonSpecInsts 525453 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewDispSquashedInsts 201798 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispStoreInsts 1538474 # Number of dispatched store instructions
+system.cpu1.iew.iewDispatchedInsts 12592629 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewExecLoadInsts 2252625 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 104488 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewExecutedInsts 10972727 # Number of executed instructions
+system.cpu1.iew.iewIQFullEvents 3148 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewLSQFullEvents 1266 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.iewSquashCycles 213951 # Number of cycles IEW is squashing
-system.cpu1.iew.iewUnblockCycles 8244 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewLSQFullEvents 1572 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles 311026 # Number of cycles IEW is squashing
+system.cpu1.iew.iewUnblockCycles 9766 # Number of cycles IEW is unblocking
system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread.0.cacheBlocked 56759 # Number of times an access to memory failed due to the cache being blocked
-system.cpu1.iew.lsq.thread.0.forwLoads 34660 # Number of loads that had data forwarded from stores
-system.cpu1.iew.lsq.thread.0.ignoredResponses 1926 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread.0.cacheBlocked 50281 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread.0.forwLoads 68629 # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread.0.ignoredResponses 4124 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu1.iew.lsq.thread.0.memOrderViolation 7014 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread.0.rescheduledLoads 360 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread.0.squashedLoads 281222 # Number of loads squashed
-system.cpu1.iew.lsq.thread.0.squashedStores 103367 # Number of stores squashed
-system.cpu1.iew.memOrderViolationEvents 7014 # Number of memory order violations
-system.cpu1.iew.predictedNotTakenIncorrect 58993 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.predictedTakenIncorrect 45885 # Number of branches that were predicted taken incorrectly
-system.cpu1.ipc 0.498410 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.498410 # IPC: Total IPC of All Threads
-system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3973 0.07% 0.07% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntAlu 3726705 61.73% 61.80% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntMult 10086 0.17% 61.97% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 61.97% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 10031 0.17% 62.13% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.13% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.13% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.13% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1986 0.03% 62.16% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.16% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::MemRead 1347365 22.32% 84.48% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::MemWrite 752050 12.46% 96.94% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::IprAccess 184660 3.06% 100.00% # Type of FU issued
+system.cpu1.iew.lsq.thread.0.memOrderViolation 9401 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread.0.rescheduledLoads 371 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread.0.squashedLoads 336957 # Number of loads squashed
+system.cpu1.iew.lsq.thread.0.squashedStores 129791 # Number of stores squashed
+system.cpu1.iew.memOrderViolationEvents 9401 # Number of memory order violations
+system.cpu1.iew.predictedNotTakenIncorrect 104860 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.predictedTakenIncorrect 72408 # Number of branches that were predicted taken incorrectly
+system.cpu1.ipc 0.463358 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.463358 # IPC: Total IPC of All Threads
+system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3519 0.03% 0.03% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IntAlu 6926354 62.53% 62.56% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IntMult 18692 0.17% 62.73% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.73% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 11838 0.11% 62.84% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.84% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.84% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.84% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1759 0.02% 62.85% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::MemRead 2331483 21.05% 83.90% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1476157 13.33% 97.22% # Type of FU issued
+system.cpu1.iq.ISSUE:FU_type_0::IprAccess 307413 2.78% 100.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.ISSUE:FU_type_0::total 6036856 # Type of FU issued
-system.cpu1.iq.ISSUE:fu_busy_cnt 101607 # FU busy when requested
-system.cpu1.iq.ISSUE:fu_busy_rate 0.016831 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.ISSUE:FU_type_0::total 11077215 # Type of FU issued
+system.cpu1.iq.ISSUE:fu_busy_cnt 158215 # FU busy when requested
+system.cpu1.iq.ISSUE:fu_busy_rate 0.014283 # FU busy rate (busy events/executed inst)
system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntAlu 3728 3.67% 3.67% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 3.67% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::MemRead 63305 62.30% 65.97% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:fu_full::MemWrite 34574 34.03% 100.00% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::IntAlu 4066 2.57% 2.57% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 2.57% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.57% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.57% # attempts to use FU when none available
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+system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.57% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.57% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.57% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.57% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::MemRead 92866 58.70% 61.27% # attempts to use FU when none available
+system.cpu1.iq.ISSUE:fu_full::MemWrite 61283 38.73% 100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:issued_per_cycle::samples 9876887 # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.611210 # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.231461 # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::samples 20232629 # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.547493 # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.152304 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::0 7028128 71.16% 71.16% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::1 1406586 14.24% 85.40% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::2 558070 5.65% 91.05% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::3 375734 3.80% 94.85% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::4 282352 2.86% 97.71% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::5 133259 1.35% 99.06% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::6 62266 0.63% 99.69% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::7 26307 0.27% 99.96% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::8 4185 0.04% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::0 14868449 73.49% 73.49% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::1 2672522 13.21% 86.70% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::2 1102181 5.45% 92.14% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::3 699877 3.46% 95.60% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::4 518299 2.56% 98.16% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::5 241576 1.19% 99.36% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::6 93786 0.46% 99.82% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::7 30604 0.15% 99.97% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::8 5335 0.03% 100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::total 9876887 # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:rate 0.561219 # Inst issue rate
-system.cpu1.iq.iqInstsAdded 6356285 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqInstsIssued 6036856 # Number of instructions issued
-system.cpu1.iq.iqNonSpecInstsAdded 287856 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqSquashedInstsExamined 1234181 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedInstsIssued 8959 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedNonSpecRemoved 216717 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.iqSquashedOperandsExamined 734853 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.ISSUE:issued_per_cycle::total 20232629 # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:rate 0.503596 # Inst issue rate
+system.cpu1.iq.iqInstsAdded 11373839 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqInstsIssued 11077215 # Number of instructions issued
+system.cpu1.iq.iqNonSpecInstsAdded 584917 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqSquashedInstsExamined 1698901 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedInstsIssued 10384 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedNonSpecRemoved 412332 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.iqSquashedOperandsExamined 877867 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_hits 0 # DTB hits
system.cpu1.itb.data_misses 0 # DTB misses
-system.cpu1.itb.fetch_accesses 347409 # ITB accesses
-system.cpu1.itb.fetch_acv 92 # ITB acv
-system.cpu1.itb.fetch_hits 340665 # ITB hits
-system.cpu1.itb.fetch_misses 6744 # ITB misses
+system.cpu1.itb.fetch_accesses 413824 # ITB accesses
+system.cpu1.itb.fetch_acv 100 # ITB acv
+system.cpu1.itb.fetch_hits 408478 # ITB hits
+system.cpu1.itb.fetch_misses 5346 # ITB misses
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
-system.cpu1.kern.callpal::wripir 7 0.02% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed
-system.cpu1.kern.callpal::swpctx 357 1.17% 1.20% # number of callpals executed
-system.cpu1.kern.callpal::tbi 3 0.01% 1.21% # number of callpals executed
-system.cpu1.kern.callpal::wrent 7 0.02% 1.23% # number of callpals executed
-system.cpu1.kern.callpal::swpipl 25115 82.21% 83.44% # number of callpals executed
-system.cpu1.kern.callpal::rdps 2369 7.75% 91.20% # number of callpals executed
-system.cpu1.kern.callpal::wrkgp 1 0.00% 91.20% # number of callpals executed
-system.cpu1.kern.callpal::wrusp 4 0.01% 91.21% # number of callpals executed
-system.cpu1.kern.callpal::whami 3 0.01% 91.22% # number of callpals executed
-system.cpu1.kern.callpal::rti 2501 8.19% 99.41% # number of callpals executed
-system.cpu1.kern.callpal::callsys 136 0.45% 99.85% # number of callpals executed
-system.cpu1.kern.callpal::imb 44 0.14% 100.00% # number of callpals executed
+system.cpu1.kern.callpal::wripir 300 0.50% 0.50% # number of callpals executed
+system.cpu1.kern.callpal::wrmces 1 0.00% 0.50% # number of callpals executed
+system.cpu1.kern.callpal::wrfen 1 0.00% 0.50% # number of callpals executed
+system.cpu1.kern.callpal::swpctx 1497 2.49% 3.00% # number of callpals executed
+system.cpu1.kern.callpal::tbi 3 0.00% 3.00% # number of callpals executed
+system.cpu1.kern.callpal::wrent 7 0.01% 3.02% # number of callpals executed
+system.cpu1.kern.callpal::swpipl 52375 87.24% 90.26% # number of callpals executed
+system.cpu1.kern.callpal::rdps 2373 3.95% 94.21% # number of callpals executed
+system.cpu1.kern.callpal::wrkgp 1 0.00% 94.21% # number of callpals executed
+system.cpu1.kern.callpal::wrusp 4 0.01% 94.22% # number of callpals executed
+system.cpu1.kern.callpal::whami 3 0.00% 94.22% # number of callpals executed
+system.cpu1.kern.callpal::rti 3300 5.50% 99.72% # number of callpals executed
+system.cpu1.kern.callpal::callsys 124 0.21% 99.93% # number of callpals executed
+system.cpu1.kern.callpal::imb 42 0.07% 100.00% # number of callpals executed
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
-system.cpu1.kern.callpal::total 30551 # number of callpals executed
+system.cpu1.kern.callpal::total 60033 # number of callpals executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.hwrei 37164 # number of hwrei instructions executed
-system.cpu1.kern.inst.quiesce 2263 # number of quiesce instructions executed
-system.cpu1.kern.ipl_count::0 9735 32.84% 32.84% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1929 6.51% 39.35% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 98 0.33% 39.68% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 17882 60.32% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 29644 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 9724 45.49% 45.49% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1929 9.02% 54.51% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 98 0.46% 54.97% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 9626 45.03% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 21377 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1880211308500 98.51% 98.51% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 349210000 0.02% 98.53% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 40269500 0.00% 98.53% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 28079728000 1.47% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1908680516000 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.998870 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.hwrei 66427 # number of hwrei instructions executed
+system.cpu1.kern.inst.quiesce 2553 # number of quiesce instructions executed
+system.cpu1.kern.ipl_count::0 21855 37.68% 37.68% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22 1927 3.32% 41.01% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30 393 0.68% 41.68% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31 33821 58.32% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total 57996 # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0 21257 47.83% 47.83% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22 1927 4.34% 52.17% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30 393 0.88% 53.05% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 20864 46.95% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total 44441 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0 1874788065000 98.35% 98.35% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 349524500 0.02% 98.37% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 166729500 0.01% 98.38% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 30954744500 1.62% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1906259063500 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.972638 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.538307 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.mode_good::kernel 485
-system.cpu1.kern.mode_good::user 463
-system.cpu1.kern.mode_good::idle 22
-system.cpu1.kern.mode_switch::kernel 814 # number of protection mode switches
-system.cpu1.kern.mode_switch::user 463 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2046 # number of protection mode switches
-system.cpu1.kern.mode_switch_good::kernel 0.595823 # fraction of useful protection mode switches
+system.cpu1.kern.ipl_used::31 0.616895 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.mode_good::kernel 700
+system.cpu1.kern.mode_good::user 383
+system.cpu1.kern.mode_good::idle 317
+system.cpu1.kern.mode_switch::kernel 1588 # number of protection mode switches
+system.cpu1.kern.mode_switch::user 383 # number of protection mode switches
+system.cpu1.kern.mode_switch::idle 2627 # number of protection mode switches
+system.cpu1.kern.mode_switch_good::kernel 0.440806 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle 0.010753 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total 1.606576 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 2177635500 0.11% 0.11% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 994853500 0.05% 0.17% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1905508019000 99.83% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 358 # number of times the context was actually changed
-system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed
-system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed
-system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed
-system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed
-system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed
-system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed
-system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed
-system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed
-system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed
-system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed
-system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed
-system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed
-system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed
-system.cpu1.kern.syscall::total 104 # number of syscalls executed
-system.cpu1.memDep0.conflictingLoads 249198 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 232138 # Number of conflicting stores.
-system.cpu1.memDep0.insertedLoads 1391930 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 802099 # Number of stores inserted to the mem dependence unit.
-system.cpu1.numCycles 10756690 # number of cpu cycles simulated
-system.cpu1.rename.RENAME:BlockCycles 465609 # Number of cycles rename is blocking
-system.cpu1.rename.RENAME:CommittedMaps 3852724 # Number of HB maps that are committed
-system.cpu1.rename.RENAME:IQFullEvents 44260 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.RENAME:IdleCycles 4077020 # Number of cycles rename is idle
-system.cpu1.rename.RENAME:LSQFullEvents 64277 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RENAME:ROBFullEvents 71 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.RENAME:RenameLookups 8954426 # Number of register rename lookups that rename has made
-system.cpu1.rename.RENAME:RenamedInsts 7268297 # Number of instructions processed by rename
-system.cpu1.rename.RENAME:RenamedOperands 4874919 # Number of destination operands rename has renamed
-system.cpu1.rename.RENAME:RunCycles 1341579 # Number of cycles rename is running
-system.cpu1.rename.RENAME:SquashCycles 213951 # Number of cycles rename is squashing
-system.cpu1.rename.RENAME:UnblockCycles 396189 # Number of cycles rename is unblocking
-system.cpu1.rename.RENAME:UndoneMaps 1022193 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.RENAME:serializeStallCycles 3382537 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RENAME:serializingInsts 292831 # count of serializing insts renamed
-system.cpu1.rename.RENAME:skidInsts 1228786 # count of insts added to the skid buffer
-system.cpu1.rename.RENAME:tempSerializingInsts 20447 # count of temporary serializing insts renamed
-system.cpu1.timesIdled 85032 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.kern.mode_switch_good::idle 0.120670 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total 1.561476 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel 7544739000 0.40% 0.40% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user 853569500 0.04% 0.44% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle 1897425262500 99.56% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 1498 # number of times the context was actually changed
+system.cpu1.kern.syscall::3 10 10.64% 10.64% # number of syscalls executed
+system.cpu1.kern.syscall::6 9 9.57% 20.21% # number of syscalls executed
+system.cpu1.kern.syscall::15 1 1.06% 21.28% # number of syscalls executed
+system.cpu1.kern.syscall::17 6 6.38% 27.66% # number of syscalls executed
+system.cpu1.kern.syscall::23 3 3.19% 30.85% # number of syscalls executed
+system.cpu1.kern.syscall::24 3 3.19% 34.04% # number of syscalls executed
+system.cpu1.kern.syscall::33 4 4.26% 38.30% # number of syscalls executed
+system.cpu1.kern.syscall::45 15 15.96% 54.26% # number of syscalls executed
+system.cpu1.kern.syscall::47 3 3.19% 57.45% # number of syscalls executed
+system.cpu1.kern.syscall::59 1 1.06% 58.51% # number of syscalls executed
+system.cpu1.kern.syscall::71 27 28.72% 87.23% # number of syscalls executed
+system.cpu1.kern.syscall::74 9 9.57% 96.81% # number of syscalls executed
+system.cpu1.kern.syscall::132 3 3.19% 100.00% # number of syscalls executed
+system.cpu1.kern.syscall::total 94 # number of syscalls executed
+system.cpu1.memDep0.conflictingLoads 510972 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 447437 # Number of conflicting stores.
+system.cpu1.memDep0.insertedLoads 2358529 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 1538474 # Number of stores inserted to the mem dependence unit.
+system.cpu1.numCycles 21996230 # number of cpu cycles simulated
+system.cpu1.rename.RENAME:BlockCycles 659886 # Number of cycles rename is blocking
+system.cpu1.rename.RENAME:CommittedMaps 7238905 # Number of HB maps that are committed
+system.cpu1.rename.RENAME:IQFullEvents 29431 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.RENAME:IdleCycles 8848928 # Number of cycles rename is idle
+system.cpu1.rename.RENAME:LSQFullEvents 376341 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RENAME:ROBFullEvents 2702 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.RENAME:RenameLookups 15628999 # Number of register rename lookups that rename has made
+system.cpu1.rename.RENAME:RenamedInsts 13115251 # Number of instructions processed by rename
+system.cpu1.rename.RENAME:RenamedOperands 8582665 # Number of destination operands rename has renamed
+system.cpu1.rename.RENAME:RunCycles 2365502 # Number of cycles rename is running
+system.cpu1.rename.RENAME:SquashCycles 311026 # Number of cycles rename is squashing
+system.cpu1.rename.RENAME:UnblockCycles 913464 # Number of cycles rename is unblocking
+system.cpu1.rename.RENAME:UndoneMaps 1343760 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.RENAME:serializeStallCycles 7133821 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RENAME:serializingInsts 521569 # count of serializing insts renamed
+system.cpu1.rename.RENAME:skidInsts 2485864 # count of insts added to the skid buffer
+system.cpu1.rename.RENAME:tempSerializingInsts 55479 # count of temporary serializing insts renamed
+system.cpu1.timesIdled 207727 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.iocache.ReadReq_accesses::1 177 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::1 172 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 172 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 115209.028249 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::1 115273.244186 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency 63209.028249 # average ReadReq mshr miss latency
-system.iocache.ReadReq_miss_latency 20391998 # number of ReadReq miss cycles
+system.iocache.ReadReq_avg_mshr_miss_latency 63273.244186 # average ReadReq mshr miss latency
+system.iocache.ReadReq_miss_latency 19826998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_misses::1 177 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 177 # number of ReadReq misses
-system.iocache.ReadReq_mshr_miss_latency 11187998 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_misses::1 172 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 172 # number of ReadReq misses
+system.iocache.ReadReq_mshr_miss_latency 10882998 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_misses 177 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses 172 # number of ReadReq MSHR misses
system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137839.112582 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137834.973190 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85835.459039 # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency 5727490806 # number of WriteReq miss cycles
+system.iocache.WriteReq_avg_mshr_miss_latency 85831.529120 # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency 5727318806 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
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system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
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system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.avg_refs 0 # Average number of references to valid blocks.
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system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
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system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
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system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
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system.iocache.demand_hits::0 0 # number of demand (read+write) hits
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
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system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
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system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
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system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
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system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
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system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.iocache.overall_hits::0 0 # number of overall hits
system.iocache.overall_hits::1 0 # number of overall hits
system.iocache.overall_hits::total 0 # number of overall hits
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system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
system.iocache.overall_misses::0 0 # number of overall misses
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system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
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system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
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system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.iocache.total_refs 0 # Total number of references to valid blocks.
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system.iocache.writebacks 41520 # number of writebacks
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system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
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system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses
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system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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system.l2c.ReadReq_mshr_hits 18 # number of ReadReq MSHR hits
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system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses
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system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency
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system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
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-system.l2c.UpgradeReq_avg_miss_latency::1 1062484.256087 # average UpgradeReq miss latency
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system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
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system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
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system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 1422860998 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0 431189 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 431189 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 431189 # number of Writeback hits
-system.l2c.Writeback_hits::total 431189 # number of Writeback hits
+system.l2c.WriteReq_mshr_uncacheable_latency 1554057498 # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses::0 446200 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 446200 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0 446200 # number of Writeback hits
+system.l2c.Writeback_hits::total 446200 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 4.720550 # Average number of references to valid blocks.
+system.l2c.avg_refs 4.752489 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 2311310 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 159472 # number of demand (read+write) accesses
+system.l2c.demand_accesses::0 2052724 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 401265 # number of demand (read+write) accesses
system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2470782 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 54449.421319 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 1267083.319196 # average overall miss latency
+system.l2c.demand_accesses::total 2453989 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0 56451.000121 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 694853.664376 # average overall miss latency
system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency
system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40113.084644 # average overall mshr miss latency
-system.l2c.demand_hits::0 1720929 # number of demand (read+write) hits
-system.l2c.demand_hits::1 134102 # number of demand (read+write) hits
+system.l2c.demand_avg_mshr_miss_latency 40111.103615 # average overall mshr miss latency
+system.l2c.demand_hits::0 1490241 # number of demand (read+write) hits
+system.l2c.demand_hits::1 355568 # number of demand (read+write) hits
system.l2c.demand_hits::2 0 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1855031 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 32145903808 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.255431 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.159087 # miss rate for demand accesses
+system.l2c.demand_hits::total 1845809 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 31752727901 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0 0.274018 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.113882 # miss rate for demand accesses
system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses
system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
-system.l2c.demand_misses::0 590381 # number of demand (read+write) misses
-system.l2c.demand_misses::1 25370 # number of demand (read+write) misses
+system.l2c.demand_misses::0 562483 # number of demand (read+write) misses
+system.l2c.demand_misses::1 45697 # number of demand (read+write) misses
system.l2c.demand_misses::2 0 # number of demand (read+write) misses
-system.l2c.demand_misses::total 615751 # number of demand (read+write) misses
+system.l2c.demand_misses::total 608180 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 18 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 24698949947 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0.266400 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 3.861073 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_latency 24394048997 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0 0.296271 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 1.515612 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 615733 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses 608162 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.092624 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.002915 # Average percentage of cache occupancy
-system.l2c.occ_%::2 0.372149 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 6070.232669 # Average occupied blocks per context
-system.l2c.occ_blocks::1 191.043265 # Average occupied blocks per context
-system.l2c.occ_blocks::2 24389.134195 # Average occupied blocks per context
-system.l2c.overall_accesses::0 2311310 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 159472 # number of overall (read+write) accesses
+system.l2c.occ_%::0 0.174396 # Average percentage of cache occupancy
+system.l2c.occ_%::1 0.005052 # Average percentage of cache occupancy
+system.l2c.occ_%::2 0.332288 # Average percentage of cache occupancy
+system.l2c.occ_blocks::0 11429.229058 # Average occupied blocks per context
+system.l2c.occ_blocks::1 331.081192 # Average occupied blocks per context
+system.l2c.occ_blocks::2 21776.825321 # Average occupied blocks per context
+system.l2c.overall_accesses::0 2052724 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 401265 # number of overall (read+write) accesses
system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2470782 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 54449.421319 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 1267083.319196 # average overall miss latency
+system.l2c.overall_accesses::total 2453989 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0 56451.000121 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 694853.664376 # average overall miss latency
system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency
system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40113.084644 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40111.103615 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 1720929 # number of overall hits
-system.l2c.overall_hits::1 134102 # number of overall hits
+system.l2c.overall_hits::0 1490241 # number of overall hits
+system.l2c.overall_hits::1 355568 # number of overall hits
system.l2c.overall_hits::2 0 # number of overall hits
-system.l2c.overall_hits::total 1855031 # number of overall hits
-system.l2c.overall_miss_latency 32145903808 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.255431 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.159087 # miss rate for overall accesses
+system.l2c.overall_hits::total 1845809 # number of overall hits
+system.l2c.overall_miss_latency 31752727901 # number of overall miss cycles
+system.l2c.overall_miss_rate::0 0.274018 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.113882 # miss rate for overall accesses
system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses
system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
-system.l2c.overall_misses::0 590381 # number of overall misses
-system.l2c.overall_misses::1 25370 # number of overall misses
+system.l2c.overall_misses::0 562483 # number of overall misses
+system.l2c.overall_misses::1 45697 # number of overall misses
system.l2c.overall_misses::2 0 # number of overall misses
-system.l2c.overall_misses::total 615751 # number of overall misses
+system.l2c.overall_misses::total 608180 # number of overall misses
system.l2c.overall_mshr_hits 18 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 24698949947 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 0.266400 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 3.861073 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_latency 24394048997 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0 0.296271 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 1.515612 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 615733 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 2263452498 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_misses 608162 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 2394888498 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 399449 # number of replacements
-system.l2c.sampled_refs 433881 # Sample count of references to valid blocks.
+system.l2c.replacements 399060 # number of replacements
+system.l2c.sampled_refs 435274 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 30650.410129 # Cycle average of tags in use
-system.l2c.total_refs 2048157 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 9278771000 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 122161 # number of writebacks
+system.l2c.tagsinuse 33537.135570 # Cycle average of tags in use
+system.l2c.total_refs 2068635 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 9277782000 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 122307 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/home/stever/m5/m5_system_2.0b3/binaries/console
+console=/dist/m5/system/binaries/console
init_param=0
-kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
+load_addr_mask=1099511627775
mem_mode=timing
-pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
+pal=/dist/m5/system/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
[system.disk0.image.child]
type=RawDiskImage
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.terminal]
+Redirecting stdout to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3/simout
+Redirecting stderr to build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Aug 3 2010 18:29:42
-M5 revision 75205c286109 7549 default qtip tip ext/memorderviolation_uncached.patch
-M5 started Aug 3 2010 18:34:19
-M5 executing on harpertown2
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3
+M5 compiled Aug 26 2010 12:51:14
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 12:51:33
+M5 executing on zizzer
+command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /root/ali/dist/system/m5_system_2.0b3/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
+ 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1866391592500 because m5_exit instruction encountered
+Exiting @ tick 1865288389500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 152752 # Simulator instruction rate (inst/s)
-host_mem_usage 285144 # Number of bytes of host memory used
-host_seconds 347.60 # Real time elapsed on the host
-host_tick_rate 5369308609 # Simulator tick rate (ticks/s)
+host_inst_rate 83534 # Simulator instruction rate (inst/s)
+host_mem_usage 292436 # Number of bytes of host memory used
+host_seconds 635.06 # Real time elapsed on the host
+host_tick_rate 2937207030 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 53097060 # Number of instructions simulated
-sim_seconds 1.866392 # Number of seconds simulated
-sim_ticks 1866391592500 # Number of ticks simulated
+sim_insts 53048754 # Number of instructions simulated
+sim_seconds 1.865288 # Number of seconds simulated
+sim_ticks 1865288389500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 6779171 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 13000438 # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect 41604 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 815663 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 12121236 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 14552347 # Number of BP lookups
-system.cpu.BPredUnit.usedRAS 1031270 # Number of times the RAS was used to get a target.
-system.cpu.commit.COM:branches 8463090 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 978521 # number cycles where commit BW limit reached
+system.cpu.BPredUnit.BTBHits 6766434 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 12986969 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 41472 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 813466 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 12097848 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 14524578 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 1028567 # Number of times the RAS was used to get a target.
+system.cpu.commit.COM:branches 8457223 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 1009026 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 100404039 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 0.560651 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.326562 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 98617953 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.570296 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.335991 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 76245214 75.94% 75.94% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 10678082 10.64% 86.57% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 5963966 5.94% 92.51% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 2979105 2.97% 95.48% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 2071048 2.06% 97.54% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 686360 0.68% 98.23% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 408066 0.41% 98.63% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 393677 0.39% 99.03% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 978521 0.97% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 74454640 75.50% 75.50% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 10711227 10.86% 86.36% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 5970777 6.05% 92.41% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 2911969 2.95% 95.37% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 2119464 2.15% 97.52% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 692478 0.70% 98.22% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 398357 0.40% 98.62% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 350015 0.35% 98.98% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 1009026 1.02% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 100404039 # Number of insts commited each cycle
-system.cpu.commit.COM:count 56291624 # Number of instructions committed
-system.cpu.commit.COM:loads 9309237 # Number of loads committed
-system.cpu.commit.COM:membars 227993 # Number of memory barriers committed
-system.cpu.commit.COM:refs 15703046 # Number of memory references committed
+system.cpu.commit.COM:committed_per_cycle::total 98617953 # Number of insts commited each cycle
+system.cpu.commit.COM:count 56241389 # Number of instructions committed
+system.cpu.commit.COM:loads 9301917 # Number of loads committed
+system.cpu.commit.COM:membars 227986 # Number of memory barriers committed
+system.cpu.commit.COM:refs 15690474 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 774037 # The number of times a branch was mispredicted
-system.cpu.commit.commitCommittedInsts 56291624 # The number of committed instructions
-system.cpu.commit.commitNonSpecStalls 667808 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 9441068 # The number of squashed insts skipped by commit
-system.cpu.committedInsts 53097060 # Number of Instructions Simulated
-system.cpu.committedInsts_total 53097060 # Number of Instructions Simulated
-system.cpu.cpi 2.576227 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.576227 # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses::0 214868 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 214868 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15521.971818 # average LoadLockedReq miss latency
+system.cpu.commit.branchMispredicts 771977 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 56241389 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 667741 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 9346936 # The number of squashed insts skipped by commit
+system.cpu.committedInsts 53048754 # Number of Instructions Simulated
+system.cpu.committedInsts_total 53048754 # Number of Instructions Simulated
+system.cpu.cpi 2.541919 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.541919 # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses::0 214829 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 214829 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 15450.383219 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11812.528617 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits::0 192726 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 192726 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency 343687500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103049 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0 22142 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 22142 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_hits 4670 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206388500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081315 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11789.484229 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_hits::0 192518 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 192518 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency 344713500 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103855 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses::0 22311 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 22311 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_hits 4842 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency 205950500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081316 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_misses 17472 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses::0 9342824 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 9342824 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::0 23958.883948 # average ReadReq miss latency
+system.cpu.dcache.LoadLockedReq_mshr_misses 17469 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.ReadReq_accesses::0 9301988 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 9301988 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::0 23801.813261 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22784.089495 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22758.438856 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits::0 7810369 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7810369 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 36715911500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::0 0.164025 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses::0 1532455 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 1532455 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 447788 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 24713150000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116096 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_hits::0 7781909 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 7781909 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 36180636500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate::0 0.163414 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses::0 1520079 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 1520079 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 436579 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 24658768500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116480 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 1084667 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904940500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses::0 219839 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 219839 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56332.793292 # average StoreCondReq miss latency
+system.cpu.dcache.ReadReq_mshr_misses 1083500 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904975000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.StoreCondReq_accesses::0 219792 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 219792 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56335.990566 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53332.793292 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_hits::0 189903 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 189903 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_miss_latency 1686378500 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_rate::0 0.136172 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses::0 29936 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 29936 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_mshr_miss_latency 1596570500 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.136172 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53335.990566 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_hits::0 198592 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 198592 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_miss_latency 1194323000 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_rate::0 0.096455 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_misses::0 21200 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 21200 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_mshr_miss_latency 1130723000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.096455 # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_misses 29936 # number of StoreCondReq MSHR misses
-system.cpu.dcache.WriteReq_accesses::0 6158819 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 6158819 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::0 48967.756734 # average WriteReq miss latency
+system.cpu.dcache.StoreCondReq_mshr_misses 21200 # number of StoreCondReq MSHR misses
+system.cpu.dcache.WriteReq_accesses::0 6153614 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 6153614 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency::0 48733.687858 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 54205.115025 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53794.875061 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits::0 3929838 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 3929838 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 109148199373 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate::0 0.361917 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0 2228981 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2228981 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 1831921 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 21522682972 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.064470 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_hits::0 3986142 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 3986142 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 105628903889 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate::0 0.352227 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0 2167472 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 2167472 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 1799517 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 19794093253 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.059795 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 397060 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235704997 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 9948.209554 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 34000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 8.830631 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 138723 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 1380045474 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 102000 # number of cycles access was blocked
+system.cpu.dcache.WriteReq_mshr_misses 367955 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235122997 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 9816.976394 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 17750 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 8.810921 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 136746 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 1342432254 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 35500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses::0 15501643 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::0 15455602 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 15501643 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::0 38778.836294 # average overall miss latency
+system.cpu.dcache.demand_accesses::total 15455602 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency::0 38456.292642 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 31204.015971 # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0 11740207 # number of demand (read+write) hits
+system.cpu.dcache.demand_avg_mshr_miss_latency 30626.414014 # average overall mshr miss latency
+system.cpu.dcache.demand_hits::0 11768051 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 11740207 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 145864110873 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0 0.242648 # miss rate for demand accesses
+system.cpu.dcache.demand_hits::total 11768051 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 141809540389 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate::0 0.238590 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0 3761436 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::0 3687551 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3761436 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 2279709 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 46235832972 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0 0.095585 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_misses::total 3687551 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 2236096 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 44452861753 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate::0 0.093911 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1481727 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses 1451455 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999991 # Average percentage of cache occupancy
-system.cpu.dcache.occ_%::1 -0.015267 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 511.995427 # Average occupied blocks per context
-system.cpu.dcache.occ_blocks::1 -7.816935 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses::0 15501643 # number of overall (read+write) accesses
+system.cpu.dcache.occ_%::1 -0.007635 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 511.995459 # Average occupied blocks per context
+system.cpu.dcache.occ_blocks::1 -3.909039 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses::0 15455602 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 15501643 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::0 38778.836294 # average overall miss latency
+system.cpu.dcache.overall_accesses::total 15455602 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency::0 38456.292642 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 31204.015971 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 30626.414014 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0 11740207 # number of overall hits
+system.cpu.dcache.overall_hits::0 11768051 # number of overall hits
system.cpu.dcache.overall_hits::1 0 # number of overall hits
-system.cpu.dcache.overall_hits::total 11740207 # number of overall hits
-system.cpu.dcache.overall_miss_latency 145864110873 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0 0.242648 # miss rate for overall accesses
+system.cpu.dcache.overall_hits::total 11768051 # number of overall hits
+system.cpu.dcache.overall_miss_latency 141809540389 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate::0 0.238590 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0 3761436 # number of overall misses
+system.cpu.dcache.overall_misses::0 3687551 # number of overall misses
system.cpu.dcache.overall_misses::1 0 # number of overall misses
-system.cpu.dcache.overall_misses::total 3761436 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 2279709 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 46235832972 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::0 0.095585 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_misses::total 3687551 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 2236096 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 44452861753 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate::0 0.093911 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1481727 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency 2140645497 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_misses 1451455 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency 2140097997 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 1401867 # number of replacements
-system.cpu.dcache.sampled_refs 1402379 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 1400442 # number of replacements
+system.cpu.dcache.sampled_refs 1400954 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 508.086965 # Cycle average of tags in use
-system.cpu.dcache.total_refs 12383892 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 21394000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 430752 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 48365906 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 42626 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 618516 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 72644608 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 37897287 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 12992433 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 1631262 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 135583 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 1148412 # Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses 1233977 # DTB accesses
-system.cpu.dtb.data_acv 814 # DTB access violations
-system.cpu.dtb.data_hits 16773992 # DTB hits
-system.cpu.dtb.data_misses 45116 # DTB misses
+system.cpu.dcache.tagsinuse 510.040943 # Cycle average of tags in use
+system.cpu.dcache.total_refs 12343695 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 21271000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 455265 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 46660710 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 42482 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 616847 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 72473028 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 37849528 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 12958836 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 1616629 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 135444 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 1148878 # Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses 1239402 # DTB accesses
+system.cpu.dtb.data_acv 830 # DTB access violations
+system.cpu.dtb.data_hits 16737953 # DTB hits
+system.cpu.dtb.data_misses 44771 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 912580 # DTB read accesses
-system.cpu.dtb.read_acv 580 # DTB read access violations
-system.cpu.dtb.read_hits 10175278 # DTB read hits
-system.cpu.dtb.read_misses 36864 # DTB read misses
-system.cpu.dtb.write_accesses 321397 # DTB write accesses
-system.cpu.dtb.write_acv 234 # DTB write access violations
-system.cpu.dtb.write_hits 6598714 # DTB write hits
-system.cpu.dtb.write_misses 8252 # DTB write misses
-system.cpu.fetch.Branches 14552347 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 8974775 # Number of cache lines fetched
-system.cpu.fetch.Cycles 23368319 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 459035 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 74152954 # Number of instructions fetch has processed
-system.cpu.fetch.MiscStallCycles 1764 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.SquashCycles 956539 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.106385 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 8974775 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 7810441 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.542093 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 102035301 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.726738 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.024554 # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.read_accesses 913549 # DTB read accesses
+system.cpu.dtb.read_acv 594 # DTB read access violations
+system.cpu.dtb.read_hits 10142643 # DTB read hits
+system.cpu.dtb.read_misses 36670 # DTB read misses
+system.cpu.dtb.write_accesses 325853 # DTB write accesses
+system.cpu.dtb.write_acv 236 # DTB write access violations
+system.cpu.dtb.write_hits 6595310 # DTB write hits
+system.cpu.dtb.write_misses 8101 # DTB write misses
+system.cpu.fetch.Branches 14524578 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 8948260 # Number of cache lines fetched
+system.cpu.fetch.Cycles 23311047 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 456775 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 73989590 # Number of instructions fetch has processed
+system.cpu.fetch.MiscStallCycles 2537 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.SquashCycles 952530 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.107713 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 8948260 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 7795001 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.548698 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 100234582 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.738164 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.038365 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 87682148 85.93% 85.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1045613 1.02% 86.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1977723 1.94% 88.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 941704 0.92% 89.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2994515 2.93% 92.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 665574 0.65% 93.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 793530 0.78% 94.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1216279 1.19% 95.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 4718215 4.62% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 85912196 85.71% 85.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1042441 1.04% 86.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1978378 1.97% 88.72% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 936363 0.93% 89.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2989129 2.98% 92.64% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 664727 0.66% 93.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 787515 0.79% 94.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1214601 1.21% 95.30% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 4709232 4.70% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 102035301 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses::0 8974775 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 8974775 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::0 14904.774114 # average ReadReq miss latency
+system.cpu.fetch.rateDist::total 100234582 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses::0 8948260 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 8948260 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency::0 14907.888251 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11909.268781 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::0 7927523 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 7927523 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 15609054500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::0 0.116688 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::0 1047252 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1047252 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 51900 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 11853914500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0 0.110906 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11902.318660 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits::0 7903415 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 7903415 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 15576432500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate::0 0.116765 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses::0 1044845 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1044845 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 50305 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 11837332000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::0 0.111143 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 995352 # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles::no_mshrs 11612.068966 # average number of cycles each access was blocked
+system.cpu.icache.ReadReq_mshr_misses 994540 # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles::no_mshrs 12104.838710 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 7.966054 # Average number of references to valid blocks.
-system.cpu.icache.blocked::no_mshrs 58 # number of cycles access was blocked
+system.cpu.icache.avg_refs 7.948315 # Average number of references to valid blocks.
+system.cpu.icache.blocked::no_mshrs 62 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_mshrs 673500 # number of cycles access was blocked
+system.cpu.icache.blocked_cycles::no_mshrs 750500 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses::0 8974775 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::0 8948260 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 8974775 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::0 14904.774114 # average overall miss latency
+system.cpu.icache.demand_accesses::total 8948260 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency::0 14907.888251 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11909.268781 # average overall mshr miss latency
-system.cpu.icache.demand_hits::0 7927523 # number of demand (read+write) hits
+system.cpu.icache.demand_avg_mshr_miss_latency 11902.318660 # average overall mshr miss latency
+system.cpu.icache.demand_hits::0 7903415 # number of demand (read+write) hits
system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 7927523 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 15609054500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate::0 0.116688 # miss rate for demand accesses
+system.cpu.icache.demand_hits::total 7903415 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 15576432500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate::0 0.116765 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.icache.demand_misses::0 1047252 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::0 1044845 # number of demand (read+write) misses
system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1047252 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 51900 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 11853914500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate::0 0.110906 # mshr miss rate for demand accesses
+system.cpu.icache.demand_misses::total 1044845 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 50305 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 11837332000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate::0 0.111143 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 995352 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses 994540 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.995668 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 509.782027 # Average occupied blocks per context
-system.cpu.icache.overall_accesses::0 8974775 # number of overall (read+write) accesses
+system.cpu.icache.occ_%::0 0.995598 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 509.746088 # Average occupied blocks per context
+system.cpu.icache.overall_accesses::0 8948260 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 8974775 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency::0 14904.774114 # average overall miss latency
+system.cpu.icache.overall_accesses::total 8948260 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency::0 14907.888251 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11909.268781 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11902.318660 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0 7927523 # number of overall hits
+system.cpu.icache.overall_hits::0 7903415 # number of overall hits
system.cpu.icache.overall_hits::1 0 # number of overall hits
-system.cpu.icache.overall_hits::total 7927523 # number of overall hits
-system.cpu.icache.overall_miss_latency 15609054500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate::0 0.116688 # miss rate for overall accesses
+system.cpu.icache.overall_hits::total 7903415 # number of overall hits
+system.cpu.icache.overall_miss_latency 15576432500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate::0 0.116765 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.icache.overall_misses::0 1047252 # number of overall misses
+system.cpu.icache.overall_misses::0 1044845 # number of overall misses
system.cpu.icache.overall_misses::1 0 # number of overall misses
-system.cpu.icache.overall_misses::total 1047252 # number of overall misses
-system.cpu.icache.overall_mshr_hits 51900 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 11853914500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate::0 0.110906 # mshr miss rate for overall accesses
+system.cpu.icache.overall_misses::total 1044845 # number of overall misses
+system.cpu.icache.overall_mshr_hits 50305 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 11837332000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate::0 0.111143 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 995352 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses 994540 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 994652 # number of replacements
-system.cpu.icache.sampled_refs 995163 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 993840 # number of replacements
+system.cpu.icache.sampled_refs 994351 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 509.782027 # Cycle average of tags in use
-system.cpu.icache.total_refs 7927522 # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle 25287688000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 34754768 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 9169930 # Number of branches executed
-system.cpu.iew.EXEC:nop 3653116 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.421040 # Inst execution rate
-system.cpu.iew.EXEC:refs 17057862 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 6621868 # Number of stores executed
+system.cpu.icache.tagsinuse 509.746088 # Cycle average of tags in use
+system.cpu.icache.total_refs 7903415 # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle 25251004000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks 5 # number of writebacks
+system.cpu.idleCycles 34611048 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 9149461 # Number of branches executed
+system.cpu.iew.EXEC:nop 3645494 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.426187 # Inst execution rate
+system.cpu.iew.EXEC:refs 17021543 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 6618330 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 34608006 # num instructions consuming a value
-system.cpu.iew.WB:count 57003958 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.763082 # average fanout of values written-back
+system.cpu.iew.WB:consumers 34491432 # num instructions consuming a value
+system.cpu.iew.WB:count 56873596 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.763558 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 26408756 # num instructions producing a value
-system.cpu.iew.WB:rate 0.416726 # insts written-back per cycle
-system.cpu.iew.WB:sent 57103806 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 838722 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 9720732 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 11045282 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 1800818 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 1012071 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 7016985 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 65863384 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 10435994 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 546687 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 57594091 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 49608 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 26336207 # num instructions producing a value
+system.cpu.iew.WB:rate 0.421768 # insts written-back per cycle
+system.cpu.iew.WB:sent 56969504 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 835772 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 9640204 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 11032857 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 1798988 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 1002562 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 7014115 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 65718389 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 10403213 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 554442 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 57469408 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 44506 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 6610 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 1631262 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 548180 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 6661 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 1616629 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 544895 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 312153 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 424842 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 8566 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked 306779 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 434666 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 11993 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 45938 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 15913 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1736045 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 623176 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 45938 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 406349 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 432373 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.388165 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.388165 # IPC: Total IPC of All Threads
-system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7290 0.01% 0.01% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu 39624499 68.15% 68.17% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult 62169 0.11% 68.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25611 0.04% 68.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3637 0.01% 68.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.32% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 10788203 18.56% 86.88% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 6676137 11.48% 98.36% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IprAccess 953234 1.64% 100.00% # Type of FU issued
+system.cpu.iew.lsq.thread.0.memOrderViolation 45591 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 18153 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 1730940 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 625558 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 45591 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 404736 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 431036 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.393404 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.393404 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7283 0.01% 0.01% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 39532589 68.13% 68.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 62065 0.11% 68.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.25% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25614 0.04% 68.30% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.30% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.30% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.30% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3637 0.01% 68.30% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.30% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 10774153 18.57% 86.87% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 6665338 11.49% 98.36% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IprAccess 953173 1.64% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 58140780 # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt 443526 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.007628 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 58023852 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 434401 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.007487 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 49984 11.27% 11.27% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.27% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.27% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.27% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.27% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.27% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.27% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.27% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.27% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 286610 64.62% 75.89% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite 106932 24.11% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 47887 11.02% 11.02% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.02% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.02% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.02% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.02% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.02% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.02% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.02% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.02% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 281518 64.81% 75.83% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 104996 24.17% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 102035301 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 0.569810 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.137806 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples 100234582 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.578881 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.146223 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 72990338 71.53% 71.53% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 14544721 14.25% 85.79% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 6428267 6.30% 92.09% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 3926151 3.85% 95.94% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 2521969 2.47% 98.41% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 1036804 1.02% 99.42% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 448412 0.44% 99.86% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 110408 0.11% 99.97% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8 28231 0.03% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 71270288 71.10% 71.10% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 14553068 14.52% 85.62% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 6335877 6.32% 91.94% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 3893576 3.88% 95.83% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 2543708 2.54% 98.37% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 1056426 1.05% 99.42% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 441326 0.44% 99.86% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 109120 0.11% 99.97% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 31193 0.03% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 102035301 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 0.425037 # Inst issue rate
-system.cpu.iq.iqInstsAdded 60158404 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 58140780 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 2051864 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 8719443 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 37043 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 1384056 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 4669750 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total 100234582 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.430298 # Inst issue rate
+system.cpu.iq.iqInstsAdded 60022452 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 58023852 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 2050443 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 8631662 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 41705 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 1382702 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 4647656 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 1303496 # ITB accesses
-system.cpu.itb.fetch_acv 936 # ITB acv
-system.cpu.itb.fetch_hits 1264039 # ITB hits
-system.cpu.itb.fetch_misses 39457 # ITB misses
+system.cpu.itb.fetch_accesses 1304111 # ITB accesses
+system.cpu.itb.fetch_acv 934 # ITB acv
+system.cpu.itb.fetch_hits 1264639 # ITB hits
+system.cpu.itb.fetch_misses 39472 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed
+system.cpu.kern.callpal::swpctx 4178 2.17% 2.17% # number of callpals executed
system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed
-system.cpu.kern.callpal::swpipl 175675 91.19% 93.39% # number of callpals executed
-system.cpu.kern.callpal::rdps 6793 3.53% 96.92% # number of callpals executed
+system.cpu.kern.callpal::swpipl 175665 91.19% 93.39% # number of callpals executed
+system.cpu.kern.callpal::rdps 6792 3.53% 96.92% # number of callpals executed
system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed
-system.cpu.kern.callpal::rti 5220 2.71% 99.64% # number of callpals executed
+system.cpu.kern.callpal::rti 5219 2.71% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 192644 # number of callpals executed
+system.cpu.kern.callpal::total 192634 # number of callpals executed
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.hwrei 211803 # number of hwrei instructions executed
+system.cpu.kern.inst.hwrei 211790 # number of hwrei instructions executed
system.cpu.kern.inst.quiesce 6385 # number of quiesce instructions executed
-system.cpu.kern.ipl_count::0 74956 40.95% 40.95% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::21 237 0.13% 41.08% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22 1889 1.03% 42.12% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 105940 57.88% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 183022 # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0 73589 49.29% 49.29% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count::0 74955 40.96% 40.96% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::21 237 0.13% 41.09% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::22 1888 1.03% 42.12% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::31 105930 57.88% 100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_count::total 183010 # number of times we switched to this ipl
+system.cpu.kern.ipl_good::0 73588 49.29% 49.29% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 237 0.16% 49.45% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22 1889 1.27% 50.71% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31 73589 49.29% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total 149304 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1823811543000 97.72% 97.72% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 102514500 0.01% 97.72% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 392104500 0.02% 97.75% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 42084556500 2.25% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1866390718500 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0 0.981763 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good::22 1888 1.26% 50.71% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::31 73588 49.29% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total 149301 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0 1823061244500 97.74% 97.74% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21 98162000 0.01% 97.74% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22 391950000 0.02% 97.76% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 41736158500 2.24% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1865287515000 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0 0.981762 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31 0.694629 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.mode_good::kernel 1910
-system.cpu.kern.mode_good::user 1740
+system.cpu.kern.ipl_used::31 0.694685 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.mode_good::kernel 1909
+system.cpu.kern.mode_good::user 1739
system.cpu.kern.mode_good::idle 170
-system.cpu.kern.mode_switch::kernel 5969 # number of protection mode switches
-system.cpu.kern.mode_switch::user 1740 # number of protection mode switches
+system.cpu.kern.mode_switch::kernel 5970 # number of protection mode switches
+system.cpu.kern.mode_switch::user 1739 # number of protection mode switches
system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches
-system.cpu.kern.mode_switch_good::kernel 0.319987 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::kernel 0.319765 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total 1.401132 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 31305722000 1.68% 1.68% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 3191321000 0.17% 1.85% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1831893667500 98.15% 100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context 4177 # number of times the context was actually changed
+system.cpu.kern.mode_switch_good::total 1.400911 # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel 31031458000 1.66% 1.66% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user 3177312000 0.17% 1.83% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1831078737000 98.17% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context 4179 # number of times the context was actually changed
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu.kern.syscall::total 326 # number of syscalls executed
-system.cpu.memDep0.conflictingLoads 3074116 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2796142 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 11045282 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 7016985 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 136790069 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 14275602 # Number of cycles rename is blocking
-system.cpu.rename.RENAME:CommittedMaps 38263165 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 1103259 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 39498573 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 2244862 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 15668 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 83383655 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 68588182 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 45977130 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 12625374 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 1631262 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 5234920 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 7713963 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 28769568 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 1705106 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 12848723 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 257016 # count of temporary serializing insts renamed
-system.cpu.timesIdled 1324942 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.memDep0.conflictingLoads 3098880 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2694658 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 11032857 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 7014115 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 134845630 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 14093810 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 38225332 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IQFullEvents 1080811 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 39441227 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 2214917 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 14670 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 83145881 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 68419430 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 45844130 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 12603060 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 1616629 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 5180630 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 7618796 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 27299224 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 1703562 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 12710348 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 255623 # count of temporary serializing insts renamed
+system.cpu.timesIdled 1320206 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 115277.445087 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency 63277.445087 # average ReadReq mshr miss latency
-system.iocache.ReadReq_miss_latency 19942998 # number of ReadReq miss cycles
+system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency
+system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_misses::1 173 # number of ReadReq misses
system.iocache.ReadReq_misses::total 173 # number of ReadReq misses
-system.iocache.ReadReq_mshr_miss_latency 10946998 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
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system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
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system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
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system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
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system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.avg_refs 0 # Average number of references to valid blocks.
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system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
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system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
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system.iocache.demand_hits::0 0 # number of demand (read+write) hits
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
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system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
system.iocache.demand_misses::1 41725 # number of demand (read+write) misses
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
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system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
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system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.iocache.overall_hits::0 0 # number of overall hits
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system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
system.iocache.overall_misses::1 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
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system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
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system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
system.iocache.replacements 41685 # number of replacements
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 1.259751 # Cycle average of tags in use
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system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.warmup_cycle 1716179733000 # Cycle when the warmup percentage was hit.
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system.iocache.writebacks 41512 # number of writebacks
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system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
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system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
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system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits
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system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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system.l2c.SCUpgradeReq_avg_miss_latency::1 inf # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency
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system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
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system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
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system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
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system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
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system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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-system.l2c.Writeback_accesses::total 430752 # number of Writeback accesses(hits+misses)
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-system.l2c.Writeback_hits::total 430752 # number of Writeback hits
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+system.l2c.Writeback_hits::total 455270 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
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system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses
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system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency
system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
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system.l2c.demand_hits::1 0 # number of demand (read+write) hits
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system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses
system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
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system.l2c.demand_misses::1 0 # number of demand (read+write) misses
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system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits
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system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.090384 # Average percentage of cache occupancy
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+system.l2c.occ_blocks::0 11568.063937 # Average occupied blocks per context
+system.l2c.occ_blocks::1 21331.159568 # Average occupied blocks per context
+system.l2c.overall_accesses::0 2395532 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2397771 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 52206.280446 # average overall miss latency
+system.l2c.overall_accesses::total 2395532 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0 52206.057388 # average overall miss latency
system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency
system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40114.981715 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40113.108078 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 1785564 # number of overall hits
+system.l2c.overall_hits::0 1787144 # number of overall hits
system.l2c.overall_hits::1 0 # number of overall hits
-system.l2c.overall_hits::total 1785564 # number of overall hits
-system.l2c.overall_miss_latency 31961050333 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.255323 # miss rate for overall accesses
+system.l2c.overall_hits::total 1787144 # number of overall hits
+system.l2c.overall_miss_latency 31761538842 # number of overall miss cycles
+system.l2c.overall_miss_rate::0 0.253968 # miss rate for overall accesses
system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses
system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
-system.l2c.overall_misses::0 612207 # number of overall misses
+system.l2c.overall_misses::0 608388 # number of overall misses
system.l2c.overall_misses::1 0 # number of overall misses
-system.l2c.overall_misses::total 612207 # number of overall misses
+system.l2c.overall_misses::total 608388 # number of overall misses
system.l2c.overall_mshr_hits 1 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 24558632496 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 0.255323 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_latency 24404293484 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0 0.253967 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 612206 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 1926664998 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_misses 608387 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 1926105498 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 396159 # number of replacements
-system.l2c.sampled_refs 427780 # Sample count of references to valid blocks.
+system.l2c.replacements 394069 # number of replacements
+system.l2c.sampled_refs 426267 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 30721.225374 # Cycle average of tags in use
-system.l2c.total_refs 1967340 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 5645112000 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 119153 # number of writebacks
+system.l2c.tagsinuse 32899.223505 # Cycle average of tags in use
+system.l2c.total_refs 2000592 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 5644310000 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 118209 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
egid=100
env=
errout=cerr
+Redirecting stdout to build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Aug 24 2010 15:34:40
-M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
-M5 started Aug 24 2010 15:38:31
+M5 compiled Aug 26 2010 13:52:30
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 14:11:34
M5 executing on zizzer
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 152158072000 because target called exit()
+Exiting @ tick 152155526000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 1413696 # Simulator instruction rate (inst/s)
-host_mem_usage 343480 # Number of bytes of host memory used
-host_seconds 64.50 # Real time elapsed on the host
-host_tick_rate 2359219725 # Simulator tick rate (ticks/s)
+host_inst_rate 1008175 # Simulator instruction rate (inst/s)
+host_mem_usage 344580 # Number of bytes of host memory used
+host_seconds 90.44 # Real time elapsed on the host
+host_tick_rate 1682447495 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91176087 # Number of instructions simulated
-sim_seconds 0.152158 # Number of seconds simulated
-sim_ticks 152158072000 # Number of ticks simulated
+sim_seconds 0.152156 # Number of seconds simulated
+sim_ticks 152155526000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 22564820 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14013.903608 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.903608 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_mshr_miss_rate 0.039894 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 900198 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 4738868 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 4642722 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 5384176000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.020289 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 96146 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 5095738000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.020289 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 96146 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 55998.688893 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52998.688893 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 4642766 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 5381586000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.020280 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 96102 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 5093280000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.020280 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 96102 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 27.837649 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 27303688 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 18065.511510 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 15065.511510 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 26307344 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 17999464000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.036491 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 996344 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 18063.709726 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 15063.709726 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 26307388 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 17996874000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.036490 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 996300 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 15010432000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.036491 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 996344 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 15007974000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.036490 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 996300 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.874740 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 3582.934837 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.874745 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 3582.956819 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 27303688 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 18065.511510 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 15065.511510 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 18063.709726 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 15063.709726 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 26307344 # number of overall hits
-system.cpu.dcache.overall_miss_latency 17999464000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.036491 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 996344 # number of overall misses
+system.cpu.dcache.overall_hits 26307388 # number of overall hits
+system.cpu.dcache.overall_miss_latency 17996874000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.036490 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 996300 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 15010432000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.036491 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 996344 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 15007974000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.036490 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 996300 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 942711 # number of replacements
system.cpu.dcache.sampled_refs 946807 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 3582.934837 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 3582.956819 # Cycle average of tags in use
system.cpu.dcache.total_refs 26356881 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 54489025000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 96053 # number of writebacks
+system.cpu.dcache.warmup_cycle 54487870000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 96132 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.249734 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 511.454894 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.249735 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 511.457636 # Average occupied blocks per context
system.cpu.icache.overall_accesses 107819118 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 54667.779633 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 51667.779633 # average overall mshr miss latency
system.cpu.icache.replacements 2 # number of replacements
system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 511.454894 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 511.457636 # Cycle average of tags in use
system.cpu.icache.total_refs 107818519 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadExReq_accesses 46609 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 2423668000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 46609 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1864360000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 46609 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits
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+system.cpu.l2cache.ReadExReq_miss_rate 0.999936 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 46606 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1864240000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999936 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 46606 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 900797 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_latency 35120000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.000975 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 878 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 49537 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses 49493 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 2575924000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 2573636000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 49537 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1981480000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 49493 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1979720000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 49537 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 96053 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 96053 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_mshr_misses 49493 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 96132 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 96132 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 52.567404 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 52.533433 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 947406 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 899919 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 2469324000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.050123 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 47487 # number of demand (read+write) misses
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+system.cpu.l2cache.demand_miss_rate 0.050120 # miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 1899480000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.050123 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 47487 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 1899360000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.050120 # mshr miss rate for demand accesses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.009182 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.265752 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 300.880505 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 8708.164911 # Average occupied blocks per context
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+system.cpu.l2cache.occ_blocks::0 320.609441 # Average occupied blocks per context
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system.cpu.l2cache.overall_accesses 947406 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 899919 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 2469324000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.050123 # miss rate for overall accesses
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+system.cpu.l2cache.overall_miss_rate 0.050120 # miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 1899480000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.050123 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 47487 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 1899360000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.050120 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 47484 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 678 # number of replacements
-system.cpu.l2cache.sampled_refs 15333 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 15344 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 9009.045417 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 806016 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 9016.719375 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 806073 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 35 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 304316144 # number of cpu cycles simulated
+system.cpu.numCycles 304311052 # number of cpu cycles simulated
system.cpu.num_insts 91176087 # Number of instructions executed
system.cpu.num_refs 27330336 # Number of memory references
system.cpu.workload.PROG:num_syscalls 442 # Number of system calls
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
+cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/mcf
+executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
gid=100
-input=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
+Redirecting stdout to build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Feb 25 2010 03:11:27
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:30:29
-M5 executing on SC2B0619
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/10.mcf/sparc/linux/simple-timing
+M5 compiled Aug 26 2010 13:03:41
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:06:13
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 366435406000 because target called exit()
+Exiting @ tick 366433850000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 794629 # Simulator instruction rate (inst/s)
-host_mem_usage 325576 # Number of bytes of host memory used
-host_seconds 306.85 # Real time elapsed on the host
-host_tick_rate 1194166006 # Simulator tick rate (ticks/s)
+host_inst_rate 994564 # Simulator instruction rate (inst/s)
+host_mem_usage 343716 # Number of bytes of host memory used
+host_seconds 245.17 # Real time elapsed on the host
+host_tick_rate 1494621764 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 243835278 # Number of instructions simulated
-sim_seconds 0.366435 # Number of seconds simulated
-sim_ticks 366435406000 # Number of ticks simulated
+sim_seconds 0.366434 # Number of seconds simulated
+sim_ticks 366433850000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 14009.690242 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.690242 # average ReadReq mshr miss latency
system.cpu.dcache.SwapReq_mshr_miss_rate 0.002059 # mshr miss rate for SwapReq accesses
system.cpu.dcache.SwapReq_mshr_misses 8 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 22901951 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 22806988 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 5317928000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.004147 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 94963 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 5033039000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.004147 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 94963 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 18046.382944 # average overall miss latency
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system.cpu.dcache.demand_miss_rate 0.009397 # miss rate for demand accesses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_rate 0.009397 # mshr miss rate for demand accesses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 104134565 # number of overall hits
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system.cpu.dcache.overall_miss_rate 0.009397 # miss rate for overall accesses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_rate 0.009397 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 987820 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 935475 # number of replacements
system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 3569.622607 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 3569.628477 # Cycle average of tags in use
system.cpu.dcache.total_refs 104186700 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 134379688000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 94877 # number of writebacks
+system.cpu.dcache.warmup_cycle 134378918000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 94947 # number of writebacks
system.cpu.icache.ReadReq_accesses 244421512 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 55904.761905 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 52904.761905 # average ReadReq mshr miss latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.occ_%::0 0.354611 # Average percentage of cache occupancy
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system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55904.761905 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52904.761905 # average overall mshr miss latency
system.cpu.icache.replacements 25 # number of replacements
system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 726.242454 # Cycle average of tags in use
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system.cpu.icache.total_refs 244420630 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadExReq_accesses 46714 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 2429128000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 46714 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1868560000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 46714 # number of ReadExReq MSHR misses
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1868440000 # number of ReadExReq MSHR miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_misses 46711 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 893739 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_latency 43440000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001215 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 1086 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 48257 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 2509364000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 2508012000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 48257 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1930280000 # number of UpgradeReq MSHR miss cycles
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+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1929240000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 48257 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 94877 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 94877 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_mshr_misses 48231 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 94947 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 94947 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 51.559226 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 940453 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 892653 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 2485600000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.050827 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 47800 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 1912000000 # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.demand_mshr_misses 47800 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.010976 # Average percentage of cache occupancy
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-system.cpu.l2cache.occ_blocks::1 8599.756547 # Average occupied blocks per context
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system.cpu.l2cache.overall_accesses 940453 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 892653 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 2485600000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.050827 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 47800 # number of overall misses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 1912000000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.050827 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 47800 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 1911880000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.050823 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 47797 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 891 # number of replacements
-system.cpu.l2cache.sampled_refs 15559 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 15566 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 8959.416448 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 802210 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 8964.628794 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 802243 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 41 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 732870812 # number of cpu cycles simulated
+system.cpu.numCycles 732867700 # number of cpu cycles simulated
system.cpu.num_insts 243835278 # Number of instructions executed
system.cpu.num_refs 105711442 # Number of memory references
system.cpu.workload.PROG:num_syscalls 443 # Number of system calls
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
+cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
egid=100
env=
errout=cerr
+Redirecting stdout to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled May 2 2010 23:23:01
-M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
-M5 started May 2 2010 23:23:02
-M5 executing on burrito
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/10.mcf/x86/linux/simple-timing
+M5 compiled Aug 26 2010 13:20:12
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:47:25
+M5 executing on zizzer
+command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 382077495000 because target called exit()
+Exiting @ tick 378879619000 because target called exit()
---------- Begin Simulation Statistics ----------
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 70890 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 764154990 # number of cpu cycles simulated
+system.cpu.numCycles 757759238 # number of cpu cycles simulated
system.cpu.num_insts 269696010 # Number of instructions executed
system.cpu.num_refs 122219139 # Number of memory references
system.cpu.workload.PROG:num_syscalls 444 # Number of system calls
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
-cwd=build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
egid=100
env=
errout=cerr
+Redirecting stdout to build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Aug 24 2010 15:34:40
-M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
-M5 started Aug 24 2010 15:39:26
+M5 compiled Aug 26 2010 13:52:30
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:57:01
M5 executing on zizzer
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 755274721000 because target called exit()
+Exiting @ tick 745672616000 because target called exit()
---------- Begin Simulation Statistics ----------
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sim_freq 1000000000000 # Frequency of simulated ticks
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 258533 # number of replacements
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu.l2cache.writebacks 186433 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1510549442 # number of cpu cycles simulated
+system.cpu.numCycles 1491345232 # number of cpu cycles simulated
system.cpu.num_insts 559470527 # Number of instructions executed
system.cpu.num_refs 184987503 # Number of memory references
system.cpu.workload.PROG:num_syscalls 548 # Number of system calls
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
-cwd=build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
+cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
egid=100
env=
errout=cerr
+Redirecting stdout to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled May 2 2010 23:23:01
-M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
-M5 started May 2 2010 23:23:02
-M5 executing on burrito
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/20.parser/x86/linux/simple-timing
+M5 compiled Aug 26 2010 13:20:12
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:22:00
+M5 executing on zizzer
+command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 1722332515000 because target called exit()
+Exiting @ tick 1701783891000 because target called exit()
---------- Begin Simulation Statistics ----------
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sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1495700521 # Number of instructions simulated
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system.cpu.dcache.ReadReq_accesses 384102189 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_hits 382374775 # number of ReadReq hits
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system.cpu.dcache.ReadReq_miss_rate 0.004497 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.004497 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.replacements 2514362 # number of replacements
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system.cpu.icache.ReadReq_avg_miss_latency 48626.865672 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 45626.865672 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadExReq_accesses 791044 # number of ReadExReq accesses(hits+misses)
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-system.cpu.l2cache.overall_mshr_miss_latency 48437800000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.480291 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 1210945 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 43515760000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.431486 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 1087894 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 664035 # number of replacements
-system.cpu.l2cache.sampled_refs 680440 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 603454 # number of replacements
+system.cpu.l2cache.sampled_refs 621473 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 17212.897835 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 2329996 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 921653687000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 481618 # number of writebacks
+system.cpu.l2cache.tagsinuse 19824.270630 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 2471683 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 910963647000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 436481 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 3444665030 # number of cpu cycles simulated
+system.cpu.numCycles 3403567782 # number of cpu cycles simulated
system.cpu.num_insts 1495700521 # Number of instructions executed
system.cpu.num_refs 533262345 # Number of memory references
system.cpu.workload.PROG:num_syscalls 551 # Number of system calls
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
12 8 14
13 8 14
14 8 14
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing/simerr
+Redirecting stdout to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jun 6 2010 03:04:38
-M5 revision ba1a0193c050 7448 default tip
-M5 started Jun 6 2010 03:04:42
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:52:05
M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.133333
+Exiting @ tick 136571603500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 242260 # Simulator instruction rate (inst/s)
-host_mem_usage 213404 # Number of bytes of host memory used
-host_seconds 1550.30 # Real time elapsed on the host
-host_tick_rate 86851686 # Simulator tick rate (ticks/s)
+host_inst_rate 136199 # Simulator instruction rate (inst/s)
+host_mem_usage 214028 # Number of bytes of host memory used
+host_seconds 2757.55 # Real time elapsed on the host
+host_tick_rate 49526494 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 375574819 # Number of instructions simulated
-sim_seconds 0.134646 # Number of seconds simulated
-sim_ticks 134646047500 # Number of ticks simulated
+sim_seconds 0.136572 # Number of seconds simulated
+sim_ticks 136571603500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 35411688 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 43873215 # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect 1393 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 5500503 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 35240813 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 62127254 # Number of BP lookups
-system.cpu.BPredUnit.usedRAS 12478438 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.BTBHits 34712245 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 43971564 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 1375 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 5750083 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 35466067 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 62830534 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 12729193 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 44587532 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 13023462 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 12727499 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 253935739 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 1.569943 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 2.243237 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 257005436 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.551191 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 2.213326 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 122688628 48.31% 48.31% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 50190176 19.76% 68.08% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 18710011 7.37% 75.45% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 19547996 7.70% 83.15% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 12735073 5.02% 88.16% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 8256826 3.25% 91.41% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 5486679 2.16% 93.57% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 3296888 1.30% 94.87% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 13023462 5.13% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 123174402 47.93% 47.93% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 51601116 20.08% 68.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 20452287 7.96% 75.96% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 20740884 8.07% 84.03% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 11122877 4.33% 88.36% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 8764041 3.41% 91.77% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 5151763 2.00% 93.78% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 3270567 1.27% 95.05% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 12727499 4.95% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 253935739 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 257005436 # Number of insts commited each cycle
system.cpu.commit.COM:count 398664594 # Number of instructions committed
system.cpu.commit.COM:loads 100651995 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 174183397 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 5496166 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 5745758 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 95019473 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 99827575 # The number of squashed insts skipped by commit
system.cpu.committedInsts 375574819 # Number of Instructions Simulated
system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated
-system.cpu.cpi 0.717013 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.717013 # CPI: Total CPI of All Threads
-system.cpu.dcache.LoadLockedReq_accesses 1 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_hits 1 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 95369422 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 33035.714286 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31908.121827 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 95367714 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 56425000 # number of ReadReq miss cycles
+system.cpu.cpi 0.727267 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.727267 # CPI: Total CPI of All Threads
+system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits
+system.cpu.dcache.ReadReq_accesses 95959241 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 33093.582888 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31984.199796 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 95957558 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 55696500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1708 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 723 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 31429500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_misses 1683 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 702 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 31376500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 985 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses 981 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 30397.287074 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36179.950785 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 73502664 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 549126991 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000246 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 18065 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 14753 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 119827997 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 3312 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 3499.727273 # average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_avg_miss_latency 30331.836439 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36071.185392 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 73502803 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 543728500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000244 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 17926 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 14695 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 116546000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 3231 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 40390.006697 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
+system.cpu.dcache.avg_refs 40579.607280 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 38497 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 168890151 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 30625.195519 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35200.720735 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 168870378 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 605551991 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000117 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 19773 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 15476 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 151257497 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_accesses 169479970 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 30568.871437 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35119.301994 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 169460361 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 599425000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000116 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 19609 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 15397 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 147922500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 4297 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses 4212 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.804196 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 3293.985737 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 168890151 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 30625.195519 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35200.720735 # average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.804256 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 3294.233360 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 169479970 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 30568.871437 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35119.301994 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 168870378 # number of overall hits
-system.cpu.dcache.overall_miss_latency 605551991 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000117 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 19773 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 15476 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 151257497 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_hits 169460361 # number of overall hits
+system.cpu.dcache.overall_miss_latency 599425000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000116 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 19609 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 15397 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 147922500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 4297 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses 4212 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 786 # number of replacements
-system.cpu.dcache.sampled_refs 4181 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 781 # number of replacements
+system.cpu.dcache.sampled_refs 4176 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 3293.985737 # Cycle average of tags in use
-system.cpu.dcache.total_refs 168870618 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 3294.233360 # Cycle average of tags in use
+system.cpu.dcache.total_refs 169460440 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 639 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 20455851 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 4411 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 11313984 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 531721678 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 132373008 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 100014717 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 15215664 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 13188 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 1092163 # Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses 184984239 # DTB accesses
-system.cpu.dtb.data_acv 1 # DTB access violations
-system.cpu.dtb.data_hits 184965275 # DTB hits
-system.cpu.dtb.data_misses 18964 # DTB misses
+system.cpu.dcache.writebacks 638 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 21059081 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 4405 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 11508131 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 539100093 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 134649980 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 100169012 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 15996729 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 13181 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 1127363 # Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses 185557278 # DTB accesses
+system.cpu.dtb.data_acv 0 # DTB access violations
+system.cpu.dtb.data_hits 185509117 # DTB hits
+system.cpu.dtb.data_misses 48161 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 104315848 # DTB read accesses
+system.cpu.dtb.read_accesses 105313060 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 104298344 # DTB read hits
-system.cpu.dtb.read_misses 17504 # DTB read misses
-system.cpu.dtb.write_accesses 80668391 # DTB write accesses
-system.cpu.dtb.write_acv 1 # DTB write access violations
-system.cpu.dtb.write_hits 80666931 # DTB write hits
-system.cpu.dtb.write_misses 1460 # DTB write misses
-system.cpu.fetch.Branches 62127254 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 63793845 # Number of cache lines fetched
-system.cpu.fetch.Cycles 167246591 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 1555705 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 544184292 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 5877257 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.230706 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 63793845 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 47890126 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 2.020796 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 269151403 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.021852 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.019136 # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.read_hits 105266355 # DTB read hits
+system.cpu.dtb.read_misses 46705 # DTB read misses
+system.cpu.dtb.write_accesses 80244218 # DTB write accesses
+system.cpu.dtb.write_acv 0 # DTB write access violations
+system.cpu.dtb.write_hits 80242762 # DTB write hits
+system.cpu.dtb.write_misses 1456 # DTB write misses
+system.cpu.fetch.Branches 62830534 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 64860863 # Number of cache lines fetched
+system.cpu.fetch.Cycles 168703371 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 1410406 # Number of outstanding Icache misses that were squashed
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+system.cpu.fetch.predictedBranches 47441438 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 2.022934 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 273002165 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.023979 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.024544 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 165698966 61.56% 61.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 11106934 4.13% 65.69% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 11530416 4.28% 69.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 6307474 2.34% 72.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 14437862 5.36% 77.68% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 9686725 3.60% 81.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 7134176 2.65% 83.93% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 3886825 1.44% 85.38% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 39362025 14.62% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 169159964 61.96% 61.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 10172385 3.73% 65.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 10846224 3.97% 69.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 7014396 2.57% 72.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 14631841 5.36% 77.59% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 9961062 3.65% 81.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 7189550 2.63% 83.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 4041352 1.48% 85.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 39985391 14.65% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 269151403 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses 63793845 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 32214.491857 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 30831.032720 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 63788994 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 156272500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 4851 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 939 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 120611000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 3912 # number of ReadReq MSHR misses
+system.cpu.fetch.rateDist::total 273002165 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 64860863 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 32283.674736 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 30878.201844 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 64856030 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 156027000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000075 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 4833 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 929 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 120548500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000060 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 3904 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 16305.980061 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 16612.712602 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 63793845 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 32214.491857 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 30831.032720 # average overall mshr miss latency
-system.cpu.icache.demand_hits 63788994 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 156272500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses
-system.cpu.icache.demand_misses 4851 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 939 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 120611000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 3912 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 64860863 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 32283.674736 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 30878.201844 # average overall mshr miss latency
+system.cpu.icache.demand_hits 64856030 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 156027000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000075 # miss rate for demand accesses
+system.cpu.icache.demand_misses 4833 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 929 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 120548500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000060 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 3904 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.890533 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1823.811736 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 63793845 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 32214.491857 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 30831.032720 # average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.891431 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1825.650576 # Average occupied blocks per context
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+system.cpu.icache.overall_avg_miss_latency 32283.674736 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 30878.201844 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 63788994 # number of overall hits
-system.cpu.icache.overall_miss_latency 156272500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses
-system.cpu.icache.overall_misses 4851 # number of overall misses
-system.cpu.icache.overall_mshr_hits 939 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 120611000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 3912 # number of overall MSHR misses
+system.cpu.icache.overall_hits 64856030 # number of overall hits
+system.cpu.icache.overall_miss_latency 156027000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000075 # miss rate for overall accesses
+system.cpu.icache.overall_misses 4833 # number of overall misses
+system.cpu.icache.overall_mshr_hits 929 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 120548500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000060 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 3904 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 1991 # number of replacements
-system.cpu.icache.sampled_refs 3912 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 1982 # number of replacements
+system.cpu.icache.sampled_refs 3904 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1823.811736 # Cycle average of tags in use
-system.cpu.icache.total_refs 63788994 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1825.650576 # Cycle average of tags in use
+system.cpu.icache.total_refs 64856030 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 140695 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 51026412 # Number of branches executed
-system.cpu.iew.EXEC:nop 27112711 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.557485 # Inst execution rate
-system.cpu.iew.EXEC:refs 191688570 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 80679099 # Number of stores executed
+system.cpu.idleCycles 141045 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 51385726 # Number of branches executed
+system.cpu.iew.EXEC:nop 27755438 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.545021 # Inst execution rate
+system.cpu.iew.EXEC:refs 192526473 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 80254900 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 288216530 # num instructions consuming a value
-system.cpu.iew.WB:count 415792778 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.699054 # average fanout of values written-back
+system.cpu.iew.WB:consumers 290066917 # num instructions consuming a value
+system.cpu.iew.WB:count 417830932 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.699779 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 201478800 # num instructions producing a value
-system.cpu.iew.WB:rate 1.544021 # insts written-back per cycle
-system.cpu.iew.WB:sent 416379790 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 6053312 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 2368258 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 124922222 # Number of dispatched load instructions
+system.cpu.iew.WB:producers 202982772 # num instructions producing a value
+system.cpu.iew.WB:rate 1.529714 # insts written-back per cycle
+system.cpu.iew.WB:sent 418648136 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 6175903 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 3284723 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 125889658 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 241 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 6336167 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 92376215 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 493684492 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 111009471 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 9414741 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 419418502 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 122120 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewDispSquashedInsts 6874932 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 92903281 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 498492595 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 112271573 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 9215998 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 422011987 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 145222 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 26143 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 15215664 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 517890 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 28045 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 15996729 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 550279 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 33 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 8752772 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 41071 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 9131244 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 2248 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 605872 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 176126 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 24270227 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 18844813 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 605872 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 1054390 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 4998922 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 1.394674 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.394674 # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation 648565 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 175867 # Number of loads that were rescheduled
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+system.cpu.iew.lsq.thread.0.squashedStores 19371879 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 648565 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 1211280 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 4964623 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 1.375011 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.375011 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued
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-system.cpu.iq.ISSUE:FU_type_0::IntMult 2152798 0.50% 39.31% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 39.31% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 34694447 8.09% 47.40% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp 7781263 1.81% 49.22% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2950957 0.69% 49.91% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 16800389 3.92% 53.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 1571056 0.37% 54.19% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.19% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 113131674 26.38% 80.57% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 83311342 19.43% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 168382264 39.05% 39.05% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 2152290 0.50% 39.55% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 39.55% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 34830384 8.08% 47.63% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 7781044 1.80% 49.44% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2959993 0.69% 50.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 16854742 3.91% 54.03% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 1589897 0.37% 54.40% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.40% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 114726286 26.60% 81.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 81917504 19.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 428833243 # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt 10058147 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.023455 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 431227985 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 9397735 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.021793 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 25860 0.26% 0.26% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.26% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.26% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd 93260 0.93% 1.18% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp 5650 0.06% 1.24% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt 7446 0.07% 1.31% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult 1317455 13.10% 14.41% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv 1454078 14.46% 28.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 28.87% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 5920939 58.87% 87.74% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite 1233459 12.26% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 51470 0.55% 0.55% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.55% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd 51324 0.55% 1.09% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp 3037 0.03% 1.13% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt 5843 0.06% 1.19% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 1281381 13.63% 14.82% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv 969484 10.32% 25.14% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 25.14% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 5699185 60.64% 85.78% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 1336011 14.22% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 269151403 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 1.593279 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.717169 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples 273002165 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 1.579577 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.704793 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 98731931 36.68% 36.68% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 57661044 21.42% 58.11% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 40586976 15.08% 73.19% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 29421704 10.93% 84.12% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 23908046 8.88% 93.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 10239078 3.80% 96.80% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 5871323 2.18% 98.99% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 2172785 0.81% 99.79% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8 558516 0.21% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 100185843 36.70% 36.70% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 58377873 21.38% 58.08% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 43478311 15.93% 74.01% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 28530639 10.45% 84.46% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 23283249 8.53% 92.99% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 11208488 4.11% 97.09% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 5200545 1.90% 99.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 1974869 0.72% 99.72% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 762348 0.28% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 269151403 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 1.592446 # Inst issue rate
-system.cpu.iq.iqInstsAdded 466571540 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 428833243 # Number of instructions issued
+system.cpu.iq.ISSUE:issued_per_cycle::total 273002165 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 1.578762 # Inst issue rate
+system.cpu.iq.iqInstsAdded 470736916 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 431227985 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 241 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 89966373 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 863763 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 94399417 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 779543 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 26 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 69307198 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 72495736 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 63794154 # ITB accesses
+system.cpu.itb.fetch_accesses 64861170 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_hits 63793845 # ITB hits
-system.cpu.itb.fetch_misses 309 # ITB misses
+system.cpu.itb.fetch_hits 64860863 # ITB hits
+system.cpu.itb.fetch_misses 307 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 3200 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34587.968437 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31457.812500 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 110681499 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 3200 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 100665000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 3200 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 4893 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34357.615894 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31171.594134 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 665 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 145264000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.864092 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 4228 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 131793500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864092 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 4228 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 119 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34466.386555 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31289.915966 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 4101500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_accesses 3199 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34578.066333 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31448.372966 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 110511500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.999062 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 3196 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 100509000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999062 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 3196 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 4881 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34355.892097 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31170.255561 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 655 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 145188000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.865806 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 4226 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 131725500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.865806 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 4226 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 36 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34236.111111 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 1232500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 119 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3723500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 36 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1116000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 119 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 639 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 639 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2666.666667 # average number of cycles each access was blocked
+system.cpu.l2cache.UpgradeReq_mshr_misses 36 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 638 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 638 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.131910 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked
+system.cpu.l2cache.avg_refs 0.134782 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs 8000 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 8093 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34456.852316 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31294.897684 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 665 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 255945499 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.917830 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 7428 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 8080 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34451.562921 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31290.016168 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 658 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 255699500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.918564 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 7422 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 232458500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.917830 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 7428 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 232234500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.918564 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 7422 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.106843 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.011587 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 3501.040941 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 379.684950 # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses 8093 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34456.852316 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31294.897684 # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0 0.108617 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.011284 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 3559.151087 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 369.756870 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 8080 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34451.562921 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31290.016168 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 665 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 255945499 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.917830 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 7428 # number of overall misses
+system.cpu.l2cache.overall_hits 658 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 255699500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.918564 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 7422 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 232458500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.917830 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 7428 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 232234500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.918564 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 7422 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 15 # number of replacements
-system.cpu.l2cache.sampled_refs 4685 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 14 # number of replacements
+system.cpu.l2cache.sampled_refs 4741 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 3880.725891 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 618 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 3928.907957 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 639 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.memDep0.conflictingLoads 74849853 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 55363768 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 124922222 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 92376215 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 269292098 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 9673248 # Number of cycles rename is blocking
+system.cpu.memDep0.conflictingLoads 73373175 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 55113413 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 125889658 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 92903281 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 273143210 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 10612512 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 1504479 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 137416112 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 8012015 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:IQFullEvents 2173514 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 139438532 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 7156113 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 682754738 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 518229128 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 335302113 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 95729398 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 15215664 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 10747190 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 75769772 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 369791 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 37587 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 23404736 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 258 # count of temporary serializing insts renamed
-system.cpu.timesIdled 3105 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:RenameLookups 690877715 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 524876259 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 339660686 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 96195896 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 15996729 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 10389927 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 80128345 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 368569 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 37570 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 22417777 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 259 # count of temporary serializing insts renamed
+system.cpu.timesIdled 3102 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
---------- End Simulation Statistics ----------
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/eon
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
12 8 14
13 8 14
14 8 14
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
+Redirecting stdout to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Feb 24 2010 23:12:40
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 02:20:32
-M5 executing on SC2B0619
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:52:05
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.566667
+Exiting @ tick 567347489000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 860135 # Simulator instruction rate (inst/s)
-host_mem_usage 198216 # Number of bytes of host memory used
-host_seconds 463.49 # Real time elapsed on the host
-host_tick_rate 1224083493 # Simulator tick rate (ticks/s)
+host_inst_rate 1188061 # Simulator instruction rate (inst/s)
+host_mem_usage 213244 # Number of bytes of host memory used
+host_seconds 335.56 # Real time elapsed on the host
+host_tick_rate 1690751695 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 398664609 # Number of instructions simulated
-sim_seconds 0.567352 # Number of seconds simulated
-sim_ticks 567351850000 # Number of ticks simulated
+sim_seconds 0.567347 # Number of seconds simulated
+sim_ticks 567347489000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 94754490 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 73520730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 73517416 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 185584000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000045 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 3314 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 175642000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000045 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 3314 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 55961.075070 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52961.075070 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 73517493 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 181146000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 3237 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 171435000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 3237 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 40527.713873 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 168275220 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 54847.560976 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 168270956 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 233870000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_avg_miss_latency 54796.274182 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 51796.274182 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 168271033 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 229432000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 4264 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses 4187 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 221078000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 216871000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 4264 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses 4187 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.802954 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 3288.899192 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.802957 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 3288.911680 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 168275220 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 54847.560976 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51847.560976 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 54796.274182 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 51796.274182 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 168270956 # number of overall hits
-system.cpu.dcache.overall_miss_latency 233870000 # number of overall miss cycles
+system.cpu.dcache.overall_hits 168271033 # number of overall hits
+system.cpu.dcache.overall_miss_latency 229432000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 4264 # number of overall misses
+system.cpu.dcache.overall_misses 4187 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 221078000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 216871000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 4264 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses 4187 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 764 # number of replacements
system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 3288.899192 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 3288.911680 # Cycle average of tags in use
system.cpu.dcache.total_refs 168271068 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 625 # number of writebacks
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.876526 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1795.124700 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.876529 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1795.130856 # Average occupied blocks per context
system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199 # average overall mshr miss latency
system.cpu.icache.replacements 1769 # number of replacements
system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1795.124700 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1795.130856 # Cycle average of tags in use
system.cpu.icache.total_refs 398660993 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadExReq_accesses 3202 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 166504000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 3202 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 128080000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 3202 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits 3 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 166348000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.999063 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 3199 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 127960000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999063 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 3199 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 4623 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_latency 161520000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 112 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses 35 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 5824000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 1820000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 112 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4480000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 35 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1400000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 112 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses 35 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.120240 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.125220 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 7825 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 585 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 376480000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.925240 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 7240 # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits 588 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 376324000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.924856 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 7237 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 289600000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.925240 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 7240 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 289480000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.924856 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 7237 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.101996 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.011352 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 3342.203160 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 371.972955 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.103673 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.011078 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 3397.172145 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 362.997313 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 7825 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 585 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 376480000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.925240 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 7240 # number of overall misses
+system.cpu.l2cache.overall_hits 588 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 376324000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.924856 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 7237 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 289600000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.925240 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 7240 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 289480000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.924856 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 7237 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 15 # number of replacements
-system.cpu.l2cache.sampled_refs 4491 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 14 # number of replacements
+system.cpu.l2cache.sampled_refs 4544 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 3714.176115 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 540 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 3760.169458 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 569 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1134703700 # number of cpu cycles simulated
+system.cpu.numCycles 1134694978 # number of cpu cycles simulated
system.cpu.num_insts 398664609 # Number of instructions executed
system.cpu.num_refs 174183455 # Number of memory references
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
egid=100
env=
errout=cerr
+Redirecting stdout to build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Aug 24 2010 15:34:40
-M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
-M5 started Aug 24 2010 15:37:41
+M5 compiled Aug 26 2010 13:52:30
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:52:33
M5 executing on zizzer
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
OO-style eon Time= 0.520000
-Exiting @ tick 525836291000 because target called exit()
+Exiting @ tick 525827779000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 1023413 # Simulator instruction rate (inst/s)
-host_mem_usage 218276 # Number of bytes of host memory used
-host_seconds 336.52 # Real time elapsed on the host
-host_tick_rate 1562566741 # Simulator tick rate (ticks/s)
+host_inst_rate 898977 # Simulator instruction rate (inst/s)
+host_mem_usage 219380 # Number of bytes of host memory used
+host_seconds 383.10 # Real time elapsed on the host
+host_tick_rate 1372552338 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 344399678 # Number of instructions simulated
-sim_seconds 0.525836 # Number of seconds simulated
-sim_ticks 525836291000 # Number of ticks simulated
+sim_seconds 0.525828 # Number of seconds simulated
+sim_ticks 525827779000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 94586725 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 49727.442439 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46727.442439 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000017 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1607 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 82063572 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 82060523 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 170744000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000037 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 3049 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 161597000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000037 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 3049 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 55985.492228 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52985.492228 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 82060677 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 162078000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000035 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 2895 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 153393000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000035 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 2895 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 39438.673365 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 176650297 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 53835.051546 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 50835.051546 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 176645641 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 250656000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000026 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 4656 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 53751.665926 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 50751.665926 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 176645795 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 241990000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 4502 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 236688000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000026 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 4656 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 228484000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 4502 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.751811 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 3079.417400 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.751814 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 3079.430321 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 176650297 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 53835.051546 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 50835.051546 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 53751.665926 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 50751.665926 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 176645641 # number of overall hits
-system.cpu.dcache.overall_miss_latency 250656000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000026 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 4656 # number of overall misses
+system.cpu.dcache.overall_hits 176645795 # number of overall hits
+system.cpu.dcache.overall_miss_latency 241990000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 4502 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 236688000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000026 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 4656 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 228484000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 4502 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 1332 # number of replacements
system.cpu.dcache.sampled_refs 4479 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 3079.417400 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 3079.430321 # Cycle average of tags in use
system.cpu.dcache.total_refs 176645818 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 974 # number of writebacks
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.862302 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1765.994016 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.862305 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1766.000778 # Average occupied blocks per context
system.cpu.icache.overall_accesses 348627536 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 21025.572005 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 18025.572005 # average overall mshr miss latency
system.cpu.icache.replacements 13796 # number of replacements
system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1765.994016 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1766.000778 # Cycle average of tags in use
system.cpu.icache.total_refs 348611933 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadExReq_accesses 2872 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 149344000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 2872 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 114880000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 2872 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits 1 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 149292000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.999652 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 2871 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 114840000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999652 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 2871 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 17210 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_mshr_miss_latency 159080000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.231087 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3977 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 177 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses 23 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 9204000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 1196000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 177 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7080000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 23 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 920000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 177 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses 23 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 974 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 974 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 2.776587 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 2.717391 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 20082 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 13233 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 356148000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.341052 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 6849 # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits 13234 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 356096000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.341002 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 6848 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 273960000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.341052 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 6849 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 273920000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.341002 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 6848 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.091337 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.010370 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 2992.938866 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 339.814124 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.095645 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.010365 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 3134.105136 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 339.639233 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 20082 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 13233 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 356148000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.341052 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 6849 # number of overall misses
+system.cpu.l2cache.overall_hits 13234 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 356096000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.341002 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 6848 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 273960000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.341052 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 6849 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 273920000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.341002 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 6848 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 48 # number of replacements
-system.cpu.l2cache.sampled_refs 4758 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 4876 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 3332.752990 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 13211 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 3473.744369 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 13250 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1051672582 # number of cpu cycles simulated
+system.cpu.numCycles 1051655558 # number of cpu cycles simulated
system.cpu.num_insts 344399678 # Number of instructions executed
system.cpu.num_refs 177028576 # Number of memory references
system.cpu.workload.PROG:num_syscalls 191 # Number of system calls
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
+cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
For more information see: http://www.m5sim.org/warn/d946bea6
warn: ignoring syscall sigprocmask(0, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing/simerr
+Redirecting stdout to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jun 6 2010 03:04:38
-M5 revision ba1a0193c050 7448 default tip
-M5 started Jun 6 2010 03:07:52
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 12:01:20
M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
2000: 760651391
1000: 4031656975
0: 2206428413
+Exiting @ tick 702688811500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 150652 # Simulator instruction rate (inst/s)
-host_mem_usage 214040 # Number of bytes of host memory used
-host_seconds 12101.02 # Real time elapsed on the host
-host_tick_rate 57884111 # Simulator tick rate (ticks/s)
+host_inst_rate 105247 # Simulator instruction rate (inst/s)
+host_mem_usage 214344 # Number of bytes of host memory used
+host_seconds 17321.56 # Real time elapsed on the host
+host_tick_rate 40567294 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1823043370 # Number of instructions simulated
-sim_seconds 0.700457 # Number of seconds simulated
-sim_ticks 700456762500 # Number of ticks simulated
+sim_seconds 0.702689 # Number of seconds simulated
+sim_ticks 702688811500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 237313176 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 290294551 # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect 3578 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 28357853 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 231827098 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 346133867 # Number of BP lookups
-system.cpu.BPredUnit.usedRAS 49328779 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.BTBHits 239396241 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 292393914 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 3599 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 28358143 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 232710596 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 347019771 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 49329086 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 266706457 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 69311011 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 67430429 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 1302157693 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 1.542814 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 2.203929 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 1305107182 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.539328 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 2.193562 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 596380613 45.80% 45.80% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 273242120 20.98% 66.78% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 173533589 13.33% 80.11% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 65306568 5.02% 85.13% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 48690140 3.74% 88.86% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 33944722 2.61% 91.47% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 18456166 1.42% 92.89% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 23292764 1.79% 94.68% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 69311011 5.32% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 596079504 45.67% 45.67% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 274005611 20.99% 66.67% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 176024939 13.49% 80.16% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 67867193 5.20% 85.36% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 46132467 3.53% 88.89% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 33942844 2.60% 91.49% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 19726349 1.51% 93.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 23897846 1.83% 94.83% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 67430429 5.17% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 1302157693 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 1305107182 # Number of insts commited each cycle
system.cpu.commit.COM:count 2008987604 # Number of instructions committed
system.cpu.commit.COM:loads 511595302 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 722390433 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 28346017 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 28346322 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 686852992 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 694586134 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
-system.cpu.cpi 0.768448 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.768448 # CPI: Total CPI of All Threads
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-system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 463363512 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 37524.078898 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34794.219854 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 461428955 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 72592469500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.004175 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 1934557 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 475286 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 50774196000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.003149 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 1459271 # number of ReadReq MSHR misses
+system.cpu.cpi 0.770896 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.770896 # CPI: Total CPI of All Threads
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+system.cpu.dcache.LoadLockedReq_hits 8 # number of LoadLockedReq hits
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+system.cpu.dcache.ReadReq_avg_miss_latency 37466.685698 # average ReadReq miss latency
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+system.cpu.dcache.ReadReq_mshr_miss_latency 50656079000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 38582.382670 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36523.414699 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 210235446 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 21584913985 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.002654 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 559450 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 484668 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 2731293998 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 74782 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 4879.241379 # average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_avg_miss_latency 38589.512736 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36524.349360 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 210236618 # number of WriteReq hits
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system.cpu.dcache.avg_blocked_cycles::no_targets 14500 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 438.740100 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 29 # number of cycles access was blocked
+system.cpu.dcache.avg_refs 438.700297 # Average number of references to valid blocks.
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system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 141498 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 14500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.demand_avg_miss_latency 37761.475202 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 34878.514626 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 671664401 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 94177383485 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.003699 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2494007 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 959954 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 53505489998 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.002276 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1534053 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 674153748 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 37718.232311 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 34798.041826 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 671661766 # number of demand (read+write) hits
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+system.cpu.dcache.demand_miss_rate 0.003696 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2491982 # number of demand (read+write) misses
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+system.cpu.dcache.demand_mshr_miss_latency 53368852000 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.999780 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4095.099733 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 674158408 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 37761.475202 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 34878.514626 # average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.999781 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4095.104320 # Average occupied blocks per context
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+system.cpu.dcache.overall_avg_mshr_miss_latency 34798.041826 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 671664401 # number of overall hits
-system.cpu.dcache.overall_miss_latency 94177383485 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.003699 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2494007 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 959954 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 53505489998 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.002276 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1534053 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 671661766 # number of overall hits
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+system.cpu.dcache.overall_misses 2491982 # number of overall misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 1526826 # number of replacements
-system.cpu.dcache.sampled_refs 1530922 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 1526954 # number of replacements
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.099733 # Cycle average of tags in use
-system.cpu.dcache.total_refs 671676872 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 274383000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 74589 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 32140341 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 12074 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 30417175 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 2923062124 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 711773443 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 558159581 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 98598096 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 45812 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 84328 # Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses 772918649 # DTB accesses
+system.cpu.dcache.tagsinuse 4095.104320 # Cycle average of tags in use
+system.cpu.dcache.total_refs 671672090 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 274011000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 74616 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 31207203 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 12052 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 30419221 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 2934529925 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 711825403 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 561989361 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 100109049 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 45710 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 85215 # Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses 772921338 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_hits 772293170 # DTB hits
-system.cpu.dtb.data_misses 625479 # DTB misses
+system.cpu.dtb.data_hits 772287215 # DTB hits
+system.cpu.dtb.data_misses 634123 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 514591069 # DTB read accesses
+system.cpu.dtb.read_accesses 514592222 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 514003488 # DTB read hits
-system.cpu.dtb.read_misses 587581 # DTB read misses
-system.cpu.dtb.write_accesses 258327580 # DTB write accesses
+system.cpu.dtb.read_hits 513995856 # DTB read hits
+system.cpu.dtb.read_misses 596366 # DTB read misses
+system.cpu.dtb.write_accesses 258329116 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 258289682 # DTB write hits
-system.cpu.dtb.write_misses 37898 # DTB write misses
-system.cpu.fetch.Branches 346133867 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 346369631 # Number of cache lines fetched
-system.cpu.fetch.Cycles 922290632 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 4326238 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 3015904698 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 28794725 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.247077 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 346369631 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 286641955 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 2.152813 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 1400755789 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.153055 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.032526 # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.write_hits 258291359 # DTB write hits
+system.cpu.dtb.write_misses 37757 # DTB write misses
+system.cpu.fetch.Branches 347019771 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 347236210 # Number of cache lines fetched
+system.cpu.fetch.Cycles 925540339 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 4572630 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 3016868050 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 28795074 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.246923 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 347236210 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 288725327 # Number of branches that fetch has predicted taken
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+system.cpu.fetch.rateDist::mean 2.146907 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 824834992 58.88% 58.88% # Number of instructions fetched each cycle (Total)
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-system.cpu.fetch.rateDist::2 38924738 2.78% 65.46% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 62366133 4.45% 69.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 120532729 8.60% 78.52% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 35808657 2.56% 81.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 38526871 2.75% 83.83% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 7024237 0.50% 84.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 219530615 15.67% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 826912311 58.85% 58.85% # Number of instructions fetched each cycle (Total)
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+system.cpu.fetch.rateDist::4 121409089 8.64% 78.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 34600240 2.46% 81.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 37932193 2.70% 83.88% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 7024441 0.50% 84.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 219549827 15.62% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1400755789 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses 346369631 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 15843.963981 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11642.396973 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 346358970 # number of ReadReq hits
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+system.cpu.fetch.rateDist::total 1405216231 # Number of instructions fetched each cycle (Total)
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system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 10661 # number of ReadReq misses
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 9779 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses 9785 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 35418.649146 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 35489.118050 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 346369631 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 15843.963981 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11642.396973 # average overall mshr miss latency
-system.cpu.icache.demand_hits 346358970 # number of demand (read+write) hits
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+system.cpu.icache.demand_accesses 347236210 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 15852.092893 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11646.295350 # average overall mshr miss latency
+system.cpu.icache.demand_hits 347225531 # number of demand (read+write) hits
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system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses
-system.cpu.icache.demand_misses 10661 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 882 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 113851000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_misses 10679 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 894 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 113959000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 9779 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses 9785 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.788131 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1614.092315 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 346369631 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 15843.963981 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11642.396973 # average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.787162 # Average percentage of cache occupancy
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+system.cpu.icache.overall_avg_miss_latency 15852.092893 # average overall miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 346358970 # number of overall hits
-system.cpu.icache.overall_miss_latency 168912500 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses
-system.cpu.icache.overall_misses 10661 # number of overall misses
-system.cpu.icache.overall_mshr_hits 882 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 113851000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_misses 10679 # number of overall misses
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system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 9779 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses 9785 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 8106 # number of replacements
-system.cpu.icache.sampled_refs 9779 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 8113 # number of replacements
+system.cpu.icache.sampled_refs 9784 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1614.092315 # Cycle average of tags in use
-system.cpu.icache.total_refs 346358970 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1612.107078 # Cycle average of tags in use
+system.cpu.icache.total_refs 347225531 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 157737 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 273840918 # Number of branches executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 1628963056 # num instructions consuming a value
-system.cpu.iew.WB:count 1998305294 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.696273 # average fanout of values written-back
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+system.cpu.iew.WB:fanout 0.695811 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 1134203072 # num instructions producing a value
-system.cpu.iew.WB:rate 1.426430 # insts written-back per cycle
-system.cpu.iew.WB:sent 1999262446 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 30877558 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 3458881 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 652332333 # Number of dispatched load instructions
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-system.cpu.iew.iewDispSquashedInsts 52328 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 302847672 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 2706062248 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 515125790 # Number of load instructions executed
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-system.cpu.iew.iewExecutedInsts 1999323821 # Number of executed instructions
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+system.cpu.iew.WB:sent 2001905607 # cumulative count of insts sent to commit
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 2941 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 98598096 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 141241 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 1380 # Number of times the LSQ has become full, causing a stall
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+system.cpu.iew.iewUnblockCycles 140868 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 63 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 50635810 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 214 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 3618 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 4111 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 140737031 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 92052541 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 3618 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 787831 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 30089727 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 1.301325 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.301325 # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation 3782 # Number of memory ordering violations
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+system.cpu.ipc 1.297191 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.297191 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued
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-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204646 0.35% 59.77% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 59.77% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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-system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.02% # attempts to use FU when none available
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-system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.02% # attempts to use FU when none available
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-system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 0.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.02% # attempts to use FU when none available
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-system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.02% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 27908776 75.34% 75.36% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu.iq.ISSUE:issued_per_cycle::2 272843485 19.48% 77.62% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 155156600 11.08% 88.70% # Number of insts issued each cycle
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-system.cpu.iq.ISSUE:issued_per_cycle::8 2963430 0.21% 100.00% # Number of insts issued each cycle
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system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 1400755789 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 1.487136 # Inst issue rate
-system.cpu.iq.iqInstsAdded 2377648640 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 2083348648 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 67 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 554578210 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 12403574 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 512095612 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total 1405216231 # Number of insts issued each cycle
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+system.cpu.iq.iqSquashedInstsExamined 561606840 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 12399741 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 25 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 517624785 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 346369835 # ITB accesses
+system.cpu.itb.fetch_accesses 347236419 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
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-system.cpu.itb.fetch_misses 204 # ITB misses
+system.cpu.itb.fetch_hits 347236210 # ITB hits
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system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 71651 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 35090.884984 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.644583 # average ReadExReq mshr miss latency
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+system.cpu.l2cache.ReadExReq_avg_miss_latency 35091.445798 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32065.513824 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 71651 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2297535500 # number of ReadExReq MSHR miss cycles
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system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
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-system.cpu.l2cache.ReadReq_accesses 1469050 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34290.352977 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.454128 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 28927 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 49382326000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.980309 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 1440123 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 44644467000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980309 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 1440123 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 3136 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34061.702806 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31036.830357 # average UpgradeReq mshr miss latency
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+system.cpu.l2cache.ReadReq_avg_miss_latency 34207.393582 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.426347 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 29045 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 49263470000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.980231 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 1440141 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 44644985000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980231 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 1440141 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 2624 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34296.875000 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31001.905488 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 89995000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 3136 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 97331500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 2624 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 81349000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 3136 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6458.333333 # average number of cycles each access was blocked
+system.cpu.l2cache.UpgradeReq_mshr_misses 2624 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 74616 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 74616 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7200 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.023460 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 12 # number of cycles access was blocked
+system.cpu.l2cache.avg_refs 0.023753 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs 77500 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 36000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 1540701 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34328.294441 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.939162 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 28927 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 51896623000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.981225 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 1511774 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 1540835 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34249.291899 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31050.904557 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 29045 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 51777737000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.981150 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 1511790 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 46942002500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.981225 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 1511774 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 46942447000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.981150 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 1511790 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.927763 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.046370 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 30400.923469 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 1519.457016 # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses 1540701 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34328.294441 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.939162 # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0 0.927958 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.046323 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 30407.323461 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 1517.897239 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 1540835 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34249.291899 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31050.904557 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 28927 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 51896623000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.981225 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 1511774 # number of overall misses
+system.cpu.l2cache.overall_hits 29045 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 51777737000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.981150 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 1511790 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 46942002500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.981225 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 1511774 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 46942447000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.981150 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 1511790 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 1474248 # number of replacements
-system.cpu.l2cache.sampled_refs 1506806 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 1474292 # number of replacements
+system.cpu.l2cache.sampled_refs 1506959 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 31920.380484 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 35349 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 31925.220700 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 35795 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 66899 # number of writebacks
-system.cpu.memDep0.conflictingLoads 118618588 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 21042992 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 652332333 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 302847672 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 1400913526 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 20115016 # Number of cycles rename is blocking
+system.cpu.memDep0.conflictingLoads 126385471 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 12290638 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 655963109 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 302851236 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 1405377624 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 20016233 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 673890 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 725392322 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 11324949 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:IQFullEvents 673555 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 725805122 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 10749358 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 18 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 3294871470 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 2827359257 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 1880881832 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 543088621 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 98598096 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 13538505 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 495912762 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 23229 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 2930 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 27590681 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 73 # count of temporary serializing insts renamed
-system.cpu.timesIdled 4075 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:RenameLookups 3307765426 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 2838518766 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 1890285688 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 546657671 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 100109049 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 12606278 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 505316618 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 21878 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 2883 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 26993135 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 69 # count of temporary serializing insts renamed
+system.cpu.timesIdled 4180 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
---------- End Simulation Statistics ----------
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE_MOESI_hammer/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
gid=100
input=cin
max_stack_size=67108864
For more information see: http://www.m5sim.org/warn/d946bea6
warn: ignoring syscall sigprocmask(0, 1, ...)
For more information see: http://www.m5sim.org/warn/5c5b547f
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
+Redirecting stdout to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Feb 24 2010 23:12:54
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 01:51:28
-M5 executing on SC2B0619
-command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:52:14
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
2000: 760651391
1000: 4031656975
0: 2206428413
+Exiting @ tick 2814926000000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 1237577 # Simulator instruction rate (inst/s)
-host_mem_usage 198020 # Number of bytes of host memory used
-host_seconds 1623.32 # Real time elapsed on the host
-host_tick_rate 1734066560 # Simulator tick rate (ticks/s)
+host_inst_rate 1265087 # Simulator instruction rate (inst/s)
+host_mem_usage 213100 # Number of bytes of host memory used
+host_seconds 1588.02 # Real time elapsed on the host
+host_tick_rate 1772597573 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2008987605 # Number of instructions simulated
-sim_seconds 2.814951 # Number of seconds simulated
-sim_ticks 2814951154000 # Number of ticks simulated
+sim_seconds 2.814926 # Number of seconds simulated
+sim_ticks 2814926000000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 55392.232299 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52392.232299 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 55392.203496 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52392.203496 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 80772510000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 80772468000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 76397934000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 76397892000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.692460 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.692460 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 210720109 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 4188049000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000355 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 74787 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 3963688000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000355 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 74787 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 210720566 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 4162480000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000353 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 74330 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 3939490000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000353 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 74330 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55421.867488 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52421.867488 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 720331943 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 84960559000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.002124 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1532979 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 55421.682690 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52421.682690 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 720332400 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 84934948000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.002123 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1532522 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 80361622000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.002124 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1532979 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 80337382000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.002123 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 1532522 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.999804 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4095.198740 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.999806 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4095.205038 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55421.867488 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52421.867488 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 55421.682690 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52421.682690 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 720331943 # number of overall hits
-system.cpu.dcache.overall_miss_latency 84960559000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.002124 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1532979 # number of overall misses
+system.cpu.dcache.overall_hits 720332400 # number of overall hits
+system.cpu.dcache.overall_miss_latency 84934948000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.002123 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1532522 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 80361622000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.002124 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1532979 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 80337382000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.002123 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 1532522 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 1526048 # number of replacements
system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4095.198740 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4095.205038 # Cycle average of tags in use
system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 1054514000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 74589 # number of writebacks
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system.cpu.dtb.data_accesses 722298387 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 721864922 # DTB hits
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.721885 # Average percentage of cache occupancy
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system.cpu.icache.overall_accesses 2009421071 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 23421.857305 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305 # average overall mshr miss latency
system.cpu.icache.replacements 9046 # number of replacements
system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1478.420115 # Cycle average of tags in use
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system.cpu.icache.total_refs 2009410475 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadReq_accesses 1468788 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 29320 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 74852336000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.980038 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 1439468 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 57578720000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.980038 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 1439468 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 2835 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51578.130511 # average UpgradeReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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-system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 74589 # number of Writeback hits
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.demand_miss_rate 0.980970 # miss rate for demand accesses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.l2cache.demand_mshr_miss_rate 0.980970 # mshr miss rate for demand accesses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 29320 # number of overall hits
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system.cpu.l2cache.overall_miss_rate 0.980970 # miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_miss_rate 0.980970 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 1473608 # number of replacements
-system.cpu.l2cache.sampled_refs 1506166 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 66899 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 5629902308 # number of cpu cycles simulated
+system.cpu.numCycles 5629852000 # number of cpu cycles simulated
system.cpu.num_insts 2008987605 # Number of instructions executed
system.cpu.num_refs 722823898 # Number of memory references
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
egid=100
env=
errout=cerr
+Redirecting stdout to build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Aug 24 2010 15:34:40
-M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
-M5 started Aug 24 2010 15:43:18
+M5 compiled Aug 26 2010 13:52:30
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 14:03:19
M5 executing on zizzer
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
2000: 760651391
1000: 4031656975
0: 2206428413
-Exiting @ tick 2371369572000 because target called exit()
+Exiting @ tick 2371349716000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 1398740 # Simulator instruction rate (inst/s)
-host_mem_usage 215468 # Number of bytes of host memory used
-host_seconds 1310.23 # Real time elapsed on the host
-host_tick_rate 1809883950 # Simulator tick rate (ticks/s)
+host_inst_rate 1110314 # Simulator instruction rate (inst/s)
+host_mem_usage 216744 # Number of bytes of host memory used
+host_seconds 1650.59 # Real time elapsed on the host
+host_tick_rate 1436666087 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1832675505 # Number of instructions simulated
-sim_seconds 2.371370 # Number of seconds simulated
-sim_ticks 2371369572000 # Number of ticks simulated
+sim_seconds 2.371350 # Number of seconds simulated
+sim_ticks 2371349716000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 620364065 # number of ReadReq accesses(hits+misses)
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52313.788145 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 55313.730657 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52313.730657 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 618902904 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 80822350000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.002355 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 1461161 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 76438867000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 76438783000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002355 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 1461161 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 276945663 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.799022 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.799022 # average WriteReq mshr miss latency
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-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 74635 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 55999.434541 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.434541 # average WriteReq mshr miss latency
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 583.970170 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 897309728 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55347.126181 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52347.126181 # average overall mshr miss latency
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-system.cpu.dcache.demand_miss_rate 0.001712 # miss rate for demand accesses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 80394507000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.001712 # mshr miss rate for demand accesses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.999747 # Average percentage of cache occupancy
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system.cpu.dcache.overall_accesses 897309728 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 80394507000 # number of overall MSHR miss cycles
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-system.cpu.dcache.overall_mshr_misses 1535796 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 1529845 # number of replacements
system.cpu.dcache.sampled_refs 1533941 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4094.964018 # Cycle average of tags in use
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system.cpu.dcache.total_refs 895775787 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 995704000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 74508 # number of writebacks
+system.cpu.dcache.warmup_cycle 993999000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 74582 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 1390241555 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 18784.729586 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 15784.729586 # average overall mshr miss latency
system.cpu.icache.replacements 18364 # number of replacements
system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1392.324951 # Cycle average of tags in use
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system.cpu.icache.total_refs 1390221752 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadExReq_accesses 72780 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 3784560000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 72780 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2911200000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 72780 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits 1 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 3784508000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.999986 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 72779 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2911160000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999986 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 72779 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 1480964 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 41420 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 74856288000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.972032 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 1439544 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 57581760000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.972032 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 1439544 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 1855 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51579.514825 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadReq_hits 41422 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 74856184000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.972030 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 1439542 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 57581680000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.972030 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 1439542 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 1496 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 95680000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 77792000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 1855 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 74200000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 1496 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 59840000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 1855 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 74508 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 74508 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_mshr_misses 1496 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 74582 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 74582 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.032124 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.032374 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 1553744 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 41420 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 78640848000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.973342 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 1512324 # number of demand (read+write) misses
+system.cpu.l2cache.demand_hits 41423 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 78640692000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.973340 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 1512321 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 60492960000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.973342 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 1512324 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 60492840000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.973340 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 1512321 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.927309 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.046837 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 30386.057269 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 1534.770026 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.927467 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.046803 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 30391.242944 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 1533.635543 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 1553744 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 41420 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 78640848000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.973342 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 1512324 # number of overall misses
+system.cpu.l2cache.overall_hits 41423 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 78640692000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.973340 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 1512321 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 60492960000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.973342 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 1512324 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 60492840000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.973340 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 1512321 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 1472870 # number of replacements
-system.cpu.l2cache.sampled_refs 1505525 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 1472894 # number of replacements
+system.cpu.l2cache.sampled_refs 1505603 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 31920.827295 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 48363 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 31924.878487 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 48742 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 66101 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 4742739144 # number of cpu cycles simulated
+system.cpu.numCycles 4742699432 # number of cpu cycles simulated
system.cpu.num_insts 1832675505 # Number of instructions executed
system.cpu.num_refs 908401146 # Number of memory references
system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
For more information see: http://www.m5sim.org/warn/8028fa22
warn: Write Hints currently unimplemented
For more information see: http://www.m5sim.org/warn/cfb3293b
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
+Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jun 25 2010 15:39:41
-M5 revision 93b1ca421839+ 7482+ default qtip tip update_regr
-M5 started Jun 25 2010 16:11:25
-M5 executing on zooks
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:52:06
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
+Exiting @ tick 104900991500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 46297 # Simulator instruction rate (inst/s)
-host_mem_usage 167032 # Number of bytes of host memory used
-host_seconds 1908.12 # Real time elapsed on the host
-host_tick_rate 55055354 # Simulator tick rate (ticks/s)
+host_inst_rate 31368 # Simulator instruction rate (inst/s)
+host_mem_usage 223704 # Number of bytes of host memory used
+host_seconds 2816.26 # Real time elapsed on the host
+host_tick_rate 37248320 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
-sim_seconds 0.105052 # Number of seconds simulated
-sim_ticks 105052358500 # Number of ticks simulated
+sim_seconds 0.104901 # Number of seconds simulated
+sim_ticks 104900991500 # Number of ticks simulated
system.cpu.AGEN-Unit.agens 35224018 # Number of Address Generations
system.cpu.Branch-Predictor.BTBHitPct 41.015608 # BTB Hit Percentage
system.cpu.Branch-Predictor.BTBHits 4719981 # Number of BTB hits
system.cpu.Execution-Unit.predictedTakenIncorrect 217237 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed
system.cpu.Mult-Div-Unit.multiplies 41101 # Number of Multipy Operations Executed
-system.cpu.RegFile-Manager.regFileAccesses 156428920 # Number of Total Accesses (Read+Write) to the Register File
-system.cpu.RegFile-Manager.regFileReads 103882039 # Number of Reads from Register File
+system.cpu.RegFile-Manager.regFileAccesses 156429013 # Number of Total Accesses (Read+Write) to the Register File
+system.cpu.RegFile-Manager.regFileReads 103882132 # Number of Reads from Register File
system.cpu.RegFile-Manager.regFileWrites 52546881 # Number of Writes to Register File
-system.cpu.RegFile-Manager.regForwards 2136326 # Number of Registers Read Through Forwarding Logic
-system.cpu.activity 84.633296 # Percentage of cycles cpu is active
+system.cpu.RegFile-Manager.regForwards 2136233 # Number of Registers Read Through Forwarding Logic
+system.cpu.activity 84.755939 # Percentage of cycles cpu is active
system.cpu.comBranches 13754477 # Number of Branches instructions committed
system.cpu.comFloats 151453 # Number of Floating Point instructions committed
system.cpu.comInts 30457224 # Number of Integer instructions committed
system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total)
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.cpi 2.378346 # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total 2.378346 # CPI: Total CPI of All Threads
+system.cpu.cpi 2.374919 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total 2.374919 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 38171.526841 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35064.773064 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 38051.171708 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34943.916006 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2319531000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 2312217500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 2130746000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 2123402000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56426.999259 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53426.999259 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 8452369500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 8002990500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 56416.363760 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53416.289024 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 14466192 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 8303642500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.010072 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 147185 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 7862076500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.010072 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 147185 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 51158.585005 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 48127.776538 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 34679456 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 10771900500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 210559 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 51049.814620 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 48018.420205 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 34682064 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 10615860000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.005960 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 207951 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 10133736500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.006035 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 210559 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 9985478500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.005960 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 207951 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.995308 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4076.781631 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.995330 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4076.871208 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 51158.585005 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 48127.776538 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 51049.814620 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 48018.420205 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 34679456 # number of overall hits
-system.cpu.dcache.overall_miss_latency 10771900500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.006035 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 210559 # number of overall misses
+system.cpu.dcache.overall_hits 34682064 # number of overall hits
+system.cpu.dcache.overall_miss_latency 10615860000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.005960 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 207951 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 10133736500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.006035 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 210559 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 9985478500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.005960 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 207951 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 200248 # number of replacements
system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4076.781631 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4076.871208 # Cycle average of tags in use
system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 838762000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 147714 # number of writebacks
+system.cpu.dcache.warmup_cycle 834930000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 149164 # number of writebacks
system.cpu.dtb.data_accesses 34987415 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 34890015 # DTB hits
system.cpu.dtb.write_hits 14613377 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.icache.ReadReq_accesses 97023272 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 19069.814885 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15852.089330 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 19062.290643 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 15844.379626 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 96943862 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 1514334000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 1513736500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000818 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 79410 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 1586 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 1233673000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 1233073000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000802 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 77824 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.blocked_cycles::no_targets 4000 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 97023272 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 19069.814885 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15852.089330 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 19062.290643 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 15844.379626 # average overall mshr miss latency
system.cpu.icache.demand_hits 96943862 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 1514334000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 1513736500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000818 # miss rate for demand accesses
system.cpu.icache.demand_misses 79410 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 1586 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 1233673000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 1233073000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000802 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 77824 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.914669 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1873.241202 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.914717 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1873.340733 # Average occupied blocks per context
system.cpu.icache.overall_accesses 97023272 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 19069.814885 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 15852.089330 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 19062.290643 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 15844.379626 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 96943862 # number of overall hits
-system.cpu.icache.overall_miss_latency 1514334000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 1513736500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000818 # miss rate for overall accesses
system.cpu.icache.overall_misses 79410 # number of overall misses
system.cpu.icache.overall_mshr_hits 1586 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 1233673000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 1233073000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000802 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 77824 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements 75778 # number of replacements
system.cpu.icache.sampled_refs 77824 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1873.241202 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1873.340733 # Cycle average of tags in use
system.cpu.icache.total_refs 96943862 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 32286171 # Number of cycles cpu's stages were not processed
-system.cpu.ipc 0.420460 # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total 0.420460 # IPC: Total IPC of All Threads
+system.cpu.idleCycles 31982342 # Number of cycles cpu's stages were not processed
+system.cpu.ipc 0.421067 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total 0.421067 # IPC: Total IPC of All Threads
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52436.396941 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.233323 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 7528713000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 143578 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 5743153500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 143578 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52436.707450 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.226443 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits 54 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 7525926000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.999624 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 143524 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 5740992500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999624 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 143524 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 138590 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52301.497653 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40004.842643 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 95122 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 2273441500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.313645 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 43468 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1738930500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.313645 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 43468 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 6215 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51889.300080 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40002.654867 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 322492000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadReq_avg_miss_latency 52302.271309 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40004.863791 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 95311 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 2263590000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.312281 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 43279 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1731370500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.312281 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 43279 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 3607 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51817.854172 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40002.356529 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 186907000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248616500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 3607 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 144288500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 6215 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_mshr_misses 3607 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 149164 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 149164 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.637249 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.646134 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 282168 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52405.047421 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40001.304492 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 95122 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 9802154500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.662889 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 187046 # number of demand (read+write) misses
+system.cpu.l2cache.demand_avg_miss_latency 52405.560939 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 40001.300836 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 95365 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 9789516000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.662028 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 186803 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 7482084000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.662889 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 187046 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 7472363000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.662028 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 186803 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.083128 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.473986 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 2723.922410 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 15531.583322 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.089575 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.471967 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 2935.193659 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 15465.399858 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 282168 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52405.047421 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40001.304492 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52405.560939 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 40001.300836 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 95122 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 9802154500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.662889 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 187046 # number of overall misses
+system.cpu.l2cache.overall_hits 95365 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 9789516000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.662028 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 186803 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 7482084000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.662889 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 187046 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 7472363000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.662028 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 186803 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 147731 # number of replacements
-system.cpu.l2cache.sampled_refs 172937 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 147725 # number of replacements
+system.cpu.l2cache.sampled_refs 173054 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 18255.505732 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 110204 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 18400.593517 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 111816 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 120636 # number of writebacks
-system.cpu.numCycles 210104718 # number of cpu cycles simulated
-system.cpu.runCycles 177818547 # Number of cycles cpu stages are processed.
+system.cpu.l2cache.writebacks 120606 # number of writebacks
+system.cpu.numCycles 209801984 # number of cpu cycles simulated
+system.cpu.runCycles 177819642 # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
-system.cpu.stage-0.idleCycles 113077434 # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.idleCycles 112774700 # Number of cycles 0 instructions are processed.
system.cpu.stage-0.runCycles 97027284 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-0.utilization 46.180440 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-1.idleCycles 121740642 # Number of cycles 0 instructions are processed.
-system.cpu.stage-1.runCycles 88364076 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-1.utilization 42.057159 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-2.idleCycles 120288932 # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.utilization 46.247076 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-1.idleCycles 121437923 # Number of cycles 0 instructions are processed.
+system.cpu.stage-1.runCycles 88364061 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-1.utilization 42.117839 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-2.idleCycles 119986198 # Number of cycles 0 instructions are processed.
system.cpu.stage-2.runCycles 89815786 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-2.utilization 42.748105 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-3.idleCycles 174873448 # Number of cycles 0 instructions are processed.
+system.cpu.stage-2.utilization 42.809789 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-3.idleCycles 174570714 # Number of cycles 0 instructions are processed.
system.cpu.stage-3.runCycles 35231270 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-3.utilization 16.768434 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-4.idleCycles 121764045 # Number of cycles 0 instructions are processed.
+system.cpu.stage-3.utilization 16.792630 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-4.idleCycles 121461311 # Number of cycles 0 instructions are processed.
system.cpu.stage-4.runCycles 88340673 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-4.utilization 42.046021 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.threadCycles 210104718 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.stage-4.utilization 42.106691 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.threadCycles 209801984 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ----------
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing/simerr
+Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jun 6 2010 03:04:38
-M5 revision ba1a0193c050 7448 default tip
-M5 started Jun 6 2010 03:07:19
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:53:46
M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
+Exiting @ tick 27109454000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 172331 # Simulator instruction rate (inst/s)
-host_mem_usage 216300 # Number of bytes of host memory used
-host_seconds 461.86 # Real time elapsed on the host
-host_tick_rate 58843672 # Simulator tick rate (ticks/s)
+host_inst_rate 111480 # Simulator instruction rate (inst/s)
+host_mem_usage 216720 # Number of bytes of host memory used
+host_seconds 713.95 # Real time elapsed on the host
+host_tick_rate 37970836 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 79591756 # Number of instructions simulated
-sim_seconds 0.027177 # Number of seconds simulated
-sim_ticks 27177245500 # Number of ticks simulated
+sim_seconds 0.027109 # Number of seconds simulated
+sim_ticks 27109454000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 8069483 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 14149168 # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect 34397 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 454823 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 10566027 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 16273288 # Number of BP lookups
-system.cpu.BPredUnit.usedRAS 1942431 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.BTBHits 8023938 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 14145639 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 34256 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 455419 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 10571328 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 16274912 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 1940184 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 13754477 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 3319944 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 3318027 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 51827032 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 1.704529 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 2.326613 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 51708884 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.708423 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 2.329205 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 22597378 43.60% 43.60% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 11350095 21.90% 65.50% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 5102840 9.85% 75.35% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 3559000 6.87% 82.21% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 2567186 4.95% 87.17% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 1515845 2.92% 90.09% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 1002832 1.93% 92.03% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 811912 1.57% 93.59% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 3319944 6.41% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 22519798 43.55% 43.55% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 11308699 21.87% 65.42% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 5100268 9.86% 75.28% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 3555628 6.88% 82.16% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 2564108 4.96% 87.12% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 1506181 2.91% 90.03% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 1020225 1.97% 92.01% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 815950 1.58% 93.58% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 3318027 6.42% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 51827032 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 51708884 # Number of insts commited each cycle
system.cpu.commit.COM:count 88340672 # Number of instructions committed
system.cpu.commit.COM:loads 20379399 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 35224018 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 359545 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 360224 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 8408904 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 8384811 # The number of squashed insts skipped by commit
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
-system.cpu.cpi 0.682916 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.682916 # CPI: Total CPI of All Threads
+system.cpu.cpi 0.681213 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.681213 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 43 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 43 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 20447523 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 30372.255855 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20950.835512 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 20297704 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4550341000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.007327 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 149819 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 88240 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 1290131500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.003012 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 61579 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_accesses 20456575 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 30286.204567 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20855.715214 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 20307098 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4527091000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.007307 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 149477 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 87887 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 1284503500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.003011 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 61590 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 32253.546396 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35751.235092 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 13562946 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 33880124994 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.071881 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1050431 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 900647 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 5354962997 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 149784 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 3083 # average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_avg_miss_latency 32227.418613 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35731.214318 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 13566176 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 33748584999 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.071660 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1047201 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 900041 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 5258205499 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.010070 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 147160 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 165.176300 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked
+system.cpu.dcache.avg_refs 165.209324 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 18498 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 35060900 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 32018.717762 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 31439.251416 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 33860650 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 38430465994 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.034233 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1200250 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 988887 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 6645094497 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.006028 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 211363 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 35069952 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 31984.941646 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 31342.318558 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 33873274 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 38275675999 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.034123 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1196678 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 987928 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 6542708999 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.005952 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 208750 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.995485 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4077.505020 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 35060900 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 32018.717762 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 31439.251416 # average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.995492 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4077.536069 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 35069952 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 31984.941646 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 31342.318558 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 33860650 # number of overall hits
-system.cpu.dcache.overall_miss_latency 38430465994 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.034233 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1200250 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 988887 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 6645094497 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.006028 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 211363 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 33873274 # number of overall hits
+system.cpu.dcache.overall_miss_latency 38275675999 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.034123 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1196678 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 987928 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 6542708999 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.005952 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 208750 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 200975 # number of replacements
-system.cpu.dcache.sampled_refs 205071 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 200988 # number of replacements
+system.cpu.dcache.sampled_refs 205084 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4077.505020 # Cycle average of tags in use
-system.cpu.dcache.total_refs 33872869 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 182118000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 147751 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 3544786 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 96141 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 3662025 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 101883380 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 28549595 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 19586782 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 1306643 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 281833 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 145869 # Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses 36634667 # DTB accesses
-system.cpu.dtb.data_acv 32 # DTB access violations
-system.cpu.dtb.data_hits 36459913 # DTB hits
-system.cpu.dtb.data_misses 174754 # DTB misses
+system.cpu.dcache.tagsinuse 4077.536069 # Cycle average of tags in use
+system.cpu.dcache.total_refs 33881789 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 181403000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 149251 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 3489554 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 96109 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 3659886 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 101890177 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 28536030 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 19538571 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 1305079 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 281240 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 144729 # Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses 36643462 # DTB accesses
+system.cpu.dtb.data_acv 34 # DTB access violations
+system.cpu.dtb.data_hits 36467174 # DTB hits
+system.cpu.dtb.data_misses 176288 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 21560876 # DTB read accesses
-system.cpu.dtb.read_acv 29 # DTB read access violations
-system.cpu.dtb.read_hits 21402283 # DTB read hits
-system.cpu.dtb.read_misses 158593 # DTB read misses
-system.cpu.dtb.write_accesses 15073791 # DTB write accesses
-system.cpu.dtb.write_acv 3 # DTB write access violations
-system.cpu.dtb.write_hits 15057630 # DTB write hits
-system.cpu.dtb.write_misses 16161 # DTB write misses
-system.cpu.fetch.Branches 16273288 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 13390069 # Number of cache lines fetched
-system.cpu.fetch.Cycles 33318554 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 152706 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 103441312 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 571617 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.299392 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 13390069 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 10011914 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.903087 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 53133675 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.946813 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.939021 # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.read_accesses 21569273 # DTB read accesses
+system.cpu.dtb.read_acv 32 # DTB read access violations
+system.cpu.dtb.read_hits 21411172 # DTB read hits
+system.cpu.dtb.read_misses 158101 # DTB read misses
+system.cpu.dtb.write_accesses 15074189 # DTB write accesses
+system.cpu.dtb.write_acv 2 # DTB write access violations
+system.cpu.dtb.write_hits 15056002 # DTB write hits
+system.cpu.dtb.write_misses 18187 # DTB write misses
+system.cpu.fetch.Branches 16274912 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 13386326 # Number of cache lines fetched
+system.cpu.fetch.Cycles 33268098 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 152194 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 103463438 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 573170 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.300170 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 13386326 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 9964122 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.908254 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 53013963 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.951626 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.945013 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 33232285 62.54% 62.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1906283 3.59% 66.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1507954 2.84% 68.97% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 1896878 3.57% 72.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 3940139 7.42% 79.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1882924 3.54% 83.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 690153 1.30% 84.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1104079 2.08% 86.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 6972980 13.12% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 33159204 62.55% 62.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1896528 3.58% 66.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1503537 2.84% 68.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 1853022 3.50% 72.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 3942692 7.44% 79.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1853723 3.50% 83.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 688430 1.30% 84.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1103809 2.08% 86.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 7013018 13.23% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 53133675 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses 13390069 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 9552.030813 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 6056.454886 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 13301016 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 850637000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.006651 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 89053 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 2816 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 522290500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.006440 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 86237 # number of ReadReq MSHR misses
+system.cpu.fetch.rateDist::total 53013963 # Number of instructions fetched each cycle (Total)
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+system.cpu.icache.ReadReq_avg_miss_latency 9552.485505 # average ReadReq miss latency
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+system.cpu.icache.ReadReq_miss_latency 850133000 # number of ReadReq miss cycles
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+system.cpu.icache.ReadReq_mshr_hits 2824 # number of ReadReq MSHR hits
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 154.239714 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 154.313284 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 13390069 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 9552.030813 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 6056.454886 # average overall mshr miss latency
-system.cpu.icache.demand_hits 13301016 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 850637000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.006651 # miss rate for demand accesses
-system.cpu.icache.demand_misses 89053 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 2816 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 522290500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.006440 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 86237 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 13386326 # number of demand (read+write) accesses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.936831 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1918.630870 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 13390069 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 9552.030813 # average overall miss latency
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+system.cpu.icache.occ_%::0 0.936859 # Average percentage of cache occupancy
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 13301016 # number of overall hits
-system.cpu.icache.overall_miss_latency 850637000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.006651 # miss rate for overall accesses
-system.cpu.icache.overall_misses 89053 # number of overall misses
-system.cpu.icache.overall_mshr_hits 2816 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 522290500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.006440 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 86237 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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-system.cpu.icache.sampled_refs 86236 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 84124 # number of replacements
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1918.630870 # Cycle average of tags in use
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
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-system.cpu.iew.EXEC:branches 14763362 # Number of branches executed
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system.cpu.iew.EXEC:swp 0 # number of swp insts executed
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+system.cpu.iew.WB:count 84456261 # cumulative count of insts written-back
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system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 32312963 # num instructions producing a value
-system.cpu.iew.WB:rate 1.553523 # insts written-back per cycle
-system.cpu.iew.WB:sent 84676788 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 400577 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 625766 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 23022182 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 5008 # Number of dispatched non-speculative instructions
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-system.cpu.iew.iewDispStoreInsts 16353481 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 99092373 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 21670628 # Number of load instructions executed
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+system.cpu.iew.WB:sent 84693859 # cumulative count of insts sent to commit
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 9016 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 1306643 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 43564 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 8978 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 1305079 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 42917 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 31 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 953335 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 730 # Number of memory responses ignored because the instruction is squashed
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system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 19282 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 1358 # Number of loads that were rescheduled
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-system.cpu.iew.lsq.thread.0.squashedStores 1508862 # Number of stores squashed
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-system.cpu.iew.predictedNotTakenIncorrect 131988 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 268589 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 1.464309 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.464309 # IPC: Total IPC of All Threads
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+system.cpu.ipc_total 1.467970 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.17% # Type of FU issued
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-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122397 0.14% 56.46% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
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-system.cpu.iq.ISSUE:rate 1.572032 # Inst issue rate
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-system.cpu.iq.iqInstsIssued 85446999 # Number of instructions issued
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-system.cpu.iq.iqSquashedInstsIssued 48902 # Number of squashed instructions issued
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-system.cpu.iq.iqSquashedOperandsExamined 6828439 # Number of squashed operands that are examined and possibly removed from graph
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+system.cpu.iq.ISSUE:rate 1.576455 # Inst issue rate
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+system.cpu.iq.iqSquashedOperandsExamined 6797277 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 13417164 # ITB accesses
+system.cpu.itb.fetch_accesses 13413339 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_hits 13390069 # ITB hits
-system.cpu.itb.fetch_misses 27095 # ITB misses
+system.cpu.itb.fetch_hits 13386326 # ITB hits
+system.cpu.itb.fetch_misses 27013 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 143493 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34335.441443 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31231.837093 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 4926895499 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 143493 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 4481550000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 143493 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 147815 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34139.493240 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31035.309786 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 103139 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 1525216000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.302243 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 44676 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1386533500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.302243 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 44676 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 6336 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34034.485480 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31031.960227 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 215642500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_accesses 143495 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34335.046084 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31231.824393 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_hits 61 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 4924813000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.999575 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 143434 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 4479705500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.999575 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 143434 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 147761 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34138.356934 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31034.221173 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 103271 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 1518815500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.301094 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 44490 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 1380712500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.301094 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 44490 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 3671 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 33969.081994 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31027.649142 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 124700500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 6336 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 196618500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 3671 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 113902500 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 6336 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 147751 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 147751 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2000 # average number of cycles each access was blocked
+system.cpu.l2cache.UpgradeReq_mshr_misses 3671 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 149251 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 149251 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.679657 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
+system.cpu.l2cache.avg_refs 0.688286 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs 2000 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 291308 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34288.918467 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31185.176623 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 103139 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 6452111499 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.645945 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 188169 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 291256 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34288.480982 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31185.042890 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 103332 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 6443628500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.645219 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 187924 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 5868083500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.645945 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 188169 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 5860418000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.645219 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 187924 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.090420 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.474090 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 2962.888778 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 15534.990261 # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses 291308 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34288.918467 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31185.176623 # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0 0.096999 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.471977 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 3178.468873 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 15465.728229 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 291256 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34288.480982 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31185.042890 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 103139 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 6452111499 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.645945 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 188169 # number of overall misses
+system.cpu.l2cache.overall_hits 103332 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 6443628500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.645219 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 187924 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 5868083500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.645945 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 188169 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 5860418000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.645219 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 187924 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 148882 # number of replacements
-system.cpu.l2cache.sampled_refs 174101 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 148884 # number of replacements
+system.cpu.l2cache.sampled_refs 174227 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 18497.879039 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 118329 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 18644.197102 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 119918 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 120652 # number of writebacks
-system.cpu.memDep0.conflictingLoads 12671277 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 11281308 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 23022182 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 16353481 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 54354492 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 2040280 # Number of cycles rename is blocking
+system.cpu.l2cache.writebacks 120621 # number of writebacks
+system.cpu.memDep0.conflictingLoads 12607383 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 11255649 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 23014883 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 16347988 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 54218909 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 2001211 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 60824 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 28947603 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 1285549 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 34 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 121774399 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 101069730 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 60794101 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 19336245 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 1306643 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 1420628 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 8247220 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 82276 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 5281 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 2797354 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 5278 # count of temporary serializing insts renamed
-system.cpu.timesIdled 42409 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IQFullEvents 58273 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 28932787 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 1273359 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 32 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 121782078 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 101070010 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 60804975 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 19289152 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 1305079 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 1405067 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 8258094 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 80667 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 5283 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 2766751 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 5281 # count of temporary serializing insts renamed
+system.cpu.timesIdled 41950 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
---------- End Simulation Statistics ----------
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
+Redirecting stdout to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Feb 24 2010 23:12:40
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 02:21:01
-M5 executing on SC2B0619
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:57:42
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
+Exiting @ tick 135015129000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 1182325 # Simulator instruction rate (inst/s)
-host_mem_usage 200332 # Number of bytes of host memory used
-host_seconds 74.72 # Real time elapsed on the host
-host_tick_rate 1809050434 # Simulator tick rate (ticks/s)
+host_inst_rate 1159310 # Simulator instruction rate (inst/s)
+host_mem_usage 215356 # Number of bytes of host memory used
+host_seconds 76.20 # Real time elapsed on the host
+host_tick_rate 1771821789 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 88340673 # Number of instructions simulated
-sim_seconds 0.135169 # Number of seconds simulated
-sim_ticks 135168766000 # Number of ticks simulated
+sim_seconds 0.135015 # Number of seconds simulated
+sim_ticks 135015129000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 37874.600928 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34874.600928 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 37754.336306 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34754.336306 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2301488000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 2294180000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 2119190000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 2111882000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.752992 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.752992 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 14463584 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 8388371000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.010250 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 149793 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 7938992000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.010250 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 149793 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 55984.400584 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52984.400584 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 14466192 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 8240064000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.010072 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 147185 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 7798509000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.010072 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 147185 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 50768.948371 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 47768.948371 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 34679456 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 10689859000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.006035 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 210559 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 50657.337546 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dtb.data_accesses 34987415 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 34890015 # DTB hits
system.cpu.dtb.write_hits 14613377 # DTB write hits
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system.cpu.icache.ReadReq_accesses 88438074 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 18810.691297 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15810.691297 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_mshr_miss_rate 0.000864 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_miss_rate 0.000864 # mshr miss rate for demand accesses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.overall_mshr_miss_rate 0.000864 # mshr miss rate for overall accesses
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system.cpu.icache.replacements 74391 # number of replacements
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1871.768668 # Cycle average of tags in use
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 6215 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 248600000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
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-system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 147714 # number of Writeback hits
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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-system.cpu.l2cache.demand_mshr_misses 186875 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 93905 # number of overall hits
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 147561 # number of replacements
-system.cpu.l2cache.sampled_refs 172766 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 147555 # number of replacements
+system.cpu.l2cache.sampled_refs 172883 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 18255.825674 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 108986 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 18402.705343 # Cycle average of tags in use
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 120634 # number of writebacks
+system.cpu.l2cache.writebacks 120604 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 270337532 # number of cpu cycles simulated
+system.cpu.numCycles 270030258 # number of cpu cycles simulated
system.cpu.num_insts 88340673 # Number of instructions executed
system.cpu.num_refs 35321418 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
egid=100
env=
errout=cerr
+Redirecting stdout to build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Aug 24 2010 15:34:40
-M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
-M5 started Aug 24 2010 15:39:36
+M5 compiled Aug 26 2010 13:52:30
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:53:04
M5 executing on zizzer
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 133556162000 because target called exit()
+Exiting @ tick 133464153000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 1745846 # Simulator instruction rate (inst/s)
-host_mem_usage 217668 # Number of bytes of host memory used
-host_seconds 56.13 # Real time elapsed on the host
-host_tick_rate 2379327214 # Simulator tick rate (ticks/s)
+host_inst_rate 1245224 # Simulator instruction rate (inst/s)
+host_mem_usage 218772 # Number of bytes of host memory used
+host_seconds 78.70 # Real time elapsed on the host
+host_tick_rate 1695886374 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 97997303 # Number of instructions simulated
-sim_seconds 0.133556 # Number of seconds simulated
-sim_ticks 133556162000 # Number of ticks simulated
+sim_seconds 0.133464 # Number of seconds simulated
+sim_ticks 133464153000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 27164439 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 35927.990796 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32927.990796 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 35865.411818 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32865.411818 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 27111418 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 1904938000 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_rate 0.001952 # miss rate for ReadReq accesses
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[system.cpu.workload]
type=LiveProcess
cmd=vortex bendian.raw
-cwd=build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
+cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/vortex
+executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Feb 25 2010 03:11:27
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:34:57
-M5 executing on SC2B0619
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/50.vortex/sparc/linux/simple-timing
+M5 compiled Aug 26 2010 13:03:41
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:06:02
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
-Exiting @ tick 203376692000 because target called exit()
+Exiting @ tick 203281649000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 755710 # Simulator instruction rate (inst/s)
-host_mem_usage 202292 # Number of bytes of host memory used
-host_seconds 180.15 # Real time elapsed on the host
-host_tick_rate 1128944281 # Simulator tick rate (ticks/s)
+host_inst_rate 1039608 # Simulator instruction rate (inst/s)
+host_mem_usage 220432 # Number of bytes of host memory used
+host_seconds 130.95 # Real time elapsed on the host
+host_tick_rate 1552328099 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 136139203 # Number of instructions simulated
-sim_seconds 0.203377 # Number of seconds simulated
-sim_ticks 203376692000 # Number of ticks simulated
+sim_seconds 0.203282 # Number of seconds simulated
+sim_ticks 203281649000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 37231301 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 38620.848810 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35620.848810 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 38539.616255 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35539.616255 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 37185802 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 1757210000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 1753514000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.001222 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 45499 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 1620713000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 1617017000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.001222 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 45499 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 15916 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_hits 15876 # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency 2240000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_rate 0.002513 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_misses 40 # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency 2120000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_rate 0.002513 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_misses 40 # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_hits 15879 # number of SwapReq hits
+system.cpu.dcache.SwapReq_miss_latency 2072000 # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_rate 0.002325 # miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_misses 37 # number of SwapReq misses
+system.cpu.dcache.SwapReq_mshr_miss_latency 1961000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_rate 0.002325 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.SwapReq_mshr_misses 37 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 20864304 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.835474 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.835474 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 20754899 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 6126662000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.005244 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 109405 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 5798447000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.005244 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 109405 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 55967.131927 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52967.131927 # average WriteReq mshr miss latency
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 384.666925 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 58095605 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 50895.212519 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 57940701 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 7883872000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.002666 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 154904 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 50795.504944 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 47795.504944 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 57942281 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 7788170000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.002639 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 153324 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 7419160000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.002666 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 154904 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 7328198000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.002639 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 153324 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.997952 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4087.609698 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.997956 # Average percentage of cache occupancy
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system.cpu.dcache.overall_accesses 58095605 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 50895.212519 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 47895.212519 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 50795.504944 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 47795.504944 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 57940701 # number of overall hits
-system.cpu.dcache.overall_miss_latency 7883872000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.002666 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 154904 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 7419160000 # number of overall MSHR miss cycles
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-system.cpu.dcache.overall_mshr_misses 154904 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 146582 # number of replacements
system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4087.609698 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4087.629454 # Cycle average of tags in use
system.cpu.dcache.total_refs 57960843 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 778280000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 107279 # number of writebacks
+system.cpu.dcache.warmup_cycle 776960000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 108328 # number of writebacks
system.cpu.icache.ReadReq_accesses 134553584 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 16936.029600 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 13936.029600 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 16931.987339 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 13931.987339 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 134366560 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 3167444000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_rate 0.001390 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 2606372000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate 0.001390 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 134553584 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 16936.029600 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency
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+system.cpu.icache.demand_avg_mshr_miss_latency 13931.987339 # average overall mshr miss latency
system.cpu.icache.demand_hits 134366560 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 3167444000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_rate 0.001390 # miss rate for demand accesses
system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 2606372000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_rate 0.001390 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.978865 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 2004.715107 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.978873 # Average percentage of cache occupancy
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system.cpu.icache.overall_accesses 134553584 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 16936.029600 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 13936.029600 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 16931.987339 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 13931.987339 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 134366560 # number of overall hits
-system.cpu.icache.overall_miss_latency 3167444000 # number of overall miss cycles
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system.cpu.icache.overall_miss_rate 0.001390 # miss rate for overall accesses
system.cpu.icache.overall_misses 187024 # number of overall misses
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-system.cpu.icache.overall_mshr_miss_latency 2606372000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_rate 0.001390 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements 184976 # number of replacements
system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 2004.715107 # Cycle average of tags in use
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system.cpu.icache.total_refs 134366560 # Total number of references to valid blocks.
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system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.idle_fraction 0 # Percentage of idle cycles
system.cpu.l2cache.ReadExReq_accesses 105179 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
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system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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+system.cpu.l2cache.demand_miss_latency 7526220000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.428588 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 144735 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 5797000000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.429151 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 144925 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 5789400000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.428588 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 144735 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.120206 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.469380 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 3938.922202 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 15380.640176 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.127128 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.467489 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 4165.731733 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 15318.691405 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 337702 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 192777 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 7536100000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.429151 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 144925 # number of overall misses
+system.cpu.l2cache.overall_hits 192967 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 7526220000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.428588 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 144735 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 5797000000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.429151 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 144925 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 5789400000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.428588 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 144735 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 120487 # number of replacements
-system.cpu.l2cache.sampled_refs 139197 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 120481 # number of replacements
+system.cpu.l2cache.sampled_refs 139283 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 19319.562378 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 199591 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 19484.423138 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 200725 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 87414 # number of writebacks
+system.cpu.l2cache.writebacks 87388 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 406753384 # number of cpu cycles simulated
+system.cpu.numCycles 406563298 # number of cpu cycles simulated
system.cpu.num_insts 136139203 # Number of instructions executed
system.cpu.num_refs 58160249 # Number of memory references
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing/simerr
+Redirecting stdout to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jun 6 2010 03:04:38
-M5 revision ba1a0193c050 7448 default tip
-M5 started Jun 6 2010 03:30:51
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 12:05:40
M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
+Exiting @ tick 732922365000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 192033 # Simulator instruction rate (inst/s)
-host_mem_usage 206980 # Number of bytes of host memory used
-host_seconds 9040.35 # Real time elapsed on the host
-host_tick_rate 81902195 # Simulator tick rate (ticks/s)
+host_inst_rate 115207 # Simulator instruction rate (inst/s)
+host_mem_usage 207548 # Number of bytes of host memory used
+host_seconds 15068.91 # Real time elapsed on the host
+host_tick_rate 48638035 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1736043781 # Number of instructions simulated
-sim_seconds 0.740425 # Number of seconds simulated
-sim_ticks 740424887500 # Number of ticks simulated
+sim_seconds 0.732922 # Number of seconds simulated
+sim_ticks 732922365000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 300304269 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 307023866 # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect 161 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 19915568 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 268271856 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 347819261 # Number of BP lookups
-system.cpu.BPredUnit.usedRAS 23893430 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.BTBHits 297651815 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 304473054 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 146 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 19905340 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 266187209 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 345286425 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 23890708 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 214632552 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 63188477 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 63402454 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 1374695730 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 1.323769 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 2.099460 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 1362326064 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.335789 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 2.108307 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 733755921 53.38% 53.38% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 260590847 18.96% 72.33% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 127148586 9.25% 81.58% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 73808717 5.37% 86.95% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 48837558 3.55% 90.50% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 32392808 2.36% 92.86% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 24165844 1.76% 94.62% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 10806972 0.79% 95.40% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 63188477 4.60% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 722221726 53.01% 53.01% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 260663635 19.13% 72.15% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 126275090 9.27% 81.42% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 73614843 5.40% 86.82% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 49214339 3.61% 90.43% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 31342415 2.30% 92.73% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 24208215 1.78% 94.51% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 11383347 0.84% 95.35% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 63402454 4.65% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 1374695730 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 1362326064 # Number of insts commited each cycle
system.cpu.commit.COM:count 1819780126 # Number of instructions committed
system.cpu.commit.COM:loads 445666361 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 606571343 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 19915049 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 19904825 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 631770816 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 616386841 # The number of squashed insts skipped by commit
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
-system.cpu.cpi 0.853003 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.853003 # CPI: Total CPI of All Threads
+system.cpu.cpi 0.844359 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.844359 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses 523747084 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 16905.655994 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11269.981612 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 513424902 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 174503258000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.019708 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 10322182 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 3045892 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 82003654500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.013893 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 7276290 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_accesses 521630579 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 16446.832647 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11014.947389 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 511650921 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 164133765000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.019132 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 9979658 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 2703270 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 80149031000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.013949 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses 7276388 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 33742.228480 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37153.275529 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 155297365 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 183258665559 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.033791 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 5431137 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 3182597 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 83540626157 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.013990 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 2248540 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 6330.872599 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 30366.853399 # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 73.096818 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 156412 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 65334 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 990224445 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 1983988000 # number of cycles access was blocked
+system.cpu.dcache.WriteReq_avg_miss_latency 32545.971387 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34322.334946 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 155766779 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 161484094789 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.030870 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 4961723 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 2963011 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 68600462724 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.012435 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1998712 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 5974.555782 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets 30410.724976 # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs 72.882698 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 121015 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 65147 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 723010868 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 1981167500 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 684475586 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 22710.257030 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 17380.287171 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 668722267 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 357761923559 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.023015 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 15753319 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 6228489 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 165544280657 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.013916 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 9524830 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 682359081 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 21793.023000 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 16037.508353 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 667417700 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 325617859789 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.021897 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 14941381 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 5666281 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 148749493724 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.013593 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 9275100 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.997494 # Average percentage of cache occupancy
-system.cpu.dcache.occ_%::1 -0.003143 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4085.737319 # Average occupied blocks per context
-system.cpu.dcache.occ_blocks::1 -12.874688 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 684475586 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 22710.257030 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 17380.287171 # average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.997469 # Average percentage of cache occupancy
+system.cpu.dcache.occ_%::1 -0.002947 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4085.632664 # Average occupied blocks per context
+system.cpu.dcache.occ_blocks::1 -12.069593 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 682359081 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 21793.023000 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 16037.508353 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 668722267 # number of overall hits
-system.cpu.dcache.overall_miss_latency 357761923559 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.023015 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 15753319 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 6228489 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 165544280657 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.013916 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 9524830 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 667417700 # number of overall hits
+system.cpu.dcache.overall_miss_latency 325617859789 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.021897 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 14941381 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 5666281 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 148749493724 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.013593 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 9275100 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 9156903 # number of replacements
-system.cpu.dcache.sampled_refs 9160999 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 9156983 # number of replacements
+system.cpu.dcache.sampled_refs 9161079 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4079.299976 # Cycle average of tags in use
-system.cpu.dcache.total_refs 669639874 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 7084220000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 2245460 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 97965081 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 741 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 54990106 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 2817972216 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 726420898 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 545630418 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 93906879 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 1735 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 4679333 # Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses 771953785 # DTB accesses
+system.cpu.dcache.tagsinuse 4079.597867 # Cycle average of tags in use
+system.cpu.dcache.total_refs 667684156 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 7084801000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 2367711 # number of writebacks
+system.cpu.decode.DECODE:BlockedCycles 93349702 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 598 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 54504022 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 2803113220 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 722066213 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 542175542 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 91814713 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 1721 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 4734607 # Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses 769403639 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_hits 755880744 # DTB hits
-system.cpu.dtb.data_misses 16073041 # DTB misses
+system.cpu.dtb.data_hits 753449541 # DTB hits
+system.cpu.dtb.data_misses 15954098 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 569575118 # DTB read accesses
+system.cpu.dtb.read_accesses 567301584 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 560292416 # DTB read hits
-system.cpu.dtb.read_misses 9282702 # DTB read misses
-system.cpu.dtb.write_accesses 202378667 # DTB write accesses
+system.cpu.dtb.read_hits 558063709 # DTB read hits
+system.cpu.dtb.read_misses 9237875 # DTB read misses
+system.cpu.dtb.write_accesses 202102055 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 195588328 # DTB write hits
-system.cpu.dtb.write_misses 6790339 # DTB write misses
-system.cpu.fetch.Branches 347819261 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 356032734 # Number of cache lines fetched
-system.cpu.fetch.Cycles 917156426 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 8668632 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 2872343822 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 28362919 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.234878 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 356032734 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 324197699 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.939659 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 1468602609 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.955835 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.862588 # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.write_hits 195385832 # DTB write hits
+system.cpu.dtb.write_misses 6716223 # DTB write misses
+system.cpu.fetch.Branches 345286425 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 353801341 # Number of cache lines fetched
+system.cpu.fetch.Cycles 911477048 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 8513687 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 2856997588 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 28043242 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.235555 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 353801341 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 321542523 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.949045 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 1454140777 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.964732 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.867668 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 907478951 61.79% 61.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 48285594 3.29% 65.08% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 31293098 2.13% 67.21% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 51463172 3.50% 70.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 124103039 8.45% 79.17% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 68291233 4.65% 83.82% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 47448055 3.23% 87.05% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 37389871 2.55% 89.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 152849596 10.41% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 896465106 61.65% 61.65% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 48268270 3.32% 64.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 30594278 2.10% 67.07% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 50900501 3.50% 70.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 123419810 8.49% 79.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 68033881 4.68% 83.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 46960603 3.23% 86.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 36759628 2.53% 89.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 152738700 10.50% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1468602609 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses 356032734 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 35280.127694 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35449.450549 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 356031481 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 44206000 # number of ReadReq miss cycles
+system.cpu.fetch.rateDist::total 1454140777 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 353801341 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 35355.537721 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35450.495050 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 353800095 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 44053000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 1253 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 343 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 32259000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_misses 1246 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 337 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 32224500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 910 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses 909 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 391243.385714 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 389219.026403 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 356032734 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 35280.127694 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35449.450549 # average overall mshr miss latency
-system.cpu.icache.demand_hits 356031481 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 44206000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_accesses 353801341 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 35355.537721 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35450.495050 # average overall mshr miss latency
+system.cpu.icache.demand_hits 353800095 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 44053000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
-system.cpu.icache.demand_misses 1253 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 343 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 32259000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_misses 1246 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 32224500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 910 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses 909 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.349473 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 715.720591 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 356032734 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 35280.127694 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35449.450549 # average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.349132 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 715.022199 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 353801341 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 35355.537721 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35450.495050 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 356031481 # number of overall hits
-system.cpu.icache.overall_miss_latency 44206000 # number of overall miss cycles
+system.cpu.icache.overall_hits 353800095 # number of overall hits
+system.cpu.icache.overall_miss_latency 44053000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
-system.cpu.icache.overall_misses 1253 # number of overall misses
-system.cpu.icache.overall_mshr_hits 343 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 32259000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_misses 1246 # number of overall misses
+system.cpu.icache.overall_mshr_hits 337 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 32224500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 910 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses 909 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 1 # number of replacements
-system.cpu.icache.sampled_refs 910 # Sample count of references to valid blocks.
+system.cpu.icache.sampled_refs 909 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 715.720591 # Cycle average of tags in use
-system.cpu.icache.total_refs 356031481 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 715.022199 # Cycle average of tags in use
+system.cpu.icache.total_refs 353800095 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 12247167 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 283205490 # Number of branches executed
-system.cpu.iew.EXEC:nop 130221162 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.544186 # Inst execution rate
-system.cpu.iew.EXEC:refs 773252228 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 202589844 # Number of stores executed
+system.cpu.idleCycles 11703954 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 281582966 # Number of branches executed
+system.cpu.iew.EXEC:nop 129524501 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.553744 # Inst execution rate
+system.cpu.iew.EXEC:refs 770699454 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 202312987 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 1537746587 # num instructions consuming a value
-system.cpu.iew.WB:count 2247853705 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.811174 # average fanout of values written-back
+system.cpu.iew.WB:consumers 1532271545 # num instructions consuming a value
+system.cpu.iew.WB:count 2239351820 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.811403 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 1247380184 # num instructions producing a value
-system.cpu.iew.WB:rate 1.517949 # insts written-back per cycle
-system.cpu.iew.WB:sent 2269524166 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 21734619 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 17681894 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 621844790 # Number of dispatched load instructions
+system.cpu.iew.WB:producers 1243290213 # num instructions producing a value
+system.cpu.iew.WB:rate 1.527687 # insts written-back per cycle
+system.cpu.iew.WB:sent 2260914368 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 21706879 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 16198055 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 619677157 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 21649497 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 234635839 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 2626124753 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 570662384 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 37709808 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 2286707552 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 438059 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewDispSquashedInsts 21613314 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 233108974 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 2613111960 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 568386467 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 37669869 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 2277546807 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 471616 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 36964 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 93906879 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 800629 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 28495 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 91814713 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 777432 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 361620 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 36313428 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 213767 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked 285764 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 36261369 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 212351 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 2870017 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 18 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 176178429 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 73730857 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 2870017 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 3392458 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 18342161 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 1.172329 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.172329 # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation 2343036 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 14 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 174010796 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 72203992 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 2343036 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 3386842 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 18320037 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 1.184330 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.184330 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu 1537413633 66.14% 66.14% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult 96 0.00% 66.14% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.14% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 239 0.00% 66.14% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp 20 0.00% 66.14% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 141 0.00% 66.14% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 17 0.00% 66.14% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% 66.14% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.14% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 581325773 25.01% 91.15% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 205677417 8.85% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 1530874605 66.12% 66.12% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::FloatMult 16 0.00% 66.12% # Type of FU issued
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+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.12% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 578961528 25.01% 91.13% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 205380015 8.87% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 2324417360 # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt 13099894 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.005636 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 2315216676 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 13456867 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.005812 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 2747666 20.97% 20.97% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 20.97% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 20.97% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 20.97% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 20.97% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 20.97% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 20.97% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 20.97% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 20.97% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 8624380 65.84% 86.81% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite 1727848 13.19% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 2756939 20.49% 20.49% # attempts to use FU when none available
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+system.cpu.iq.ISSUE:fu_full::MemRead 8882759 66.01% 86.50% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 577211692 39.30% 39.30% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 268561729 18.29% 57.59% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 245516096 16.72% 74.31% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 137351239 9.35% 83.66% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 112900190 7.69% 91.35% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 73000831 4.97% 96.32% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 43951863 2.99% 99.31% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 8418123 0.57% 99.88% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8 1690846 0.12% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 566783737 38.98% 38.98% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 267408405 18.39% 57.37% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 245316156 16.87% 74.24% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 135509048 9.32% 83.56% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 112013237 7.70% 91.26% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 72675996 5.00% 96.26% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 44106984 3.03% 99.29% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 8043729 0.55% 99.84% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 2283485 0.16% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 1468602609 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 1.569651 # Inst issue rate
-system.cpu.iq.iqInstsAdded 2495903546 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 2324417360 # Number of instructions issued
+system.cpu.iq.ISSUE:issued_per_cycle::total 1454140777 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 1.579442 # Inst issue rate
+system.cpu.iq.iqInstsAdded 2483587414 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 2315216676 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 740504039 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 1264443 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 728311196 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 1117432 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 323242086 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 316872766 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 356032768 # ITB accesses
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system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_hits 356032734 # ITB hits
-system.cpu.itb.fetch_misses 34 # ITB misses
+system.cpu.itb.fetch_hits 353801341 # ITB hits
+system.cpu.itb.fetch_misses 36 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 1884709 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34610.194422 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31460.521684 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 65230144918 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 1884709 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 59293928362 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 1884709 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 7277200 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34313.246356 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31139.092194 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 5388273 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 64815217500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.259568 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 1888927 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 58819472000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259568 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 1888927 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 363845 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34326.565768 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31260.856148 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 12489549322 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_accesses 1884690 # number of ReadExReq accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_mshr_miss_latency 57292691000 # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadReq_mshr_misses 1840014 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 114023 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34289.699008 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31224.543680 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 3909814350 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 363845 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 11374106205 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 114023 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 363845 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 2245460 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 2245460 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 11887.575431 # average number of cycles each access was blocked
+system.cpu.l2cache.UpgradeReq_mshr_misses 114023 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 2367711 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 2367711 # number of Writeback hits
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs 11849.162556 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 2.418021 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 39831 # number of cycles access was blocked
+system.cpu.l2cache.avg_refs 2.526283 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 27449 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs 473494017 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 325247663 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 9161909 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34461.554431 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31299.627299 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 5388273 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 130045362418 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.411883 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 3773636 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 9161988 # number of demand (read+write) accesses
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+system.cpu.l2cache.demand_hits 5612191 # number of demand (read+write) hits
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 118113400362 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.411883 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 3773636 # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.demand_mshr_miss_rate 0.387448 # mshr miss rate for demand accesses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.452605 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.337458 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 14830.970465 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 11057.808672 # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses 9161909 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34461.554431 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31299.627299 # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0 0.481343 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.322273 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 15772.655639 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 10560.226030 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 9161988 # number of overall (read+write) accesses
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 5388273 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 130045362418 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.411883 # miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 118113400362 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.411883 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 3773636 # number of overall MSHR misses
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+system.cpu.l2cache.overall_mshr_misses 3549797 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 2759709 # number of replacements
-system.cpu.l2cache.sampled_refs 2784305 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 2708907 # number of replacements
+system.cpu.l2cache.sampled_refs 2733538 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 25888.779137 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 6732509 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 154525864500 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 1195751 # number of writebacks
-system.cpu.memDep0.conflictingLoads 123998073 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 64478030 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 621844790 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 234635839 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 1480849776 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 67789415 # Number of cycles rename is blocking
+system.cpu.l2cache.tagsinuse 26332.881669 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 6905691 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 152081139500 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 1176798 # number of writebacks
+system.cpu.memDep0.conflictingLoads 124506463 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 62743482 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 619677157 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 233108974 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 1465844731 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 63989148 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 5483545 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 745501679 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 20525033 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:ROBFullEvents 1073372 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 3564600090 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 2755431831 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 2063008571 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 531263306 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 93906879 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 30140307 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 686805608 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 1023 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:IQFullEvents 5522165 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 740664434 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 19930963 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:ROBFullEvents 1000685 # Number of times rename has blocked due to ROB full
+system.cpu.rename.RENAME:RenameLookups 3545348406 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 2741098331 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 2053584906 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 528288951 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 91814713 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 29382701 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 677381943 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 830 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 61497352 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts 59537135 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 46 # count of temporary serializing insts renamed
-system.cpu.timesIdled 461191 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.timesIdled 436319 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
---------- End Simulation Statistics ----------
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/bzip2
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
+Redirecting stdout to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Feb 24 2010 23:12:40
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 02:20:02
-M5 executing on SC2B0619
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 12:06:37
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
+Exiting @ tick 2705279137000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 1190978 # Simulator instruction rate (inst/s)
-host_mem_usage 191664 # Number of bytes of host memory used
-host_seconds 1527.97 # Real time elapsed on the host
-host_tick_rate 1785366772 # Simulator tick rate (ticks/s)
+host_inst_rate 1235575 # Simulator instruction rate (inst/s)
+host_mem_usage 206704 # Number of bytes of host memory used
+host_seconds 1472.82 # Real time elapsed on the host
+host_tick_rate 1836801554 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1819780127 # Number of instructions simulated
-sim_seconds 2.727991 # Number of seconds simulated
-sim_ticks 2727990505000 # Number of ticks simulated
+sim_seconds 2.705279 # Number of seconds simulated
+sim_ticks 2705279137000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 24899.898843 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21899.898843 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 24619.494258 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21619.494258 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 437373249 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 179837378000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 177812180000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.016245 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 7222414 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 158170136000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 156144938000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.842958 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.842958 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 158480700 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 125876559000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.013985 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 2247802 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 119133153000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.013985 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 2247802 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 52453.824926 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49453.824926 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 158727823 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 104943266000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.012448 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 2000679 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 98941229000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.012448 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 2000679 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 605324165 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 32281.622404 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 595853949 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 305713937000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.015645 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 9470216 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 30657.334367 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 27657.334367 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 596101072 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 282755446000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.015237 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 9223093 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 277303289000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.015645 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 9470216 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 255086167000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.015237 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 9223093 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.996068 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4079.892573 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.996035 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 4079.758997 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 605324165 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 32281.622404 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 29281.622404 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 30657.334367 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 27657.334367 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 595853949 # number of overall hits
-system.cpu.dcache.overall_miss_latency 305713937000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.015645 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 9470216 # number of overall misses
+system.cpu.dcache.overall_hits 596101072 # number of overall hits
+system.cpu.dcache.overall_miss_latency 282755446000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.015237 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 9223093 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 277303289000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.015645 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 9470216 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 255086167000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.015237 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 9223093 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 9107638 # number of replacements
system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4079.892573 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4079.758997 # Cycle average of tags in use
system.cpu.dcache.total_refs 596212431 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 40991470000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 2244708 # number of writebacks
+system.cpu.dcache.warmup_cycle 40990273000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 2365949 # number of writebacks
system.cpu.dtb.data_accesses 611922547 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_hits 605324165 # DTB hits
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.298700 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 611.737435 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.298761 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 611.862910 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 611.737435 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 611.862910 # Cycle average of tags in use
system.cpu.icache.total_refs 1826377708 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadExReq_accesses 1889320 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 98244640000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 1889320 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 75572800000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 1889320 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_hits 168921 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_miss_latency 89460748000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_rate 0.910592 # miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_misses 1720399 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 68815960000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.910592 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_misses 1720399 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 7223216 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 5348043 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 97508996000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.259604 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 1875173 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 75006920000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259604 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 1875173 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 358482 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51948.795198 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadReq_hits 5396262 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 95001608000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.252928 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 1826954 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 73078160000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.252928 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 1826954 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 111359 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51964.511176 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 18622708000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 5786716000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 358482 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 14339280000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 111359 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4454360000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 358482 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 2244708 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 2244708 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_mshr_misses 111359 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.Writeback_accesses 2365949 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits 2365949 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 2.407812 # Average number of references to valid blocks.
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 9112536 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 5348043 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 195753636000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.413111 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 3764493 # number of demand (read+write) misses
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system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 150579720000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.413111 # mshr miss rate for demand accesses
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+system.cpu.l2cache.demand_mshr_miss_rate 0.389283 # mshr miss rate for demand accesses
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.438454 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.335641 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 14367.257286 # Average occupied blocks per context
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+system.cpu.l2cache.occ_blocks::1 10513.160578 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 9112536 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 5348043 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 195753636000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.413111 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 3764493 # number of overall misses
+system.cpu.l2cache.overall_hits 5565183 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 184462356000 # number of overall miss cycles
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 150579720000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.413111 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 3764493 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 141894120000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.389283 # mshr miss rate for overall accesses
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system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 2751986 # number of replacements
-system.cpu.l2cache.sampled_refs 2776586 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 2701645 # number of replacements
+system.cpu.l2cache.sampled_refs 2726277 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 25365.544087 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 6685498 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 605789077000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 1194738 # number of writebacks
+system.cpu.l2cache.tagsinuse 25804.313731 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 6857112 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 596452524000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 1175830 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 5455981010 # number of cpu cycles simulated
+system.cpu.numCycles 5410558274 # number of cpu cycles simulated
system.cpu.num_insts 1819780127 # Number of instructions executed
system.cpu.num_refs 613169725 # Number of memory references
system.cpu.workload.PROG:num_syscalls 29 # Number of system calls
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
egid=100
env=
errout=cerr
+Redirecting stdout to build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Aug 24 2010 15:34:40
-M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
-M5 started Aug 24 2010 15:41:22
+M5 compiled Aug 26 2010 13:52:30
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 14:05:19
M5 executing on zizzer
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 2495902189000 because target called exit()
+Exiting @ tick 2473217439000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 1693548 # Simulator instruction rate (inst/s)
-host_mem_usage 210380 # Number of bytes of host memory used
-host_seconds 1005.94 # Real time elapsed on the host
-host_tick_rate 2481166849 # Simulator tick rate (ticks/s)
+host_inst_rate 1470110 # Simulator instruction rate (inst/s)
+host_mem_usage 211484 # Number of bytes of host memory used
+host_seconds 1158.83 # Real time elapsed on the host
+host_tick_rate 2134239180 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 1703605163 # Number of instructions simulated
-sim_seconds 2.495902 # Number of seconds simulated
-sim_ticks 2495902189000 # Number of ticks simulated
+sim_seconds 2.473217 # Number of seconds simulated
+sim_ticks 2473217439000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 482384248 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 24911.078403 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21911.078403 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 24630.043664 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21630.043664 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 475158152 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 180009844000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 177979060000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.014980 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 7226096 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 158331556000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 156300772000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.014980 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 7226096 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 172586108 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.839740 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.839740 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 170339765 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 125794848000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.013016 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 2246343 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 119055819000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.013016 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 2246343 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 52467.599202 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49467.599202 # average WriteReq mshr miss latency
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 70.854389 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 654970356 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 32283.627480 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 29283.627480 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 645497917 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 305804692000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.014462 # miss rate for demand accesses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.997080 # Average percentage of cache occupancy
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system.cpu.dcache.overall_accesses 654970356 # number of overall (read+write) accesses
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-system.cpu.dcache.overall_avg_mshr_miss_latency 29283.627480 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 645497917 # number of overall hits
-system.cpu.dcache.overall_miss_latency 305804692000 # number of overall miss cycles
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-system.cpu.dcache.overall_misses 9472439 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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-system.cpu.dcache.overall_mshr_misses 9472439 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 9111149 # number of replacements
system.cpu.dcache.sampled_refs 9115245 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4084.040360 # Cycle average of tags in use
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system.cpu.dcache.total_refs 645855111 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 25923946000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 2243257 # number of writebacks
+system.cpu.dcache.warmup_cycle 25923011000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 2365751 # number of writebacks
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.251129 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 514.312841 # Average occupied blocks per context
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system.cpu.icache.overall_accesses 1544565415 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 54551.724138 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 51551.724138 # average overall mshr miss latency
system.cpu.icache.replacements 7 # number of replacements
system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 514.312841 # Cycle average of tags in use
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system.cpu.icache.total_refs 1544564777 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadExReq_accesses 1889149 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 98235748000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 1889149 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 75565960000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 1889149 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 7226734 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 5348868 # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_misses 1877866 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 75114640000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.259850 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 1877866 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 357194 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51947.591505 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadReq_hits 5397220 # number of ReadReq hits
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+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51957.950591 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 18555368000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 357194 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 357194 # number of UpgradeReq MSHR misses
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-system.cpu.l2cache.Writeback_hits 2243257 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_mshr_misses 110061 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 150680600000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.413236 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 3767015 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 142020880000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.389487 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 3550522 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 2752487 # number of replacements
-system.cpu.l2cache.sampled_refs 2779653 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 2702712 # number of replacements
+system.cpu.l2cache.sampled_refs 2729930 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 25386.387650 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 6685114 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 562275129000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 1196151 # number of writebacks
+system.cpu.l2cache.tagsinuse 25889.601414 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 6857391 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 555158623000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 1177576 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 4991804378 # number of cpu cycles simulated
+system.cpu.numCycles 4946434878 # number of cpu cycles simulated
system.cpu.num_insts 1703605163 # Number of instructions executed
system.cpu.num_refs 660773876 # Number of memory references
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing
+cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
egid=100
env=
errout=cerr
+Redirecting stdout to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled May 2 2010 23:23:01
-M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
-M5 started May 2 2010 23:23:02
-M5 executing on burrito
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/60.bzip2/x86/linux/simple-timing
+M5 compiled Aug 26 2010 13:20:12
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:20:23
+M5 executing on zizzer
+command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 5988071419000 because target called exit()
+Exiting @ tick 5965358694000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 1729585 # Simulator instruction rate (inst/s)
-host_mem_usage 225072 # Number of bytes of host memory used
-host_seconds 2690.43 # Real time elapsed on the host
-host_tick_rate 2225692892 # Simulator tick rate (ticks/s)
+host_inst_rate 828534 # Simulator instruction rate (inst/s)
+host_mem_usage 210088 # Number of bytes of host memory used
+host_seconds 5616.34 # Real time elapsed on the host
+host_tick_rate 1062144168 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 4653327945 # Number of instructions simulated
-sim_seconds 5.988071 # Number of seconds simulated
-sim_ticks 5988071419000 # Number of ticks simulated
+sim_seconds 5.965359 # Number of seconds simulated
+sim_ticks 5965358694000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 1239184749 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 25017.777193 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22017.777193 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 24735.540403 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21735.540403 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 1231961899 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 180699652000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 178661098000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.005829 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 7222850 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 159031102000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 156992548000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005829 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 7222850 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 438528337 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 55999.839821 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52999.839821 # average WriteReq mshr miss latency
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-system.cpu.dcache.WriteReq_miss_rate 0.005125 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 2247488 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 119116504000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.005125 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 2247488 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 183.107599 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 1677713086 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 32370.399029 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 29370.399029 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1668242748 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 306558620000 # number of demand (read+write) miss cycles
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-system.cpu.dcache.demand_misses 9470338 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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-system.cpu.dcache.demand_mshr_misses 9470338 # number of demand (read+write) MSHR misses
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+system.cpu.dcache.demand_mshr_misses 9222600 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.997262 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 4084.783575 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.997251 # Average percentage of cache occupancy
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system.cpu.dcache.overall_accesses 1677713086 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 32370.399029 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 29370.399029 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 30750.347733 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 27750.347733 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1668242748 # number of overall hits
-system.cpu.dcache.overall_miss_latency 306558620000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.005645 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 9470338 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 278147606000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.005645 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 9470338 # number of overall MSHR misses
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+system.cpu.dcache.overall_mshr_misses 9222600 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 9108581 # number of replacements
system.cpu.dcache.sampled_refs 9112677 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 4084.783575 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 4084.741632 # Cycle average of tags in use
system.cpu.dcache.total_refs 1668600409 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 58864073000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 2244395 # number of writebacks
+system.cpu.dcache.warmup_cycle 58862918000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 2365669 # number of writebacks
system.cpu.icache.ReadReq_accesses 4013232927 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.271276 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 555.572992 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.271287 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 555.595041 # Average occupied blocks per context
system.cpu.icache.overall_accesses 4013232927 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.replacements 10 # number of replacements
system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 555.572992 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 555.595041 # Cycle average of tags in use
system.cpu.icache.total_refs 4013232252 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadExReq_accesses 1889827 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 98271004000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 1889827 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 75593080000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 1889827 # number of ReadExReq MSHR misses
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system.cpu.l2cache.ReadReq_accesses 7223525 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 5328094 # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_miss_rate 0.262397 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 1895431 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 75817240000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.262397 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 1895431 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 357661 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 51947.659935 # average UpgradeReq miss latency
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+system.cpu.l2cache.UpgradeReq_avg_miss_latency 51961.682268 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 18579652000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 357661 # number of UpgradeReq misses
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 357661 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.Writeback_accesses 2244395 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits 2244395 # number of Writeback hits
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.demand_accesses 9113352 # number of demand (read+write) accesses
system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
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system.cpu.l2cache.overall_accesses 9113352 # number of overall (read+write) accesses
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-system.cpu.l2cache.overall_mshr_misses 3785258 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 142755640000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.391611 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 3568891 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.replacements 2772035 # number of replacements
-system.cpu.l2cache.sampled_refs 2798208 # Sample count of references to valid blocks.
+system.cpu.l2cache.replacements 2721965 # number of replacements
+system.cpu.l2cache.sampled_refs 2748168 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 25743.046878 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 6663271 # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle 4737794502000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks 1199204 # number of writebacks
+system.cpu.l2cache.tagsinuse 26291.594343 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 6834640 # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle 1346606710000 # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks 1180493 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 11976142838 # number of cpu cycles simulated
+system.cpu.numCycles 11930717388 # number of cpu cycles simulated
system.cpu.num_insts 4653327945 # Number of instructions executed
system.cpu.num_refs 1677713086 # Number of memory references
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing
+cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
For more information see: http://www.m5sim.org/warn/8028fa22
warn: Write Hints currently unimplemented
For more information see: http://www.m5sim.org/warn/cfb3293b
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
+Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jun 25 2010 15:39:41
-M5 revision 93b1ca421839+ 7482+ default qtip tip update_regr
-M5 started Jun 25 2010 15:39:42
-M5 executing on zooks
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 12:18:42
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing
+Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sav
+Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124
\ No newline at end of file
+122 123 124 Exiting @ tick 98337080000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 48476 # Simulator instruction rate (inst/s)
-host_mem_usage 156444 # Number of bytes of host memory used
-host_seconds 1895.84 # Real time elapsed on the host
-host_tick_rate 51872539 # Simulator tick rate (ticks/s)
+host_inst_rate 33745 # Simulator instruction rate (inst/s)
+host_mem_usage 211108 # Number of bytes of host memory used
+host_seconds 2723.45 # Real time elapsed on the host
+host_tick_rate 36107563 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903056 # Number of instructions simulated
-sim_seconds 0.098342 # Number of seconds simulated
-sim_ticks 98342168000 # Number of ticks simulated
+sim_seconds 0.098337 # Number of seconds simulated
+sim_ticks 98337080000 # Number of ticks simulated
system.cpu.AGEN-Unit.agens 26537108 # Number of Address Generations
system.cpu.Branch-Predictor.BTBHitPct 64.034182 # BTB Hit Percentage
system.cpu.Branch-Predictor.BTBHits 5496951 # Number of BTB hits
system.cpu.Execution-Unit.predictedTakenIncorrect 1911977 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed
system.cpu.Mult-Div-Unit.multiplies 458252 # Number of Multipy Operations Executed
-system.cpu.RegFile-Manager.regFileAccesses 185972249 # Number of Total Accesses (Read+Write) to the Register File
-system.cpu.RegFile-Manager.regFileReads 117544888 # Number of Reads from Register File
+system.cpu.RegFile-Manager.regFileAccesses 185972267 # Number of Total Accesses (Read+Write) to the Register File
+system.cpu.RegFile-Manager.regFileReads 117544906 # Number of Reads from Register File
system.cpu.RegFile-Manager.regFileWrites 68427361 # Number of Writes to Register File
-system.cpu.RegFile-Manager.regForwards 2843109 # Number of Registers Read Through Forwarding Logic
-system.cpu.activity 95.455386 # Percentage of cycles cpu is active
+system.cpu.RegFile-Manager.regForwards 2843091 # Number of Registers Read Through Forwarding Logic
+system.cpu.activity 95.460360 # Percentage of cycles cpu is active
system.cpu.comBranches 10240685 # Number of Branches instructions committed
system.cpu.comFloats 3775974 # Number of Floating Point instructions committed
system.cpu.comInts 43625545 # Number of Integer instructions committed
system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total)
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.cpi 2.140128 # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total 2.140128 # CPI: Total CPI of All Threads
+system.cpu.cpi 2.140018 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total 2.140018 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 51549.473684 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48523.157895 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 51551.578947 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48525.263158 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 24486000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency 24487000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 23048500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 23049500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56219.741797 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53219.741797 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 104512500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 98935500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 56221.371882 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53221.371882 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 6499339 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 99174500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000271 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1764 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 93882500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000271 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1764 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55269.280206 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52263.924593 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 26494967 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 128998500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2334 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 55230.683341 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52225.100491 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 26495062 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 123661500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2239 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 121984000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 2334 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 116932000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 2239 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.352015 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 1441.851487 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.352018 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 1441.865798 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55269.280206 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52263.924593 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 55230.683341 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52225.100491 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 26494967 # number of overall hits
-system.cpu.dcache.overall_miss_latency 128998500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2334 # number of overall misses
+system.cpu.dcache.overall_hits 26495062 # number of overall hits
+system.cpu.dcache.overall_miss_latency 123661500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 2239 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 121984000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 2334 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 116932000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 2239 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 157 # number of replacements
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1441.851487 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 1441.865798 # Cycle average of tags in use
system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 104 # number of writebacks
system.cpu.dtb.write_hits 6501103 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.icache.ReadReq_accesses 101762751 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 27218.382183 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 27218.266790 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 23985.018072 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 101754085 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 235874500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 235873500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.000085 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 8666 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 89 # number of ReadReq MSHR hits
system.cpu.icache.blocked_cycles::no_targets 2000 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 101762751 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 27218.382183 # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency 27218.266790 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 23985.018072 # average overall mshr miss latency
system.cpu.icache.demand_hits 101754085 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 235874500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 235873500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.000085 # miss rate for demand accesses
system.cpu.icache.demand_misses 8666 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 89 # number of demand (read+write) MSHR hits
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.697630 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1428.745723 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.697638 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1428.763035 # Average occupied blocks per context
system.cpu.icache.overall_accesses 101762751 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 27218.382183 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency 27218.266790 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 23985.018072 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 101754085 # number of overall hits
-system.cpu.icache.overall_miss_latency 235874500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 235873500 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.000085 # miss rate for overall accesses
system.cpu.icache.overall_misses 8666 # number of overall misses
system.cpu.icache.overall_mshr_hits 89 # number of overall MSHR hits
system.cpu.icache.replacements 6743 # number of replacements
system.cpu.icache.sampled_refs 8577 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1428.745723 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1428.763035 # Cycle average of tags in use
system.cpu.icache.total_refs 101754085 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 8938543 # Number of cycles cpu's stages were not processed
-system.cpu.ipc 0.467262 # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total 0.467262 # IPC: Total IPC of All Threads
+system.cpu.idleCycles 8928298 # Number of cycles cpu's stages were not processed
+system.cpu.ipc 0.467286 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total 0.467286 # IPC: Total IPC of All Threads
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52212.528604 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52216.819222 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40005.720824 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 91267500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 91275000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 1748 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 69930000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 1748 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 9052 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52167.646099 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 52167.809337 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40020.078355 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 5989 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 159789500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 159790000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.338378 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 3063 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 122581500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338378 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3063 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52265.765766 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40009.009009 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 5801500 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_accesses 16 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 52250 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40062.500000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 836000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4441000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 16 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 641000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 111 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses 16 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 1.971947 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 1.912000 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 10800 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52183.953440 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52185.616296 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40014.861775 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 5989 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 251057000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 251065000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.445463 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 4811 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.061824 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::0 0.063287 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.000419 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 2025.851218 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 13.722274 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::0 2073.775621 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 13.721424 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 10800 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52183.953440 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52185.616296 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40014.861775 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 5989 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 251057000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 251065000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.445463 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 4811 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 3030 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 3125 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 2039.573492 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 2087.497045 # Cycle average of tags in use
system.cpu.l2cache.total_refs 5975 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 196684337 # number of cpu cycles simulated
-system.cpu.runCycles 187745794 # Number of cycles cpu stages are processed.
+system.cpu.numCycles 196674161 # number of cpu cycles simulated
+system.cpu.runCycles 187745863 # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
-system.cpu.stage-0.idleCycles 94921538 # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.idleCycles 94911362 # Number of cycles 0 instructions are processed.
system.cpu.stage-0.runCycles 101762799 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-0.utilization 51.739147 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-1.idleCycles 104523823 # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.utilization 51.741824 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-1.idleCycles 104513647 # Number of cycles 0 instructions are processed.
system.cpu.stage-1.runCycles 92160514 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-1.utilization 46.857068 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-2.idleCycles 103191853 # Number of cycles 0 instructions are processed.
+system.cpu.stage-1.utilization 46.859493 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-2.idleCycles 103181677 # Number of cycles 0 instructions are processed.
system.cpu.stage-2.runCycles 93492484 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-2.utilization 47.534280 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-3.idleCycles 170147206 # Number of cycles 0 instructions are processed.
+system.cpu.stage-2.utilization 47.536740 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-3.idleCycles 170137030 # Number of cycles 0 instructions are processed.
system.cpu.stage-3.runCycles 26537131 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-3.utilization 13.492244 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-4.idleCycles 104781281 # Number of cycles 0 instructions are processed.
+system.cpu.stage-3.utilization 13.492942 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-4.idleCycles 104771105 # Number of cycles 0 instructions are processed.
system.cpu.stage-4.runCycles 91903056 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-4.utilization 46.726169 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.threadCycles 196684337 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.stage-4.utilization 46.728587 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.threadCycles 196674161 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
---------- End Simulation Statistics ----------
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
+cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
-Redirecting stdout to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/simerr
+Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jun 6 2010 03:04:38
-M5 revision ba1a0193c050 7448 default tip
-M5 started Jun 6 2010 03:04:41
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 12:11:51
M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing
-Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sav
-Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
+Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav
+Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124
\ No newline at end of file
+122 123 124 Exiting @ tick 40700936000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 133236 # Simulator instruction rate (inst/s)
-host_mem_usage 211268 # Number of bytes of host memory used
-host_seconds 631.81 # Real time elapsed on the host
-host_tick_rate 63779599 # Simulator tick rate (ticks/s)
+host_inst_rate 126678 # Simulator instruction rate (inst/s)
+host_mem_usage 211676 # Number of bytes of host memory used
+host_seconds 664.52 # Real time elapsed on the host
+host_tick_rate 61249065 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 84179709 # Number of instructions simulated
-sim_seconds 0.040297 # Number of seconds simulated
-sim_ticks 40296654500 # Number of ticks simulated
+sim_seconds 0.040701 # Number of seconds simulated
+sim_ticks 40700936000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 11897638 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 15852760 # Number of BTB lookups
-system.cpu.BPredUnit.RASInCorrect 1209 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 1887267 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 14560688 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 19536875 # Number of BP lookups
-system.cpu.BPredUnit.usedRAS 1737186 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.BTBHits 11915731 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 15874516 # Number of BTB lookups
+system.cpu.BPredUnit.RASInCorrect 1218 # Number of incorrect RAS predictions.
+system.cpu.BPredUnit.condIncorrect 1889856 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 14601933 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 19578482 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 1736849 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 10240685 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 2907966 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 2865019 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 72454759 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 1.268420 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.963909 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 73200115 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 1.255504 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.951469 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 35335976 48.77% 48.77% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 18219580 25.15% 73.92% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 7350657 10.15% 84.06% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 3843959 5.31% 89.37% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 2026400 2.80% 92.16% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 1285963 1.77% 93.94% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 738665 1.02% 94.96% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 745593 1.03% 95.99% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 2907966 4.01% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 35882998 49.02% 49.02% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 18421131 25.17% 74.19% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 7399939 10.11% 84.30% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 3793003 5.18% 89.48% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 2033143 2.78% 92.25% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 1324637 1.81% 94.06% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 734587 1.00% 95.07% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 745658 1.02% 96.09% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 2865019 3.91% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 72454759 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 73200115 # Number of insts commited each cycle
system.cpu.commit.COM:count 91903055 # Number of instructions committed
system.cpu.commit.COM:loads 20034413 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.COM:refs 26537108 # Number of memory references committed
system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 1874087 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 1876719 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 55786698 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 56257070 # The number of squashed insts skipped by commit
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
-system.cpu.cpi 0.957396 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.957396 # CPI: Total CPI of All Threads
+system.cpu.cpi 0.967001 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.967001 # CPI: Total CPI of All Threads
system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_hits 11 # number of LoadLockedReq hits
-system.cpu.dcache.ReadReq_accesses 23323647 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 30060.090703 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32045.634921 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 23322765 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 26513000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_accesses 23361768 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 30148.648649 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32165.686275 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 23360880 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 26772000 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 882 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses 888 # number of ReadReq misses
system.cpu.dcache.ReadReq_mshr_hits 378 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 16151000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency 16404500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 504 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses 510 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 35743.318729 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36228.400108 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 6492795 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 296955492 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.001278 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 8308 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 6456 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 67094997 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000285 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1852 # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 4187.125000 # average number of cycles each access was blocked
+system.cpu.dcache.WriteReq_avg_miss_latency 35665.614165 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35983.686319 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 6493027 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 288035500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.001242 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 8076 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 6329 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 62863500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1747 # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 13310.644643 # Average number of references to valid blocks.
-system.cpu.dcache.blocked::no_mshrs 8 # number of cycles access was blocked
+system.cpu.dcache.avg_refs 13315.768510 # Average number of references to valid blocks.
+system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_mshrs 33497 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 29824750 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 35197.877258 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35333.615025 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 29815560 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 323468492 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000308 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 9190 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 6834 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 83245997 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000079 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 2356 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 29862871 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 35119.087461 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35120.957023 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 29853907 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 314807500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000300 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 8964 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 6707 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 79268000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000076 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 2257 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.356016 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 1458.239906 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 29824750 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 35197.877258 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35333.615025 # average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.356506 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 1460.250343 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 29862871 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 35119.087461 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35120.957023 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 29815560 # number of overall hits
-system.cpu.dcache.overall_miss_latency 323468492 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000308 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 9190 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 6834 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 83245997 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000079 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 2356 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 29853907 # number of overall hits
+system.cpu.dcache.overall_miss_latency 314807500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000300 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 8964 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 6707 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 79268000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000076 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 2257 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 160 # number of replacements
-system.cpu.dcache.sampled_refs 2240 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 2242 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1458.239906 # Cycle average of tags in use
-system.cpu.dcache.total_refs 29815844 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 1460.250343 # Cycle average of tags in use
+system.cpu.dcache.total_refs 29853953 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 106 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 3560307 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 13329 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 3136527 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 162153476 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 39273061 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 29418237 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 8029960 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 48947 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 203154 # Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses 31794123 # DTB accesses
+system.cpu.decode.DECODE:BlockedCycles 4195548 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 13275 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 3138319 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 162326104 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 39347421 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 29437279 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 8092915 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 48049 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 219867 # Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses 31798312 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_hits 31394253 # DTB hits
-system.cpu.dtb.data_misses 399870 # DTB misses
+system.cpu.dtb.data_hits 31419824 # DTB hits
+system.cpu.dtb.data_misses 378488 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 24584547 # DTB read accesses
+system.cpu.dtb.read_accesses 24587008 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 24185700 # DTB read hits
-system.cpu.dtb.read_misses 398847 # DTB read misses
-system.cpu.dtb.write_accesses 7209576 # DTB write accesses
+system.cpu.dtb.read_hits 24209579 # DTB read hits
+system.cpu.dtb.read_misses 377429 # DTB read misses
+system.cpu.dtb.write_accesses 7211304 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 7208553 # DTB write hits
-system.cpu.dtb.write_misses 1023 # DTB write misses
-system.cpu.fetch.Branches 19536875 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 19049745 # Number of cache lines fetched
-system.cpu.fetch.Cycles 49533111 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 485697 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 167120080 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 2034068 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.242413 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 19049745 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 13634824 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 2.073622 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 80484719 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.076420 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.094224 # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.write_hits 7210245 # DTB write hits
+system.cpu.dtb.write_misses 1059 # DTB write misses
+system.cpu.fetch.Branches 19578482 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 19042269 # Number of cache lines fetched
+system.cpu.fetch.Cycles 49581999 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 482446 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 167417229 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 2029251 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.240516 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 19042269 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 13652580 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 2.056675 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 81293030 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.059429 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.087442 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 50001427 62.13% 62.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 3132178 3.89% 66.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1884597 2.34% 68.36% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 3228306 4.01% 72.37% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 4370184 5.43% 77.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1507606 1.87% 79.67% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1854945 2.30% 81.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1658454 2.06% 84.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 12847022 15.96% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 50753371 62.43% 62.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 3139837 3.86% 66.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1896166 2.33% 68.63% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 3230989 3.97% 72.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 4381492 5.39% 77.99% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1498123 1.84% 79.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1855484 2.28% 82.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1657938 2.04% 84.16% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 12879630 15.84% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 80484719 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses 19049745 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 15752.064632 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11876.097465 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 19038605 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 175478000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.000585 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 11140 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 1003 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 120388000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000532 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses 10137 # number of ReadReq MSHR misses
+system.cpu.fetch.rateDist::total 81293030 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 19042269 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 15754.189443 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11879.245840 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 19031110 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 175801000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.000586 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 11159 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 1002 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 120657500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.000533 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses 10157 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 1878.130117 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 1873.694004 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 19049745 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 15752.064632 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11876.097465 # average overall mshr miss latency
-system.cpu.icache.demand_hits 19038605 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 175478000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.000585 # miss rate for demand accesses
-system.cpu.icache.demand_misses 11140 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 1003 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 120388000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.000532 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses 10137 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_accesses 19042269 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 15754.189443 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11879.245840 # average overall mshr miss latency
+system.cpu.icache.demand_hits 19031110 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 175801000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.000586 # miss rate for demand accesses
+system.cpu.icache.demand_misses 11159 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 1002 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 120657500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.000533 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses 10157 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.755796 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1547.870707 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 19049745 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 15752.064632 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11876.097465 # average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.756087 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1548.466977 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 19042269 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 15754.189443 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11879.245840 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 19038605 # number of overall hits
-system.cpu.icache.overall_miss_latency 175478000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.000585 # miss rate for overall accesses
-system.cpu.icache.overall_misses 11140 # number of overall misses
-system.cpu.icache.overall_mshr_hits 1003 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 120388000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.000532 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 10137 # number of overall MSHR misses
+system.cpu.icache.overall_hits 19031110 # number of overall hits
+system.cpu.icache.overall_miss_latency 175801000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.000586 # miss rate for overall accesses
+system.cpu.icache.overall_misses 11159 # number of overall misses
+system.cpu.icache.overall_mshr_hits 1002 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 120657500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.000533 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses 10157 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 8223 # number of replacements
-system.cpu.icache.sampled_refs 10137 # Sample count of references to valid blocks.
+system.cpu.icache.replacements 8241 # number of replacements
+system.cpu.icache.sampled_refs 10157 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1547.870707 # Cycle average of tags in use
-system.cpu.icache.total_refs 19038605 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 1548.466977 # Cycle average of tags in use
+system.cpu.icache.total_refs 19031110 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 108591 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 12897175 # Number of branches executed
-system.cpu.iew.EXEC:nop 12739019 # number of nop insts executed
-system.cpu.iew.EXEC:rate 1.262855 # Inst execution rate
-system.cpu.iew.EXEC:refs 31847616 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 7211217 # Number of stores executed
+system.cpu.idleCycles 108843 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 12932923 # Number of branches executed
+system.cpu.iew.EXEC:nop 12752202 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.252024 # Inst execution rate
+system.cpu.iew.EXEC:refs 31851727 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 7212953 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 91218394 # num instructions consuming a value
-system.cpu.iew.WB:count 99932054 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.721984 # average fanout of values written-back
+system.cpu.iew.WB:consumers 91350917 # num instructions consuming a value
+system.cpu.iew.WB:count 100121723 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.722506 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 65858228 # num instructions producing a value
-system.cpu.iew.WB:rate 1.239955 # insts written-back per cycle
-system.cpu.iew.WB:sent 100793715 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 2037312 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 220727 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 33778811 # Number of dispatched load instructions
-system.cpu.iew.iewDispNonSpecInsts 434 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 1499848 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 10610374 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 147688610 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 24636399 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2142931 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 101777656 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 90810 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.WB:producers 66001625 # num instructions producing a value
+system.cpu.iew.WB:rate 1.229968 # insts written-back per cycle
+system.cpu.iew.WB:sent 100959925 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 2058548 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 308035 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 33906352 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 439 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 1495689 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 10659868 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 148158966 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 24638774 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2167496 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 101917138 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 147063 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewLSQFullEvents 223 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 8029960 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 123733 # Number of cycles IEW is unblocking
+system.cpu.iew.iewLSQFullEvents 222 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 8092915 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 184741 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread.0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 852201 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread.0.ignoredResponses 2584 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 837967 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 2533 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 270101 # Number of memory ordering violations
-system.cpu.iew.lsq.thread.0.rescheduledLoads 9831 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 13744398 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 4107679 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 270101 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 440641 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 1596671 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 1.044500 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.044500 # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.memOrderViolation 262394 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 9832 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 13871939 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 4157173 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 262394 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 456488 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 1602060 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 1.034125 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.034125 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu 64410892 61.98% 61.98% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult 474451 0.46% 62.44% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.44% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2784957 2.68% 65.12% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp 114528 0.11% 65.23% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2385482 2.30% 67.52% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 305123 0.29% 67.82% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 755228 0.73% 68.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 324 0.00% 68.54% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 25350766 24.39% 92.94% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 7338829 7.06% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 64580885 62.05% 62.05% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 474250 0.46% 62.50% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.50% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2786793 2.68% 65.18% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 114549 0.11% 65.29% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2387015 2.29% 67.58% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 305140 0.29% 67.88% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 754986 0.73% 68.60% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 323 0.00% 68.60% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 25334190 24.34% 92.94% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 7346496 7.06% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 103920587 # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt 1852625 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.017827 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 104084634 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 1605159 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.015422 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 210356 11.35% 11.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.35% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd 363 0.02% 11.37% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.37% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt 3342 0.18% 11.55% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult 2324 0.13% 11.68% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv 819264 44.22% 55.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 55.90% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 748090 40.38% 96.28% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite 68886 3.72% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 233517 14.55% 14.55% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 14.55% # attempts to use FU when none available
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+system.cpu.iq.ISSUE:fu_full::FloatAdd 339 0.02% 14.57% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 14.57% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt 3702 0.23% 14.80% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 2371 0.15% 14.95% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv 538253 33.53% 48.48% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 48.48% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 750460 46.75% 95.23% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 76517 4.77% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 80484719 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 1.291184 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.543424 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples 81293030 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 1.280364 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.539599 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 34420666 42.77% 42.77% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 18632497 23.15% 65.92% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 11734091 14.58% 80.50% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 6720766 8.35% 88.85% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 5079668 6.31% 95.16% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 2378591 2.96% 98.11% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 1227784 1.53% 99.64% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 245969 0.31% 99.94% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8 44687 0.06% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 34992329 43.04% 43.04% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 18915944 23.27% 66.31% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 11753054 14.46% 80.77% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 6613669 8.14% 88.91% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 5112903 6.29% 95.20% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 2406334 2.96% 98.16% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 1201307 1.48% 99.63% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 249469 0.31% 99.94% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 48021 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 80484719 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 1.289444 # Inst issue rate
-system.cpu.iq.iqInstsAdded 134949157 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 103920587 # Number of instructions issued
-system.cpu.iq.iqNonSpecInstsAdded 434 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 50119883 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 297027 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 46887079 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.ISSUE:issued_per_cycle::total 81293030 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 1.278652 # Inst issue rate
+system.cpu.iq.iqInstsAdded 135406325 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 104084634 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 439 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 50573904 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 302099 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 50 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 47258027 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 19049819 # ITB accesses
+system.cpu.itb.fetch_accesses 19042340 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_hits 19049745 # ITB hits
-system.cpu.itb.fetch_misses 74 # ITB misses
+system.cpu.itb.fetch_hits 19042269 # ITB hits
+system.cpu.itb.fetch_misses 71 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.l2cache.ReadExReq_accesses 1736 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34694.700461 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31523.329493 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 60230000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_accesses 1732 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34688.510393 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31520.207852 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 60080500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_misses 1736 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 54724500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_misses 1732 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 54593000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_misses 1736 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 10641 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34281.074697 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31079.421317 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits 7254 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 116110000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.318297 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses 3387 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 105266000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318297 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses 3387 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 123 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34414.634146 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31256.097561 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 4233000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_mshr_misses 1732 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadReq_accesses 10667 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency 34283.465725 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.788761 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits 7268 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency 116529500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate 0.318646 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses 3399 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency 105647000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318646 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses 3399 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_avg_miss_latency 34166.666667 # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_miss_latency 512500 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 123 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 3844500 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 465000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 123 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 106 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 106 # number of Writeback hits
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs 4333.333333 # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 2.165420 # Average number of references to valid blocks.
-system.cpu.l2cache.blocked::no_mshrs 3 # number of cycles access was blocked
+system.cpu.l2cache.avg_refs 2.094427 # Average number of references to valid blocks.
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_mshrs 13000 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 12377 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34421.237556 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31229.845793 # average overall mshr miss latency
-system.cpu.l2cache.demand_hits 7254 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 176340000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.413913 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 5123 # number of demand (read+write) misses
+system.cpu.l2cache.demand_accesses 12399 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency 34420.190996 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31229.779770 # average overall mshr miss latency
+system.cpu.l2cache.demand_hits 7268 # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency 176610000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.413824 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 5131 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 159990500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate 0.413913 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses 5123 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_latency 160240000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate 0.413824 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses 5131 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.068298 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_%::1 0.000414 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 2237.998108 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 13.556876 # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses 12377 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34421.237556 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31229.845793 # average overall mshr miss latency
+system.cpu.l2cache.occ_%::0 0.070268 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::1 0.000413 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 2302.538330 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 13.547355 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 12399 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency 34420.190996 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31229.779770 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits 7254 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 176340000 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.413913 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 5123 # number of overall misses
+system.cpu.l2cache.overall_hits 7268 # number of overall hits
+system.cpu.l2cache.overall_miss_latency 176610000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.413824 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 5131 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 159990500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate 0.413913 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses 5123 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_latency 160240000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate 0.413824 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses 5131 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 3343 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 3463 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 2251.554984 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 7239 # Total number of references to valid blocks.
+system.cpu.l2cache.tagsinuse 2316.085685 # Cycle average of tags in use
+system.cpu.l2cache.total_refs 7253 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.memDep0.conflictingLoads 17229574 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 5033996 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 33778811 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 10610374 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 80593310 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 1589033 # Number of cycles rename is blocking
+system.cpu.memDep0.conflictingLoads 17615087 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 5052814 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 33906352 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 10659868 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 81401873 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 1958439 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 926186 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 40466713 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 962025 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 202340521 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 157033543 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 115331786 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 28409670 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 8029960 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 1983994 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 46904425 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 5349 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 467 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 4530466 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 456 # count of temporary serializing insts renamed
-system.cpu.timesIdled 2422 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:IQFullEvents 1204670 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 40603212 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 943778 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 202469078 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 157094553 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 115390079 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 28386104 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 8092915 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 2247194 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 46962718 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 5166 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 474 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 4950472 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 463 # count of temporary serializing insts renamed
+system.cpu.timesIdled 2416 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
---------- End Simulation Statistics ----------
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
+cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/twolf
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
+warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
+For more information see: http://www.m5sim.org/warn/5c5b547f
+hack: be nice to actually delete the event here
+Redirecting stdout to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Feb 24 2010 23:12:40
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 02:41:35
-M5 executing on SC2B0619
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:58:58
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing
+Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sav
+Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124
\ No newline at end of file
+122 123 124 Exiting @ tick 118742021000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 611509 # Simulator instruction rate (inst/s)
-host_mem_usage 195576 # Number of bytes of host memory used
-host_seconds 150.29 # Real time elapsed on the host
-host_tick_rate 790125098 # Simulator tick rate (ticks/s)
+host_inst_rate 1269659 # Simulator instruction rate (inst/s)
+host_mem_usage 210612 # Number of bytes of host memory used
+host_seconds 72.38 # Real time elapsed on the host
+host_tick_rate 1640438984 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 91903056 # Number of instructions simulated
-sim_seconds 0.118747 # Number of seconds simulated
-sim_ticks 118747246000 # Number of ticks simulated
+sim_seconds 0.118742 # Number of seconds simulated
+sim_ticks 118742021000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 6499244 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 104104000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000286 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1859 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 98527000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000286 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1859 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_hits 6499339 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 98784000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000271 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1764 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 93492000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000271 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1764 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55046.272494 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 26494967 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 128478000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.000088 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 2334 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 55005.806163 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52005.806163 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 26495062 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 123158000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 2239 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 121476000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.000088 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 2334 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 116441000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 2239 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.352056 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 1442.022508 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.352059 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 1442.035674 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55046.272494 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52046.272494 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 55005.806163 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52005.806163 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 26494967 # number of overall hits
-system.cpu.dcache.overall_miss_latency 128478000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.000088 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 2334 # number of overall misses
+system.cpu.dcache.overall_hits 26495062 # number of overall hits
+system.cpu.dcache.overall_miss_latency 123158000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 2239 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 121476000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.000088 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 2334 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 116441000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 2239 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 157 # number of replacements
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1442.022508 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 1442.035674 # Cycle average of tags in use
system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 104 # number of writebacks
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.692396 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1418.025998 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.692403 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1418.041181 # Average occupied blocks per context
system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
system.cpu.icache.replacements 6681 # number of replacements
system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1418.025998 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1418.041181 # Cycle average of tags in use
system.cpu.icache.total_refs 91894580 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_miss_latency 121720000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338676 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3043 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 111 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses 16 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 5772000 # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency 832000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 111 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 4440000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_misses 16 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency 640000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 111 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses 16 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 104 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 104 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 1.969435 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 1.909179 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.061290 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::0 0.062752 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.000419 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 2008.334369 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 13.724981 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::0 2056.260143 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 13.724287 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 10733 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 3010 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 3105 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 2022.059349 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 2069.984431 # Cycle average of tags in use
system.cpu.l2cache.total_refs 5928 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 237494492 # number of cpu cycles simulated
+system.cpu.numCycles 237484042 # number of cpu cycles simulated
system.cpu.num_insts 91903056 # Number of instructions executed
system.cpu.num_refs 26537141 # Number of memory references
system.cpu.workload.PROG:num_syscalls 389 # Number of system calls
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing
+cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
egid=100
env=
errout=cerr
+Redirecting stdout to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/simout
+Redirecting stderr to build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Aug 24 2010 15:34:40
-M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
-M5 started Aug 24 2010 15:39:29
+M5 compiled Aug 26 2010 13:52:30
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:54:23
M5 executing on zizzer
-command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing
-Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sav
-Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sv2
+command line: build/ARM_SE/m5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
+Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sav
+Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 232029492000 because target called exit()
+122 123 124 Exiting @ tick 232028062000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 1662173 # Simulator instruction rate (inst/s)
-host_mem_usage 213456 # Number of bytes of host memory used
-host_seconds 112.10 # Real time elapsed on the host
-host_tick_rate 2069793412 # Simulator tick rate (ticks/s)
+host_inst_rate 1713926 # Simulator instruction rate (inst/s)
+host_mem_usage 214560 # Number of bytes of host memory used
+host_seconds 108.72 # Real time elapsed on the host
+host_tick_rate 2134224518 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 186333855 # Number of instructions simulated
-sim_seconds 0.232029 # Number of seconds simulated
-sim_ticks 232029492000 # Number of ticks simulated
+sim_seconds 0.232028 # Number of seconds simulated
+sim_ticks 232028062000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 29640180 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 52469.565217 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 49469.565217 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_accesses 12386694 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 12385567 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 63112000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000091 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1127 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 59731000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000091 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1127 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_hits 12385593 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 61656000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000089 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1101 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 58353000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1101 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 23477.700559 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 42026874 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 54659.328564 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51659.328564 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 42025057 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 99316000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000043 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1817 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 93865000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 92487000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000043 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1817 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.333153 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 1364.595461 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 42026874 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 54659.328564 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51659.328564 # average overall mshr miss latency
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+system.cpu.dcache.overall_avg_mshr_miss_latency 51639.865997 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 42025057 # number of overall hits
-system.cpu.dcache.overall_miss_latency 99316000 # number of overall miss cycles
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system.cpu.dcache.overall_miss_rate 0.000043 # miss rate for overall accesses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_rate 0.000043 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1817 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 40 # number of replacements
system.cpu.dcache.sampled_refs 1790 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1364.595461 # Cycle average of tags in use
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system.cpu.dcache.total_refs 42025084 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 16 # number of writebacks
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.560534 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1147.972858 # Average occupied blocks per context
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system.cpu.icache.overall_accesses 189792839 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 37801.376598 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency
system.cpu.icache.replacements 1506 # number of replacements
system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1147.972858 # Cycle average of tags in use
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system.cpu.icache.total_refs 189789788 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_miss_latency 94440000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.631115 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 2361 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 27 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 1404000 # number of UpgradeReq miss cycles
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system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 27 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1080000 # number of UpgradeReq MSHR miss cycles
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 27 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.Writeback_accesses 16 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 16 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.l2cache.occ_%::1 0.000062 # Average percentage of cache occupancy
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system.cpu.l2cache.overall_accesses 4841 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 2342 # Sample count of references to valid blocks.
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system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 1652.648529 # Cycle average of tags in use
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system.cpu.l2cache.total_refs 1379 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 464058984 # number of cpu cycles simulated
+system.cpu.numCycles 464056124 # number of cpu cycles simulated
system.cpu.num_insts 186333855 # Number of instructions executed
system.cpu.num_refs 42511846 # Number of memory references
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing
+cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing
egid=100
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/sparc/linux/twolf
+executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Feb 25 2010 03:11:27
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:37:15
-M5 executing on SC2B0619
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing
+M5 compiled Aug 26 2010 13:03:41
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:03:51
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing
+Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sav
+Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
info: Increasing stack size by one page.
-122 123 124 Exiting @ tick 270578335000 because target called exit()
+122 123 124 Exiting @ tick 270576960000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 890462 # Simulator instruction rate (inst/s)
-host_mem_usage 197912 # Number of bytes of host memory used
-host_seconds 217.24 # Real time elapsed on the host
-host_tick_rate 1245520491 # Simulator tick rate (ticks/s)
+host_inst_rate 953366 # Simulator instruction rate (inst/s)
+host_mem_usage 216056 # Number of bytes of host memory used
+host_seconds 202.91 # Real time elapsed on the host
+host_tick_rate 1333500122 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 193444769 # Number of instructions simulated
-sim_seconds 0.270578 # Number of seconds simulated
-sim_ticks 270578335000 # Number of ticks simulated
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+sim_ticks 270576960000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 57735069 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.dcache.SwapReq_accesses 22406 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_avg_miss_latency 56000 # average SwapReq miss latency
system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
-system.cpu.dcache.SwapReq_hits 22404 # number of SwapReq hits
-system.cpu.dcache.SwapReq_miss_latency 112000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_rate 0.000089 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_misses 2 # number of SwapReq misses
-system.cpu.dcache.SwapReq_mshr_miss_latency 106000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_rate 0.000089 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_mshr_misses 2 # number of SwapReq MSHR misses
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+system.cpu.dcache.SwapReq_mshr_misses 1 # number of SwapReq MSHR misses
system.cpu.dcache.WriteReq_accesses 18976439 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 18975338 # number of WriteReq hits
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-system.cpu.dcache.WriteReq_miss_rate 0.000058 # miss rate for WriteReq accesses
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-system.cpu.dcache.WriteReq_mshr_misses 1101 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 48688.031726 # Average number of references to valid blocks.
system.cpu.dcache.demand_accesses 76711508 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 76709909 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_rate 0.000021 # miss rate for demand accesses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_miss_rate 0.000021 # mshr miss rate for demand accesses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.overall_accesses 76711508 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_mshr_miss_rate 0.000021 # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.dcache.replacements 2 # number of replacements
system.cpu.dcache.sampled_refs 1576 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.total_refs 76732338 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 2 # number of writebacks
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_accesses 193445549 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency
system.cpu.icache.replacements 10362 # number of replacements
system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1591.566647 # Cycle average of tags in use
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system.cpu.icache.total_refs 193433261 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_miss_latency 163800000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320272 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 4095 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 25 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 1300000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 25 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1000000 # number of UpgradeReq MSHR miss cycles
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-system.cpu.l2cache.UpgradeReq_mshr_misses 25 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 2 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 2 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.081095 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::0 0.081736 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.000000 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 2657.327524 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 0.000455 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::0 2678.326682 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 0.000454 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 13864 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 4072 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 4097 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 2657.327979 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 2678.327135 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8691 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 541156670 # number of cpu cycles simulated
+system.cpu.numCycles 541153920 # number of cpu cycles simulated
system.cpu.num_insts 193444769 # Number of instructions executed
system.cpu.num_refs 76733959 # Number of memory references
system.cpu.workload.PROG:num_syscalls 401 # Number of system calls
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
+cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
egid=100
env=
errout=cerr
+Redirecting stdout to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled May 2 2010 23:23:01
-M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
-M5 started May 2 2010 23:23:02
-M5 executing on burrito
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing
-Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sav
-Couldn't unlink build/X86_SE/tests/fast/long/70.twolf/x86/linux/simple-timing/smred.sv2
+M5 compiled Aug 26 2010 13:20:12
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:26:25
+M5 executing on zizzer
+command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
+Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav
+Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 250962187000 because target called exit()
+122 123 124 Exiting @ tick 250960757000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 1720597 # Simulator instruction rate (inst/s)
-host_mem_usage 232456 # Number of bytes of host memory used
-host_seconds 127.53 # Real time elapsed on the host
-host_tick_rate 1967834922 # Simulator tick rate (ticks/s)
+host_inst_rate 935562 # Simulator instruction rate (inst/s)
+host_mem_usage 217504 # Number of bytes of host memory used
+host_seconds 234.54 # Real time elapsed on the host
+host_tick_rate 1069990696 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 219431024 # Number of instructions simulated
-sim_seconds 0.250962 # Number of seconds simulated
-sim_ticks 250962187000 # Number of ticks simulated
+sim_seconds 0.250961 # Number of seconds simulated
+sim_ticks 250960757000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 56682008 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 20514126 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 89824000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.000078 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 1604 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 85012000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.000078 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 1604 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_hits 20514152 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 88368000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.000077 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 1578 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 83634000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.000077 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 1578 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 40522.746982 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 77197738 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55848.783014 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52848.524081 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 77195807 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 107844000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_avg_miss_latency 55846.719160 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52846.456693 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 77195833 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 106388000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1931 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses 1905 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 102050500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency 100672500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 1931 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses 1905 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.332873 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 1363.445907 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.332874 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 1363.451646 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 77197738 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55848.783014 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52848.524081 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 55846.719160 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52846.456693 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 77195807 # number of overall hits
-system.cpu.dcache.overall_miss_latency 107844000 # number of overall miss cycles
+system.cpu.dcache.overall_hits 77195833 # number of overall hits
+system.cpu.dcache.overall_miss_latency 106388000 # number of overall miss cycles
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1931 # number of overall misses
+system.cpu.dcache.overall_misses 1905 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 102050500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency 100672500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 1931 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses 1905 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 41 # number of replacements
system.cpu.dcache.sampled_refs 1905 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 1363.445907 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 1363.451646 # Cycle average of tags in use
system.cpu.dcache.total_refs 77195833 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 7 # number of writebacks
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.710587 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 1455.283090 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.710590 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 1455.289171 # Average occupied blocks per context
system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718 # average overall mshr miss latency
system.cpu.icache.replacements 2836 # number of replacements
system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 1455.283090 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 1455.289171 # Cycle average of tags in use
system.cpu.icache.total_refs 173489718 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_miss_latency 126400000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629357 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 3160 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 26 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 1352000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 26 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1040000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 26 # number of UpgradeReq MSHR misses
system.cpu.l2cache.Writeback_accesses 7 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_hits 7 # number of Writeback hits
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.593053 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.588180 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.062108 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_%::0 0.062810 # Average percentage of cache occupancy
system.cpu.l2cache.occ_%::1 0.000001 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 2035.144824 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 0.021758 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::0 2058.146657 # Average occupied blocks per context
+system.cpu.l2cache.occ_blocks::1 0.021757 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 6599 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52003.271423 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 3138 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 3164 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 2035.166582 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 2058.168414 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1861 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 501924374 # number of cpu cycles simulated
+system.cpu.numCycles 501921514 # number of cpu cycles simulated
system.cpu.num_insts 219431024 # Number of instructions executed
system.cpu.num_refs 77165306 # Number of memory references
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
+Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jun 25 2010 15:39:10
-M5 revision 93b1ca421839 7482 default qtip tip update_regr
-M5 started Jun 25 2010 15:39:11
-M5 executing on zooks
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:52:02
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 31194000 because target called exit()
+Exiting @ tick 30538000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 22440 # Simulator instruction rate (inst/s)
-host_mem_usage 153392 # Number of bytes of host memory used
-host_seconds 0.29 # Real time elapsed on the host
-host_tick_rate 109185606 # Simulator tick rate (ticks/s)
+host_inst_rate 4413 # Simulator instruction rate (inst/s)
+host_mem_usage 204480 # Number of bytes of host memory used
+host_seconds 1.45 # Real time elapsed on the host
+host_tick_rate 21040041 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
sim_seconds 0.000031 # Number of seconds simulated
-sim_ticks 31194000 # Number of ticks simulated
+sim_ticks 30538000 # Number of ticks simulated
system.cpu.AGEN-Unit.agens 2050 # Number of Address Generations
system.cpu.Branch-Predictor.BTBHitPct 29.967427 # BTB Hit Percentage
system.cpu.Branch-Predictor.BTBHits 92 # Number of BTB hits
system.cpu.Execution-Unit.predictedTakenIncorrect 6 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed
system.cpu.Mult-Div-Unit.multiplies 1 # Number of Multipy Operations Executed
-system.cpu.RegFile-Manager.regFileAccesses 12569 # Number of Total Accesses (Read+Write) to the Register File
-system.cpu.RegFile-Manager.regFileReads 7986 # Number of Reads from Register File
+system.cpu.RegFile-Manager.regFileAccesses 12573 # Number of Total Accesses (Read+Write) to the Register File
+system.cpu.RegFile-Manager.regFileReads 7990 # Number of Reads from Register File
system.cpu.RegFile-Manager.regFileWrites 4583 # Number of Writes to Register File
-system.cpu.RegFile-Manager.regForwards 315 # Number of Registers Read Through Forwarding Logic
-system.cpu.activity 21.904502 # Percentage of cycles cpu is active
+system.cpu.RegFile-Manager.regForwards 311 # Number of Registers Read Through Forwarding Logic
+system.cpu.activity 22.376672 # Percentage of cycles cpu is active
system.cpu.comBranches 1051 # Number of Branches instructions committed
system.cpu.comFloats 2 # Number of Floating Point instructions committed
system.cpu.comInts 3265 # Number of Integer instructions committed
system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total)
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.cpi 9.742192 # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total 9.742192 # CPI: Total CPI of All Threads
+system.cpu.cpi 9.537320 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total 9.537320 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 56384.210526 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53384.210526 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56068.965517 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53068.965517 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 4878000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 4617000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 56068.493151 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53068.493151 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 792 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 4093000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.084393 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 3874000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 56233.516484 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53233.516484 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 10234500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 56247.023810 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 53247.023810 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 1882 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 9449500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.081951 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 168 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 9688500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 8945500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.025297 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 103.617621 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.025183 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 103.151125 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 56233.516484 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53233.516484 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 56247.023810 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53247.023810 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1868 # number of overall hits
-system.cpu.dcache.overall_miss_latency 10234500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 182 # number of overall misses
+system.cpu.dcache.overall_hits 1882 # number of overall hits
+system.cpu.dcache.overall_miss_latency 9449500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.081951 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 168 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 9688500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 8945500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 103.617621 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 103.151125 # Cycle average of tags in use
system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.dtb.write_hits 865 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.icache.ReadReq_accesses 7169 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 55706.484642 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52877.192982 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 55703.071672 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52873.684211 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 6876 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 16322000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 16321000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.040870 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 293 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 8 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 15070000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 15069000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.039754 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 285 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 7169 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 55706.484642 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52877.192982 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 55703.071672 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52873.684211 # average overall mshr miss latency
system.cpu.icache.demand_hits 6876 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 16322000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 16321000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.040870 # miss rate for demand accesses
system.cpu.icache.demand_misses 293 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 8 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 15070000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 15069000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.039754 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 285 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.063594 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 130.240724 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.063218 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 129.469682 # Average occupied blocks per context
system.cpu.icache.overall_accesses 7169 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 55706.484642 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52877.192982 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 55703.071672 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52873.684211 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 6876 # number of overall hits
-system.cpu.icache.overall_miss_latency 16322000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 16321000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.040870 # miss rate for overall accesses
system.cpu.icache.overall_misses 293 # number of overall misses
system.cpu.icache.overall_mshr_hits 8 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 15070000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 15069000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.039754 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 285 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 284 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 130.240724 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 129.469682 # Cycle average of tags in use
system.cpu.icache.total_refs 6876 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 48723 # Number of cycles cpu's stages were not processed
-system.cpu.ipc 0.102646 # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total 0.102646 # IPC: Total IPC of All Threads
+system.cpu.idleCycles 47410 # Number of cycles cpu's stages were not processed
+system.cpu.ipc 0.104851 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total 0.104851 # IPC: Total IPC of All Threads
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52075.342466 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52068.493151 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40013.698630 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 3801500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 3801000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2921000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 380 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52085.751979 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 52087.071240 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39947.229551 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 19740500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 19741000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.997368 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 379 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 15140000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997368 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 379 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52035.714286 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 728500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.002747 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.002646 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.005535 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 181.374052 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.005668 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 185.735123 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 453 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52084.070796 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 39957.964602 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 364 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 378 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 181.374052 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 185.735123 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 62389 # number of cpu cycles simulated
-system.cpu.runCycles 13666 # Number of cycles cpu stages are processed.
+system.cpu.numCycles 61077 # number of cpu cycles simulated
+system.cpu.runCycles 13667 # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
-system.cpu.stage-0.idleCycles 55203 # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.idleCycles 53891 # Number of cycles 0 instructions are processed.
system.cpu.stage-0.runCycles 7186 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-0.utilization 11.518056 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-1.idleCycles 55836 # Number of cycles 0 instructions are processed.
-system.cpu.stage-1.runCycles 6553 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-1.utilization 10.503454 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-2.idleCycles 55919 # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.utilization 11.765476 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-1.idleCycles 54525 # Number of cycles 0 instructions are processed.
+system.cpu.stage-1.runCycles 6552 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-1.utilization 10.727442 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-2.idleCycles 54607 # Number of cycles 0 instructions are processed.
system.cpu.stage-2.runCycles 6470 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-2.utilization 10.370418 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-3.idleCycles 60336 # Number of cycles 0 instructions are processed.
+system.cpu.stage-2.utilization 10.593186 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-3.idleCycles 59024 # Number of cycles 0 instructions are processed.
system.cpu.stage-3.runCycles 2053 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-3.utilization 3.290644 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-4.idleCycles 55985 # Number of cycles 0 instructions are processed.
+system.cpu.stage-3.utilization 3.361331 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-4.idleCycles 54673 # Number of cycles 0 instructions are processed.
system.cpu.stage-4.runCycles 6404 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-4.utilization 10.264630 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.threadCycles 62389 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.stage-4.utilization 10.485125 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.threadCycles 61077 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
-Redirecting stdout to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing/simerr
+Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jun 6 2010 03:04:38
-M5 revision ba1a0193c050 7448 default tip
-M5 started Jun 6 2010 03:09:06
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:52:04
M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 12497500 because target called exit()
+Exiting @ tick 12412500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 80384 # Simulator instruction rate (inst/s)
-host_mem_usage 204420 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
-host_tick_rate 156814646 # Simulator tick rate (ticks/s)
+host_inst_rate 44712 # Simulator instruction rate (inst/s)
+host_mem_usage 204968 # Number of bytes of host memory used
+host_seconds 0.14 # Real time elapsed on the host
+host_tick_rate 86758837 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6386 # Number of instructions simulated
sim_seconds 0.000012 # Number of seconds simulated
-sim_ticks 12497500 # Number of ticks simulated
+sim_ticks 12412500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 692 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 1820 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 680 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 1800 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 65 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 443 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 1337 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 2245 # Number of BP lookups
-system.cpu.BPredUnit.usedRAS 315 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.condPredicted 1320 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 2222 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 313 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 1051 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 119 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 117 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 12431 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 0.515083 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.305811 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 12265 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.522055 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.306636 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 9528 76.65% 76.65% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 1629 13.10% 89.75% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 491 3.95% 93.70% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 259 2.08% 95.78% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 156 1.25% 97.04% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 104 0.84% 97.88% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 96 0.77% 98.65% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 49 0.39% 99.04% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 119 0.96% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 9355 76.27% 76.27% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 1631 13.30% 89.57% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 489 3.99% 93.56% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 266 2.17% 95.73% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 144 1.17% 96.90% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 131 1.07% 97.97% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 95 0.77% 98.74% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 37 0.30% 99.05% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 117 0.95% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 12431 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 12265 # Number of insts commited each cycle
system.cpu.commit.COM:count 6403 # Number of instructions committed
system.cpu.commit.COM:loads 1185 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.branchMispredicts 369 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 4622 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 4518 # The number of squashed insts skipped by commit
system.cpu.committedInsts 6386 # Number of Instructions Simulated
system.cpu.committedInsts_total 6386 # Number of Instructions Simulated
-system.cpu.cpi 3.914187 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.914187 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 1782 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 34993.902439 # average ReadReq miss latency
+system.cpu.cpi 3.887567 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.887567 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 1765 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 35761.146497 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36257.425743 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1618 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 5739000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.092031 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 164 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 63 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_hits 1608 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 5614500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.088952 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 157 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 3662000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.056678 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.057224 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 35082.894737 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35729.885057 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 485 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 13331500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 380 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 293 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 3108500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 34971.751412 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35815.068493 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 511 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 12380000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.409249 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 354 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 281 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 2614500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 12.275862 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 12.178161 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 2647 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 35056.066176 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 36013.297872 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2103 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 19070500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.205516 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 544 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 356 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 6770500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.071024 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 188 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 2630 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 35214.285714 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 36071.839080 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 2119 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 17994500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.194297 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 511 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 6276500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.066160 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.026868 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 110.050975 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 2647 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 35056.066176 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 36013.297872 # average overall mshr miss latency
+system.cpu.dcache.occ_blocks::0 110.049713 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 2630 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 35214.285714 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 36071.839080 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2103 # number of overall hits
-system.cpu.dcache.overall_miss_latency 19070500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.205516 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 544 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 356 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 6770500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.071024 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 188 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 2119 # number of overall hits
+system.cpu.dcache.overall_miss_latency 17994500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.194297 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 511 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 337 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 6276500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.066160 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 174 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 110.050975 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2136 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 110.049713 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2119 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 1123 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BlockedCycles 1016 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 75 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 188 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 12474 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 8945 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 2313 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 900 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:BranchResolved 185 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 12350 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 8913 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 2277 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 884 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 209 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 50 # Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses 2948 # DTB accesses
+system.cpu.decode.DECODE:UnblockCycles 59 # Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses 2921 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_hits 2887 # DTB hits
+system.cpu.dtb.data_hits 2860 # DTB hits
system.cpu.dtb.data_misses 61 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 1865 # DTB read accesses
+system.cpu.dtb.read_accesses 1845 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 1829 # DTB read hits
+system.cpu.dtb.read_hits 1809 # DTB read hits
system.cpu.dtb.read_misses 36 # DTB read misses
-system.cpu.dtb.write_accesses 1083 # DTB write accesses
+system.cpu.dtb.write_accesses 1076 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 1058 # DTB write hits
+system.cpu.dtb.write_hits 1051 # DTB write hits
system.cpu.dtb.write_misses 25 # DTB write misses
-system.cpu.fetch.Branches 2245 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 1792 # Number of cache lines fetched
-system.cpu.fetch.Cycles 4238 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 269 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 13309 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 504 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.089814 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 1792 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 1007 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.532445 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 13331 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.998350 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.390717 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.Branches 2222 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 1774 # Number of cache lines fetched
+system.cpu.fetch.Cycles 4193 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 13186 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 503 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.089503 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 1774 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 993 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.531137 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 13149 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.002814 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.396074 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 10920 81.91% 81.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 245 1.84% 83.75% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 221 1.66% 85.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 185 1.39% 86.80% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 233 1.75% 88.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 164 1.23% 89.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 228 1.71% 91.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 133 1.00% 92.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 1002 7.52% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 10764 81.86% 81.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 240 1.83% 83.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 218 1.66% 85.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 183 1.39% 86.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 231 1.76% 88.49% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 163 1.24% 89.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 224 1.70% 91.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 130 0.99% 92.43% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 996 7.57% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 13331 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses 1792 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 35303.990610 # average ReadReq miss latency
+system.cpu.fetch.rateDist::total 13149 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 1774 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 35292.253521 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35283.387622 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1366 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 15039500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.237723 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_hits 1348 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 15034500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.240135 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 426 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 119 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_miss_latency 10832000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.171317 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate 0.173055 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 4.449511 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 4.390879 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 1792 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 35303.990610 # average overall miss latency
+system.cpu.icache.demand_accesses 1774 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 35292.253521 # average overall miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1366 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 15039500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.237723 # miss rate for demand accesses
+system.cpu.icache.demand_hits 1348 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 15034500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.240135 # miss rate for demand accesses
system.cpu.icache.demand_misses 426 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 119 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_miss_latency 10832000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.171317 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate 0.173055 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 307 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.077094 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 157.888110 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 1792 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 35303.990610 # average overall miss latency
+system.cpu.icache.occ_%::0 0.077067 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 157.832479 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 1774 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 35292.253521 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35283.387622 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1366 # number of overall hits
-system.cpu.icache.overall_miss_latency 15039500 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.237723 # miss rate for overall accesses
+system.cpu.icache.overall_hits 1348 # number of overall hits
+system.cpu.icache.overall_miss_latency 15034500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.240135 # miss rate for overall accesses
system.cpu.icache.overall_misses 426 # number of overall misses
system.cpu.icache.overall_mshr_hits 119 # number of overall MSHR hits
system.cpu.icache.overall_mshr_miss_latency 10832000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.171317 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_rate 0.173055 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 307 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 307 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 157.888110 # Cycle average of tags in use
-system.cpu.icache.total_refs 1366 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 157.832479 # Cycle average of tags in use
+system.cpu.icache.total_refs 1348 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 11665 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 1448 # Number of branches executed
-system.cpu.iew.EXEC:nop 83 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.362498 # Inst execution rate
-system.cpu.iew.EXEC:refs 2956 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 1085 # Number of stores executed
+system.cpu.idleCycles 11677 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 1435 # Number of branches executed
+system.cpu.iew.EXEC:nop 82 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.361798 # Inst execution rate
+system.cpu.iew.EXEC:refs 2929 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 1078 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 6049 # num instructions consuming a value
-system.cpu.iew.WB:count 8759 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.745247 # average fanout of values written-back
+system.cpu.iew.WB:consumers 6007 # num instructions consuming a value
+system.cpu.iew.WB:count 8682 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.744798 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 4508 # num instructions producing a value
-system.cpu.iew.WB:rate 0.350416 # insts written-back per cycle
-system.cpu.iew.WB:sent 8858 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 427 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 73 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2269 # Number of dispatched load instructions
+system.cpu.iew.WB:producers 4474 # num instructions producing a value
+system.cpu.iew.WB:rate 0.349714 # insts written-back per cycle
+system.cpu.iew.WB:sent 8783 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 428 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 63 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 2242 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 191 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1271 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 11059 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 1871 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 304 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 9061 # Number of executed instructions
+system.cpu.iew.iewDispSquashedInsts 193 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 1259 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 10955 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 1851 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 291 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 8982 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 900 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking
+system.cpu.iew.iewSquashCycles 884 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread.0.forwLoads 46 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.forwLoads 43 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 64 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.memOrderViolation 63 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1084 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 406 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 64 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 302 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.lsq.thread.0.squashedLoads 1057 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 394 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 63 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 303 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.255481 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.255481 # IPC: Total IPC of All Threads
+system.cpu.ipc 0.257230 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.257230 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu 6287 67.13% 67.15% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.16% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.16% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.19% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.19% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.19% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.19% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.19% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.19% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 1968 21.01% 88.20% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 1105 11.80% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 6230 67.18% 67.21% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.01% 67.22% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 67.22% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 67.24% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 1943 20.95% 88.19% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 1095 11.81% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 9365 # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt 92 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.009824 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 9273 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 91 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.009813 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 1 1.09% 1.09% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 56 60.87% 61.96% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite 35 38.04% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 1 1.10% 1.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 1.10% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 55 60.44% 61.54% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 35 38.46% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 13331 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 0.702498 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.304735 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples 13149 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.705225 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.302669 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 9142 68.58% 68.58% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 1697 12.73% 81.31% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 1062 7.97% 89.27% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 730 5.48% 94.75% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 359 2.69% 97.44% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 188 1.41% 98.85% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 105 0.79% 99.64% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 36 0.27% 99.91% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 8989 68.36% 68.36% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 1668 12.69% 81.05% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 1105 8.40% 89.45% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 696 5.29% 94.74% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 356 2.71% 97.45% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 185 1.41% 98.86% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 104 0.79% 99.65% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 34 0.26% 99.91% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 13331 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 0.374660 # Inst issue rate
-system.cpu.iq.iqInstsAdded 10951 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 9365 # Number of instructions issued
+system.cpu.iq.ISSUE:issued_per_cycle::total 13149 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.373520 # Inst issue rate
+system.cpu.iq.iqInstsAdded 10848 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 9273 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 4181 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 4076 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 42 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2504 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 2476 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 1827 # ITB accesses
+system.cpu.itb.fetch_accesses 1808 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_hits 1792 # ITB hits
-system.cpu.itb.fetch_misses 35 # ITB misses
+system.cpu.itb.fetch_hits 1774 # ITB hits
+system.cpu.itb.fetch_misses 34 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34465.753425 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31376.712329 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 2516000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34506.849315 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31424.657534 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 2519000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2290500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 2294000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 408 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34418.918919 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31239.557740 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 34420.147420 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31243.243243 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 14008500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 14009000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.997549 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 407 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 12714500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 12716000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997549 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 407 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31035.714286 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 434500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.002545 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.002457 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 481 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34426.041667 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31260.416667 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34433.333333 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31270.833333 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 16524500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 16528000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.997921 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 480 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 15005000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 15010000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.997921 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 480 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.006535 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 214.135921 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.006704 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 219.690126 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 481 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34426.041667 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31260.416667 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34433.333333 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31270.833333 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 1 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 16524500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 16528000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.997921 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 480 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 15005000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 15010000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.997921 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 480 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 393 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 407 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 214.135921 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 219.690126 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads.
+system.cpu.memDep0.conflictingLoads 34 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 26 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 2269 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1271 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 24996 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 340 # Number of cycles rename is blocking
+system.cpu.memDep0.insertedLoads 2242 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1259 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 24826 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 346 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 4583 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IQFullEvents 9 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 9098 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 255 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 15174 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 12043 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8961 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 2203 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 900 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 292 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4378 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 498 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:IQFullEvents 8 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 9063 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 234 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 15033 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 11933 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 8883 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 2180 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 884 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 270 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 4300 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 406 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 28 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 750 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts 694 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed
-system.cpu.timesIdled 240 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.timesIdled 239 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Feb 24 2010 23:12:40
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 02:20:02
-M5 executing on SC2B0619
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/simple-timing
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:59:22
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 33777000 because target called exit()
+Exiting @ tick 33007000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 605866 # Simulator instruction rate (inst/s)
-host_mem_usage 190120 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 3109075847 # Simulator tick rate (ticks/s)
+host_inst_rate 332796 # Simulator instruction rate (inst/s)
+host_mem_usage 204128 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+host_tick_rate 1691799077 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 6404 # Number of instructions simulated
-sim_seconds 0.000034 # Number of seconds simulated
-sim_ticks 33777000 # Number of ticks simulated
+sim_seconds 0.000033 # Number of seconds simulated
+sim_ticks 33007000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 778 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 4872000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.100578 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 87 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 4611000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.100578 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 87 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_hits 792 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 4088000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.084393 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 3869000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks.
system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1868 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 10192000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.088780 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 182 # number of demand (read+write) misses
+system.cpu.dcache.demand_hits 1882 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 9408000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.081951 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 168 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 9646000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.088780 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 182 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 8904000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.025418 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 104.111261 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.025313 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 103.680615 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1868 # number of overall hits
-system.cpu.dcache.overall_miss_latency 10192000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.088780 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 182 # number of overall misses
+system.cpu.dcache.overall_hits 1882 # number of overall hits
+system.cpu.dcache.overall_miss_latency 9408000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.081951 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 168 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 9646000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.088780 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 182 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 8904000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 104.111261 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 103.680615 # Cycle average of tags in use
system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.062817 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 128.649737 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.062443 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 127.883393 # Average occupied blocks per context
system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366 # average overall mshr miss latency
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 128.649737 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 127.883393 # Cycle average of tags in use
system.cpu.icache.total_refs 6136 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_miss_latency 14920000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997326 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 373 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 728000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 560000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.002786 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.005491 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 179.928092 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.005626 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 184.342479 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 447 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 179.928092 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 184.342479 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 67554 # number of cpu cycles simulated
+system.cpu.numCycles 66014 # number of cpu cycles simulated
system.cpu.num_insts 6404 # Number of instructions executed
system.cpu.num_refs 2060 # Number of memory references
system.cpu.workload.PROG:num_syscalls 17 # Number of system calls
-Redirecting stdout to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing/simerr
+Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jun 6 2010 03:04:38
-M5 revision ba1a0193c050 7448 default tip
-M5 started Jun 6 2010 03:04:41
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:52:05
M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/o3-timing
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 7285000 because target called exit()
+Exiting @ tick 7300000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 8638 # Simulator instruction rate (inst/s)
-host_mem_usage 203416 # Number of bytes of host memory used
-host_seconds 0.28 # Real time elapsed on the host
-host_tick_rate 26335958 # Simulator tick rate (ticks/s)
+host_inst_rate 34398 # Simulator instruction rate (inst/s)
+host_mem_usage 203876 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
+host_tick_rate 104794717 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2387 # Number of instructions simulated
sim_seconds 0.000007 # Number of seconds simulated
-sim_ticks 7285000 # Number of ticks simulated
+sim_ticks 7300000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 190 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 674 # Number of BTB lookups
+system.cpu.BPredUnit.BTBLookups 683 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 35 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 220 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 463 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 916 # Number of BP lookups
-system.cpu.BPredUnit.usedRAS 178 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.condPredicted 476 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 926 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 179 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 396 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 39 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 35 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 6323 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 0.407402 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.198077 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 6328 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.407080 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.186255 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 5366 84.86% 84.86% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 262 4.14% 89.01% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 338 5.35% 94.35% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 131 2.07% 96.43% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 72 1.14% 97.56% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 64 1.01% 98.58% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 32 0.51% 99.08% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 19 0.30% 99.38% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 39 0.62% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 5362 84.73% 84.73% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 264 4.17% 88.91% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 341 5.39% 94.30% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 139 2.20% 96.49% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 71 1.12% 97.61% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 66 1.04% 98.66% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 31 0.49% 99.15% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 19 0.30% 99.45% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 35 0.55% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 6323 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 6328 # Number of insts commited each cycle
system.cpu.commit.COM:count 2576 # Number of instructions committed
system.cpu.commit.COM:loads 415 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.branchMispredicts 143 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 1946 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 1998 # The number of squashed insts skipped by commit
system.cpu.committedInsts 2387 # Number of Instructions Simulated
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
-system.cpu.cpi 6.104315 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 6.104315 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 595 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 35822.222222 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35663.934426 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 505 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 3224000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.151261 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 90 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 29 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 2175500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.102521 # mshr miss rate for ReadReq accesses
+system.cpu.cpi 6.116883 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 6.116883 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 599 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 35045 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35696.721311 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 499 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 3504500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.166945 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 100 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 39 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 2177500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.101836 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 61 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 37219.626168 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 37702.702703 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 187 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 3982500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.363946 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 107 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 70 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 1395000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.125850 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 38819.444444 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36145.833333 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 222 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 2795000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.244898 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 72 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 48 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 867500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.081633 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 24 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 8.600000 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 8.482353 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 889 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 36581.218274 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 692 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 7206500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.221597 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 197 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 99 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 3570500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.110236 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 98 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 893 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 36625 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35823.529412 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 721 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 6299500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.192609 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 172 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 87 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 3045000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.095185 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 85 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.011290 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 46.245716 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 889 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 36581.218274 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 36433.673469 # average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.011350 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 46.490005 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 893 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 36625 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35823.529412 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 692 # number of overall hits
-system.cpu.dcache.overall_miss_latency 7206500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.221597 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 197 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 99 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 3570500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.110236 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 98 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 721 # number of overall hits
+system.cpu.dcache.overall_miss_latency 6299500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.192609 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 172 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 87 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 3045000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.095185 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 85 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 46.245716 # Cycle average of tags in use
-system.cpu.dcache.total_refs 731 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 46.490005 # Cycle average of tags in use
+system.cpu.dcache.total_refs 721 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 169 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BlockedCycles 226 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 79 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 142 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 5018 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 5179 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 974 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 367 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:BranchResolved 136 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 5050 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 5122 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 978 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 373 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 284 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses 1010 # DTB accesses
+system.cpu.decode.DECODE:UnblockCycles 2 # Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses 1016 # DTB accesses
system.cpu.dtb.data_acv 1 # DTB access violations
-system.cpu.dtb.data_hits 979 # DTB hits
-system.cpu.dtb.data_misses 31 # DTB misses
+system.cpu.dtb.data_hits 978 # DTB hits
+system.cpu.dtb.data_misses 38 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 638 # DTB read accesses
+system.cpu.dtb.read_accesses 648 # DTB read accesses
system.cpu.dtb.read_acv 1 # DTB read access violations
-system.cpu.dtb.read_hits 623 # DTB read hits
-system.cpu.dtb.read_misses 15 # DTB read misses
-system.cpu.dtb.write_accesses 372 # DTB write accesses
+system.cpu.dtb.read_hits 627 # DTB read hits
+system.cpu.dtb.read_misses 21 # DTB read misses
+system.cpu.dtb.write_accesses 368 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 356 # DTB write hits
-system.cpu.dtb.write_misses 16 # DTB write misses
-system.cpu.fetch.Branches 916 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 789 # Number of cache lines fetched
-system.cpu.fetch.Cycles 1801 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 119 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 5736 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 250 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.062865 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 789 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 368 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.393659 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 6690 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.857399 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.271719 # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.write_hits 351 # DTB write hits
+system.cpu.dtb.write_misses 17 # DTB write misses
+system.cpu.fetch.Branches 926 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 782 # Number of cache lines fetched
+system.cpu.fetch.Cycles 1799 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 117 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 5752 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 249 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.063420 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 782 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 369 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 0.393946 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 6701 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.858379 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.271912 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 5707 85.31% 85.31% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 48 0.72% 86.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 101 1.51% 87.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 74 1.11% 88.64% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 123 1.84% 90.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 57 0.85% 91.33% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 51 0.76% 92.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 51 0.76% 92.86% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 478 7.14% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 5713 85.26% 85.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 53 0.79% 86.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 100 1.49% 87.54% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 71 1.06% 88.60% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 125 1.87% 90.46% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 52 0.78% 91.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 55 0.82% 92.06% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 60 0.90% 92.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 472 7.04% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 6690 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses 789 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 36081.196581 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35312.154696 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 555 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 8443000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.296578 # miss rate for ReadReq accesses
+system.cpu.fetch.rateDist::total 6701 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 782 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 36074.786325 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 35303.867403 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 548 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 8441500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.299233 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 234 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 53 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 6391500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.229404 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_latency 6390000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.231458 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 181 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 3.066298 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 3.027624 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 789 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 36081.196581 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35312.154696 # average overall mshr miss latency
-system.cpu.icache.demand_hits 555 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 8443000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.296578 # miss rate for demand accesses
+system.cpu.icache.demand_accesses 782 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 36074.786325 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 35303.867403 # average overall mshr miss latency
+system.cpu.icache.demand_hits 548 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 8441500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.299233 # miss rate for demand accesses
system.cpu.icache.demand_misses 234 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 53 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 6391500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.229404 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_latency 6390000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.231458 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 181 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.043805 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 89.711886 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 789 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 36081.196581 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35312.154696 # average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.044097 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 90.310423 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 782 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 36074.786325 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 35303.867403 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 555 # number of overall hits
-system.cpu.icache.overall_miss_latency 8443000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.296578 # miss rate for overall accesses
+system.cpu.icache.overall_hits 548 # number of overall hits
+system.cpu.icache.overall_miss_latency 8441500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.299233 # miss rate for overall accesses
system.cpu.icache.overall_misses 234 # number of overall misses
system.cpu.icache.overall_mshr_hits 53 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 6391500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.229404 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_latency 6390000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.231458 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 181 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 181 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 89.711886 # Cycle average of tags in use
-system.cpu.icache.total_refs 555 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 90.310423 # Cycle average of tags in use
+system.cpu.icache.total_refs 548 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 7881 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 607 # Number of branches executed
-system.cpu.iew.EXEC:nop 310 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.241370 # Inst execution rate
-system.cpu.iew.EXEC:refs 1013 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 372 # Number of stores executed
+system.cpu.idleCycles 7900 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 601 # Number of branches executed
+system.cpu.iew.EXEC:nop 306 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.241079 # Inst execution rate
+system.cpu.iew.EXEC:refs 1019 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 368 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 1984 # num instructions consuming a value
-system.cpu.iew.WB:count 3409 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.798891 # average fanout of values written-back
+system.cpu.iew.WB:consumers 1981 # num instructions consuming a value
+system.cpu.iew.WB:count 3402 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.795558 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 1585 # num instructions producing a value
-system.cpu.iew.WB:rate 0.233958 # insts written-back per cycle
+system.cpu.iew.WB:producers 1576 # num instructions producing a value
+system.cpu.iew.WB:rate 0.232998 # insts written-back per cycle
system.cpu.iew.WB:sent 3452 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 164 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 787 # Number of dispatched load instructions
+system.cpu.iew.iewBlockCycles 55 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 795 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 57 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 432 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 4536 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 641 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 117 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 3517 # Number of executed instructions
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewDispSquashedInsts 68 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 435 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 4588 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 651 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 3520 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
+system.cpu.iew.iewSquashCycles 373 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 28 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 14 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.memOrderViolation 13 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 372 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 138 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 110 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.163819 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.163819 # IPC: Total IPC of All Threads
+system.cpu.iew.lsq.thread.0.squashedLoads 380 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 141 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 109 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 55 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc 0.163482 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.163482 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu 2590 71.27% 71.27% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.30% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.30% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.30% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.30% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.30% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.30% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.30% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.30% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 666 18.33% 89.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 377 10.37% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 2582 71.11% 71.11% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.14% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 675 18.59% 89.73% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 373 10.27% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 3634 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::total 3631 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.009631 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_rate 0.009639 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntAlu 1 2.86% 2.86% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 2.86% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 22 62.86% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 6690 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 0.543199 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.215587 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples 6701 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.541859 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.220931 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 5134 76.74% 76.74% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 621 9.28% 86.02% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 357 5.34% 91.36% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 240 3.59% 94.95% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 184 2.75% 97.70% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 102 1.52% 99.22% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 36 0.54% 99.76% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 11 0.16% 99.93% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::8 5 0.07% 100.00% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 5144 76.76% 76.76% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 631 9.42% 86.18% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 352 5.25% 91.43% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 241 3.60% 95.03% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 180 2.69% 97.72% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 94 1.40% 99.12% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 38 0.57% 99.69% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 13 0.19% 99.88% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::8 8 0.12% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 6690 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 0.249399 # Inst issue rate
-system.cpu.iq.iqInstsAdded 4220 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 3634 # Number of instructions issued
+system.cpu.iq.ISSUE:issued_per_cycle::total 6701 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.248682 # Inst issue rate
+system.cpu.iq.iqInstsAdded 4276 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 3631 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 1660 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 33 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 1710 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 874 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 972 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 818 # ITB accesses
+system.cpu.itb.fetch_accesses 811 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_hits 789 # ITB hits
+system.cpu.itb.fetch_hits 782 # ITB hits
system.cpu.itb.fetch_misses 29 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 24 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 242 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34324.380165 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31130.165289 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_miss_latency 8306500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_avg_miss_latency 34322.314050 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31132.231405 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_miss_latency 8306000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 242 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 7533500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 7534000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 242 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34250 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31107.142857 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 479500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 435500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 266 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34349.624060 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34347.744361 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31165.413534 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 9137000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 9136500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 266 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 8289500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 8290000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 266 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.003416 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 111.924793 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.003651 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 119.628373 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 266 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34349.624060 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31163.533835 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34347.744361 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31165.413534 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 0 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 9137000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 9136500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 266 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 8289500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 8290000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 266 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 228 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 242 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 111.924793 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 119.628373 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.memDep0.conflictingLoads 12 # Number of conflicting loads.
+system.cpu.memDep0.conflictingLoads 16 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 16 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 787 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 432 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 14571 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 7 # Number of cycles rename is blocking
+system.cpu.memDep0.insertedLoads 795 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 435 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 14601 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 63 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 5259 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 8 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 5438 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 4848 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 3462 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 895 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 367 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 16 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 1694 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:IQFullEvents 3 # Number of times rename has blocked due to IQ full
+system.cpu.rename.RENAME:IdleCycles 5203 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 3 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 5514 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 4876 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 3481 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 901 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 373 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 15 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 1713 # Number of HB maps that are undone due to squashing
system.cpu.rename.RENAME:serializeStallCycles 146 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 80 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts 78 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed
-system.cpu.timesIdled 153 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.timesIdled 152 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Feb 24 2010 23:12:40
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:11:06
-M5 executing on SC2B0619
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-timing
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:52:05
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
-Exiting @ tick 17374000 because target called exit()
+Exiting @ tick 16769000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 400715 # Simulator instruction rate (inst/s)
-host_mem_usage 189300 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 2582342449 # Simulator tick rate (ticks/s)
+host_inst_rate 97740 # Simulator instruction rate (inst/s)
+host_mem_usage 203308 # Number of bytes of host memory used
+host_seconds 0.03 # Real time elapsed on the host
+host_tick_rate 629585132 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2577 # Number of instructions simulated
sim_seconds 0.000017 # Number of seconds simulated
-sim_ticks 17374000 # Number of ticks simulated
+sim_ticks 16769000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 256 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 2128000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.129252 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 38 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 2014000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.129252 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 38 # number of WriteReq MSHR misses
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+system.cpu.dcache.WriteReq_mshr_miss_latency 1431000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.091837 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 616 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 5208000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.131171 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 93 # number of demand (read+write) misses
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+system.cpu.dcache.demand_miss_latency 4592000 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 4929000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.131171 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 93 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 4346000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.115656 # mshr miss rate for demand accesses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.011615 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 47.575114 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 616 # number of overall hits
-system.cpu.dcache.overall_miss_latency 5208000 # number of overall miss cycles
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-system.cpu.dcache.overall_misses 93 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 4929000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.131171 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 93 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 47.575114 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 47.418751 # Cycle average of tags in use
system.cpu.dcache.total_refs 627 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.039276 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 80.437325 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.039064 # Average percentage of cache occupancy
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system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 80.437325 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 80.003762 # Cycle average of tags in use
system.cpu.icache.total_refs 2423 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_miss_latency 8720000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 11 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 572000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 11 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 440000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 11 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.003139 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 102.857609 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.003268 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 107.101205 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 245 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 207 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 102.857609 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 107.101205 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 34748 # number of cpu cycles simulated
+system.cpu.numCycles 33538 # number of cpu cycles simulated
system.cpu.num_insts 2577 # Number of instructions executed
system.cpu.num_refs 717 # Number of memory references
system.cpu.workload.PROG:num_syscalls 4 # Number of system calls
+Redirecting stdout to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing/simout
+Redirecting stderr to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jun 25 2010 15:39:33
-M5 revision 93b1ca421839+ 7482+ default qtip tip update_regr
-M5 started Jun 25 2010 15:39:34
-M5 executing on zooks
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing
+M5 compiled Aug 26 2010 12:56:28
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 12:56:32
+M5 executing on zizzer
+command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 29206500 because target called exit()
+Exiting @ tick 28659500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 22033 # Simulator instruction rate (inst/s)
-host_mem_usage 154168 # Number of bytes of host memory used
-host_seconds 0.26 # Real time elapsed on the host
-host_tick_rate 110232758 # Simulator tick rate (ticks/s)
+host_inst_rate 16536 # Simulator instruction rate (inst/s)
+host_mem_usage 205460 # Number of bytes of host memory used
+host_seconds 0.35 # Real time elapsed on the host
+host_tick_rate 81268272 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5827 # Number of instructions simulated
sim_seconds 0.000029 # Number of seconds simulated
-sim_ticks 29206500 # Number of ticks simulated
+sim_ticks 28659500 # Number of ticks simulated
system.cpu.AGEN-Unit.agens 2090 # Number of Address Generations
system.cpu.Branch-Predictor.BTBHitPct 15.000000 # BTB Hit Percentage
system.cpu.Branch-Predictor.BTBHits 24 # Number of BTB hits
system.cpu.Execution-Unit.predictedTakenIncorrect 37 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.Mult-Div-Unit.divides 1 # Number of Divide Operations Executed
system.cpu.Mult-Div-Unit.multiplies 3 # Number of Multipy Operations Executed
-system.cpu.RegFile-Manager.regFileAccesses 10682 # Number of Total Accesses (Read+Write) to the Register File
-system.cpu.RegFile-Manager.regFileReads 7272 # Number of Reads from Register File
+system.cpu.RegFile-Manager.regFileAccesses 10688 # Number of Total Accesses (Read+Write) to the Register File
+system.cpu.RegFile-Manager.regFileReads 7278 # Number of Reads from Register File
system.cpu.RegFile-Manager.regFileWrites 3410 # Number of Writes to Register File
-system.cpu.RegFile-Manager.regForwards 31 # Number of Registers Read Through Forwarding Logic
-system.cpu.activity 20.277673 # Percentage of cycles cpu is active
+system.cpu.RegFile-Manager.regForwards 25 # Number of Registers Read Through Forwarding Logic
+system.cpu.activity 20.706560 # Percentage of cycles cpu is active
system.cpu.comBranches 916 # Number of Branches instructions committed
system.cpu.comFloats 0 # Number of Floating Point instructions committed
system.cpu.comInts 2155 # Number of Integer instructions committed
system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread)
system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total)
system.cpu.contextSwitches 1 # Number of context switches
-system.cpu.cpi 10.024713 # CPI: Cycles Per Instruction (Per-Thread)
-system.cpu.cpi_total 10.024713 # CPI: Total CPI of All Threads
+system.cpu.cpi 9.836966 # CPI: Cycles Per Instruction (Per-Thread)
+system.cpu.cpi_total 9.836966 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 56229.885057 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53229.885057 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 56265.625000 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53265.625000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 861 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 3601000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.069189 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses
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-system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 56254.901961 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53254.901961 # average WriteReq mshr miss latency
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses
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-system.cpu.dcache.demand_avg_mshr_miss_latency 53245.033113 # average overall mshr miss latency
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-system.cpu.dcache.demand_miss_latency 8493000 # number of demand (read+write) miss cycles
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+system.cpu.dcache.demand_avg_miss_latency 56239.130435 # average overall miss latency
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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-system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses
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+system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 56245.033113 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53245.033113 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 56239.130435 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 53239.130435 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1938 # number of overall hits
-system.cpu.dcache.overall_miss_latency 8493000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.072283 # miss rate for overall accesses
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+system.cpu.dcache.overall_miss_rate 0.066060 # miss rate for overall accesses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 8040000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072283 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 7347000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 88.491296 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 88.199028 # Cycle average of tags in use
system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.icache.ReadReq_accesses 5874 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 55801.980198 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52801.980198 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 5571 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 16908000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.051583 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_accesses 5869 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 55795.379538 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 52795.379538 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 5566 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 16906000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.051627 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 15999000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.051583 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_latency 15997000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.051627 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 18.386139 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 18.369637 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 5874 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 55801.980198 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52801.980198 # average overall mshr miss latency
-system.cpu.icache.demand_hits 5571 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 16908000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.051583 # miss rate for demand accesses
+system.cpu.icache.demand_accesses 5869 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 55795.379538 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 52795.379538 # average overall mshr miss latency
+system.cpu.icache.demand_hits 5566 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 16906000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.051627 # miss rate for demand accesses
system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 15999000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.051583 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_latency 15997000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.051627 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.066095 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 135.362853 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 5874 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 55801.980198 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52801.980198 # average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.065748 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 134.651831 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 5869 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 55795.379538 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 52795.379538 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 5571 # number of overall hits
-system.cpu.icache.overall_miss_latency 16908000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.051583 # miss rate for overall accesses
+system.cpu.icache.overall_hits 5566 # number of overall hits
+system.cpu.icache.overall_miss_latency 16906000 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.051627 # miss rate for overall accesses
system.cpu.icache.overall_misses 303 # number of overall misses
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 15999000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.051583 # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_miss_latency 15997000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.051627 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 13 # number of replacements
system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 135.362853 # Cycle average of tags in use
-system.cpu.icache.total_refs 5571 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 134.651831 # Cycle average of tags in use
+system.cpu.icache.total_refs 5566 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 46569 # Number of cycles cpu's stages were not processed
-system.cpu.ipc 0.099753 # IPC: Instructions Per Cycle (Per-Thread)
-system.cpu.ipc_total 0.099753 # IPC: Total IPC of All Threads
+system.cpu.idleCycles 45451 # Number of cycles cpu's stages were not processed
+system.cpu.ipc 0.101657 # IPC: Instructions Per Cycle (Per-Thread)
+system.cpu.ipc_total 0.101657 # IPC: Total IPC of All Threads
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52264.705882 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 52254.901961 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40098.039216 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 2665500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 2665000 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2045000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 52091.494845 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 52086.340206 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40048.969072 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 20211500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 20209500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 15539000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 13 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52192.307692 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40153.846154 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 678500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 13 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 522000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 13 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.005333 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 52111.617312 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 52105.922551 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 40054.669704 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 22877000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 22874500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.005708 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 187.032260 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.005821 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 190.726729 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 52111.617312 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 52105.922551 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40054.669704 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 22877000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 22874500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 439 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 375 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 187.032260 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 190.726729 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.numCycles 58414 # number of cpu cycles simulated
-system.cpu.runCycles 11845 # Number of cycles cpu stages are processed.
+system.cpu.numCycles 57320 # number of cpu cycles simulated
+system.cpu.runCycles 11869 # Number of cycles cpu stages are processed.
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
-system.cpu.stage-0.idleCycles 52540 # Number of cycles 0 instructions are processed.
-system.cpu.stage-0.runCycles 5874 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-0.utilization 10.055809 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-1.idleCycles 52586 # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.idleCycles 51451 # Number of cycles 0 instructions are processed.
+system.cpu.stage-0.runCycles 5869 # Number of cycles 1+ instructions are processed.
+system.cpu.stage-0.utilization 10.239009 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-1.idleCycles 51492 # Number of cycles 0 instructions are processed.
system.cpu.stage-1.runCycles 5828 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-1.utilization 9.977060 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-2.idleCycles 52582 # Number of cycles 0 instructions are processed.
+system.cpu.stage-1.utilization 10.167481 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-2.idleCycles 51488 # Number of cycles 0 instructions are processed.
system.cpu.stage-2.runCycles 5832 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-2.utilization 9.983908 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-3.idleCycles 56324 # Number of cycles 0 instructions are processed.
+system.cpu.stage-2.utilization 10.174459 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-3.idleCycles 55230 # Number of cycles 0 instructions are processed.
system.cpu.stage-3.runCycles 2090 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-3.utilization 3.577909 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.stage-4.idleCycles 52587 # Number of cycles 0 instructions are processed.
+system.cpu.stage-3.utilization 3.646197 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.stage-4.idleCycles 51493 # Number of cycles 0 instructions are processed.
system.cpu.stage-4.runCycles 5827 # Number of cycles 1+ instructions are processed.
-system.cpu.stage-4.utilization 9.975348 # Percentage of cycles stage was utilized (processing insts).
-system.cpu.threadCycles 58414 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
+system.cpu.stage-4.utilization 10.165736 # Percentage of cycles stage was utilized (processing insts).
+system.cpu.threadCycles 57320 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
---------- End Simulation Statistics ----------
-Redirecting stdout to build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing/simout
-Redirecting stderr to build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing/simerr
+Redirecting stdout to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing/simout
+Redirecting stderr to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jun 6 2010 03:55:57
-M5 revision ba1a0193c050 7448 default tip
-M5 started Jun 6 2010 03:56:00
+M5 compiled Aug 26 2010 12:56:28
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 12:56:32
M5 executing on zizzer
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/o3-timing
+command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 14021500 because target called exit()
+Exiting @ tick 14010500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 59393 # Simulator instruction rate (inst/s)
-host_mem_usage 205240 # Number of bytes of host memory used
+host_inst_rate 60755 # Simulator instruction rate (inst/s)
+host_mem_usage 205968 # Number of bytes of host memory used
host_seconds 0.09 # Real time elapsed on the host
-host_tick_rate 160627549 # Simulator tick rate (ticks/s)
+host_tick_rate 164238154 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5169 # Number of instructions simulated
sim_seconds 0.000014 # Number of seconds simulated
-sim_ticks 14021500 # Number of ticks simulated
+sim_ticks 14010500 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 546 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 1900 # Number of BTB lookups
+system.cpu.BPredUnit.BTBLookups 1895 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 747 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 1589 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 2405 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 1584 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 2400 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 400 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 916 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 69 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 67 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 14488 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 0.402126 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.127822 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 14458 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.402960 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.127371 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 11934 82.37% 82.37% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 1210 8.35% 90.72% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 523 3.61% 94.33% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 292 2.02% 96.35% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 294 2.03% 98.38% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 67 0.46% 98.84% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 11898 82.29% 82.29% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 1218 8.42% 90.72% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 521 3.60% 94.32% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 292 2.02% 96.34% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 296 2.05% 98.39% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 65 0.45% 98.84% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::6 62 0.43% 99.27% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 37 0.26% 99.52% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 69 0.48% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 39 0.27% 99.54% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 67 0.46% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 14488 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 14458 # Number of insts commited each cycle
system.cpu.commit.COM:count 5826 # Number of instructions committed
system.cpu.commit.COM:loads 1164 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.branchMispredicts 616 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 5972 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 5944 # The number of squashed insts skipped by commit
system.cpu.committedInsts 5169 # Number of Instructions Simulated
system.cpu.committedInsts_total 5169 # Number of Instructions Simulated
-system.cpu.cpi 5.425421 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 5.425421 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 2310 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 34156.716418 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36032.967033 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 2176 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4577000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.058009 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 134 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 43 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 3279000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.039394 # mshr miss rate for ReadReq accesses
+system.cpu.cpi 5.421165 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 5.421165 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 2307 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 34750 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36021.978022 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 2179 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 4448000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.055483 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 128 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 37 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 3278000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate 0.039445 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 91 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 27570.707071 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36046.875000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 628 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 8188500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.321081 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 297 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 233 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 2307000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 27330.827068 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36160 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 659 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 7270000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.287568 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 266 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 216 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 1808000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.054054 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 50 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 20.148936 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 20.127660 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 3235 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 29618.329466 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 36038.709677 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2804 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 12765500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.133230 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 431 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 276 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 5586000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.047913 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 155 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_accesses 3232 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 29741.116751 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 36070.921986 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 2838 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 11718000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.121906 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 394 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 253 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 5086000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.043626 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.022304 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 91.357241 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 3235 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 29618.329466 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 36038.709677 # average overall mshr miss latency
+system.cpu.dcache.occ_%::0 0.022299 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 91.337822 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 3232 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 29741.116751 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 36070.921986 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2804 # number of overall hits
-system.cpu.dcache.overall_miss_latency 12765500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.133230 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 431 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 276 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 5586000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.047913 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 2838 # number of overall hits
+system.cpu.dcache.overall_miss_latency 11718000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.121906 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 394 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 253 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 5086000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.043626 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 91.357241 # Cycle average of tags in use
-system.cpu.dcache.total_refs 2841 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 91.337822 # Cycle average of tags in use
+system.cpu.dcache.total_refs 2838 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 521 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BlockedCycles 514 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 138 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 138 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 14337 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 10064 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 3903 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 1073 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:DecodedInsts 14307 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 10045 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 3899 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 1070 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 267 # Number of squashed instructions handled by decode
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.fetch.Branches 2405 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 2216 # Number of cache lines fetched
-system.cpu.fetch.Cycles 6303 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 358 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 15547 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 763 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.085758 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 2216 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Branches 2400 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 2213 # Number of cache lines fetched
+system.cpu.fetch.Cycles 6297 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 357 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 15518 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 762 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.085647 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 2213 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 946 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.554379 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 15561 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.999100 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.261901 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rate 0.553779 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 15528 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.999356 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.261429 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 11491 73.84% 73.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1812 11.64% 85.49% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 195 1.25% 86.74% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 11461 73.81% 73.81% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1813 11.68% 85.48% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 195 1.26% 86.74% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 140 0.90% 87.64% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 320 2.06% 89.70% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 114 0.73% 90.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 289 1.86% 92.29% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 259 1.66% 93.95% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 941 6.05% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 114 0.73% 90.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 288 1.85% 92.29% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 259 1.67% 93.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 938 6.04% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 15561 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses 2216 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 35687.203791 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34908.814590 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 1794 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 15060000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.190433 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 422 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 93 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 11485000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.148466 # mshr miss rate for ReadReq accesses
+system.cpu.fetch.rateDist::total 15528 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 2213 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 35692.399050 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34907.294833 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 1792 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 15026500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.190239 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 421 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 92 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 11484500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.148667 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 329 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 5.452888 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 5.446809 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 2216 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 35687.203791 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34908.814590 # average overall mshr miss latency
-system.cpu.icache.demand_hits 1794 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 15060000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.190433 # miss rate for demand accesses
-system.cpu.icache.demand_misses 422 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 93 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 11485000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.148466 # mshr miss rate for demand accesses
+system.cpu.icache.demand_accesses 2213 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 35692.399050 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34907.294833 # average overall mshr miss latency
+system.cpu.icache.demand_hits 1792 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 15026500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.190239 # miss rate for demand accesses
+system.cpu.icache.demand_misses 421 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 92 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 11484500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.148667 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 329 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.076241 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 156.140617 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 2216 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 35687.203791 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34908.814590 # average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.076220 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 156.098402 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 2213 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 35692.399050 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34907.294833 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 1794 # number of overall hits
-system.cpu.icache.overall_miss_latency 15060000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.190433 # miss rate for overall accesses
-system.cpu.icache.overall_misses 422 # number of overall misses
-system.cpu.icache.overall_mshr_hits 93 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 11485000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.148466 # mshr miss rate for overall accesses
+system.cpu.icache.overall_hits 1792 # number of overall hits
+system.cpu.icache.overall_miss_latency 15026500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.190239 # miss rate for overall accesses
+system.cpu.icache.overall_misses 421 # number of overall misses
+system.cpu.icache.overall_mshr_hits 92 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 11484500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.148667 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 329 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 16 # number of replacements
system.cpu.icache.sampled_refs 329 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 156.140617 # Cycle average of tags in use
-system.cpu.icache.total_refs 1794 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 156.098402 # Cycle average of tags in use
+system.cpu.icache.total_refs 1792 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 12483 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 1268 # Number of branches executed
-system.cpu.iew.EXEC:nop 1827 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.295643 # Inst execution rate
-system.cpu.iew.EXEC:refs 3444 # number of memory reference insts executed
-system.cpu.iew.EXEC:stores 1049 # Number of stores executed
+system.cpu.idleCycles 12494 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 1265 # Number of branches executed
+system.cpu.iew.EXEC:nop 1823 # number of nop insts executed
+system.cpu.iew.EXEC:rate 0.295232 # Inst execution rate
+system.cpu.iew.EXEC:refs 3434 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 1042 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 4139 # num instructions consuming a value
-system.cpu.iew.WB:count 7538 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.704035 # average fanout of values written-back
+system.cpu.iew.WB:consumers 4130 # num instructions consuming a value
+system.cpu.iew.WB:count 7520 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.704843 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 2914 # num instructions producing a value
-system.cpu.iew.WB:rate 0.268792 # insts written-back per cycle
-system.cpu.iew.WB:sent 7625 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 679 # Number of branch mispredicts detected at execute
+system.cpu.iew.WB:producers 2911 # num instructions producing a value
+system.cpu.iew.WB:rate 0.268361 # insts written-back per cycle
+system.cpu.iew.WB:sent 7608 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 678 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
-system.cpu.iew.iewDispLoadInsts 2797 # Number of dispatched load instructions
+system.cpu.iew.iewDispLoadInsts 2792 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 953 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispStoreInsts 1159 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 11802 # Number of instructions dispatched to IQ
-system.cpu.iew.iewExecLoadInsts 2395 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 544 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 8291 # Number of executed instructions
+system.cpu.iew.iewDispStoreInsts 1150 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 11774 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 2392 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 540 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 8273 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 1073 # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles 1070 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread.0.memOrderViolation 22 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.memOrderViolation 19 # Number of memory ordering violations
system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread.0.squashedLoads 1633 # Number of loads squashed
-system.cpu.iew.lsq.thread.0.squashedStores 234 # Number of stores squashed
-system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 284 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.lsq.thread.0.squashedLoads 1628 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 225 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 283 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 395 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.184318 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.184318 # IPC: Total IPC of All Threads
+system.cpu.ipc 0.184462 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.184462 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu 5173 58.55% 58.55% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.61% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.63% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.65% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemRead 2589 29.30% 87.96% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::MemWrite 1064 12.04% 100.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 5164 58.60% 58.60% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntMult 5 0.06% 58.65% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntDiv 2 0.02% 58.67% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2 0.02% 58.70% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 58.70% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 58.70% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 58.70% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 58.70% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 58.70% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemRead 2584 29.32% 88.02% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::MemWrite 1056 11.98% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 8835 # Type of FU issued
-system.cpu.iq.ISSUE:fu_busy_cnt 162 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate 0.018336 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:FU_type_0::total 8813 # Type of FU issued
+system.cpu.iq.ISSUE:fu_busy_cnt 160 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.018155 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 8 4.94% 4.94% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 4.94% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 4.94% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 4.94% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 4.94% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 4.94% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 4.94% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 4.94% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 4.94% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 100 61.73% 66.67% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite 54 33.33% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 8 5.00% 5.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 5.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 5.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemRead 100 62.50% 67.50% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::MemWrite 52 32.50% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 15561 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 0.567766 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.217819 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples 15528 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.567555 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.215524 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 11605 74.58% 74.58% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 1745 11.21% 85.79% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 791 5.08% 90.87% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 727 4.67% 95.55% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 340 2.18% 97.73% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 213 1.37% 99.10% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 93 0.60% 99.70% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 32 0.21% 99.90% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 11574 74.54% 74.54% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 1747 11.25% 85.79% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 792 5.10% 90.89% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 724 4.66% 95.55% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 342 2.20% 97.75% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 211 1.36% 99.11% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 94 0.61% 99.72% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 29 0.19% 99.90% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 15 0.10% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 15561 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 0.315041 # Inst issue rate
-system.cpu.iq.iqInstsAdded 9963 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 8835 # Number of instructions issued
+system.cpu.iq.ISSUE:issued_per_cycle::total 15528 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.314503 # Inst issue rate
+system.cpu.iq.iqInstsAdded 9939 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 8813 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 4119 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 4094 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 2680 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 2672 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 50 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 420 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34317.307692 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 34319.711538 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31133.413462 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 14276000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 14277000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.990476 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 416 # number of ReadReq misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 12951500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990476 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 416 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 14 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34428.571429 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31178.571429 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 482000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 14 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 436500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 14 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.009950 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.009615 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34356.223176 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34358.369099 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31157.725322 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 16010000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 16011000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.991489 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 466 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.006418 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 210.308968 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.006586 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 215.818258 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34356.223176 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34358.369099 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31157.725322 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 4 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 16010000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 16011000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.991489 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 466 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 402 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 210.308968 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 215.818258 # Cycle average of tags in use
system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 2797 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1159 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 28044 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 5 # Number of cycles rename is blocking
+system.cpu.memDep0.insertedLoads 2792 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1150 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 28022 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 4 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 3410 # Number of HB maps that are committed
-system.cpu.rename.RENAME:IdleCycles 10455 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 9 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 15765 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 13587 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 8333 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 3513 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 1073 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 19 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 4923 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 496 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:IdleCycles 10436 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 5 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 15725 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 13557 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 8322 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 3509 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 1070 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 15 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 4912 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 494 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 17 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 111 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts 104 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 11 # count of temporary serializing insts renamed
-system.cpu.timesIdled 249 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing/simout
+Redirecting stderr to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Feb 24 2010 23:13:04
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:11:22
-M5 executing on SC2B0619
-command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/simple-timing
+M5 compiled Aug 26 2010 12:56:28
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 12:56:30
+M5 executing on zizzer
+command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
-Exiting @ tick 32803000 because target called exit()
+Exiting @ tick 32088000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 534293 # Simulator instruction rate (inst/s)
-host_mem_usage 190944 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 2928316372 # Simulator tick rate (ticks/s)
+host_inst_rate 5098 # Simulator instruction rate (inst/s)
+host_mem_usage 204896 # Number of bytes of host memory used
+host_seconds 1.14 # Real time elapsed on the host
+host_tick_rate 28066026 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5827 # Number of instructions simulated
-sim_seconds 0.000033 # Number of seconds simulated
-sim_ticks 32803000 # Number of ticks simulated
+sim_seconds 0.000032 # Number of seconds simulated
+sim_ticks 32088000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 861 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 3584000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.069189 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 64 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 3392000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.069189 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 64 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 2856000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.055135 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 51 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 2703000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks.
system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1938 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 8456000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.072283 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 151 # number of demand (read+write) misses
+system.cpu.dcache.demand_hits 1951 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.066060 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 8003000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.072283 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 151 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.021457 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 87.887695 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.021352 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 87.458397 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1938 # number of overall hits
-system.cpu.dcache.overall_miss_latency 8456000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.072283 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 151 # number of overall misses
+system.cpu.dcache.overall_hits 1951 # number of overall hits
+system.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.066060 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 138 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 8003000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.072283 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 151 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 87.887695 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use
system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.065174 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 133.475693 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.064694 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 132.493866 # Average occupied blocks per context
system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55722.772277 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277 # average overall mshr miss latency
system.cpu.icache.replacements 13 # number of replacements
system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 133.475693 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 132.493866 # Cycle average of tags in use
system.cpu.icache.total_refs 5526 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_miss_latency 15520000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 13 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 676000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 13 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 520000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 13 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.005333 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.005638 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 184.758016 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.005739 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 188.045319 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 375 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 184.758016 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 65606 # number of cpu cycles simulated
+system.cpu.numCycles 64176 # number of cpu cycles simulated
system.cpu.num_insts 5827 # Number of instructions executed
system.cpu.num_refs 2090 # Number of memory references
system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
warn: Sockets disabled, not accepting gdb connections
For more information see: http://www.m5sim.org/warn/d946bea6
-warn: allowing mmap of file @ fd 17982776. This will break if not /dev/zero.
+warn: allowing mmap of file @ fd 16785032. This will break if not /dev/zero.
For more information see: http://www.m5sim.org/warn/3a2134f6
hack: be nice to actually delete the event here
-Redirecting stdout to build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing/simout
-Redirecting stderr to build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing/simerr
+Redirecting stdout to build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing/simout
+Redirecting stderr to build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jun 6 2010 03:59:10
-M5 revision ba1a0193c050 7448 default tip
-M5 started Jun 6 2010 03:59:12
+M5 compiled Aug 26 2010 12:59:22
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 12:59:25
M5 executing on zizzer
-command line: build/POWER_SE/m5.fast -d build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/fast/quick/00.hello/power/linux/o3-timing
+command line: build/POWER_SE/m5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 11864500 because target called exit()
+Exiting @ tick 11733000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 82571 # Simulator instruction rate (inst/s)
-host_mem_usage 202992 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
-host_tick_rate 168278845 # Simulator tick rate (ticks/s)
+host_inst_rate 8561 # Simulator instruction rate (inst/s)
+host_mem_usage 202624 # Number of bytes of host memory used
+host_seconds 0.68 # Real time elapsed on the host
+host_tick_rate 17311106 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5800 # Number of instructions simulated
sim_seconds 0.000012 # Number of seconds simulated
-sim_ticks 11864500 # Number of ticks simulated
+sim_ticks 11733000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 687 # Number of BTB hits
system.cpu.BPredUnit.BTBLookups 1888 # Number of BTB lookups
system.cpu.commit.COM:branches 1038 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 51 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 10785 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 0.537784 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.251292 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 10473 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.553805 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.272090 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 8225 76.26% 76.26% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 1129 10.47% 86.73% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 673 6.24% 92.97% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 258 2.39% 95.36% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 226 2.10% 97.46% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 120 1.11% 98.57% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 82 0.76% 99.33% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 21 0.19% 99.53% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 51 0.47% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 7930 75.72% 75.72% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 1118 10.68% 86.39% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 663 6.33% 92.72% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 256 2.44% 95.17% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 224 2.14% 97.31% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 123 1.17% 98.48% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 87 0.83% 99.31% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 21 0.20% 99.51% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 51 0.49% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 10785 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 10473 # Number of insts commited each cycle
system.cpu.commit.COM:count 5800 # Number of instructions committed
system.cpu.commit.COM:loads 962 # Number of loads committed
system.cpu.commit.COM:membars 7 # Number of memory barriers committed
system.cpu.commit.commitSquashedInsts 3389 # The number of squashed insts skipped by commit
system.cpu.committedInsts 5800 # Number of Instructions Simulated
system.cpu.committedInsts_total 5800 # Number of Instructions Simulated
-system.cpu.cpi 4.091379 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 4.091379 # CPI: Total CPI of All Threads
+system.cpu.cpi 4.046034 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 4.046034 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 1444 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 33612.359551 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency 33681.818182 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34464.285714 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 1355 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 2991500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.061634 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 89 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 33 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_hits 1356 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 2964000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.060942 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 88 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 32 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_miss_latency 1930000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.038781 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 56 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 1046 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 33542.735043 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36053.846154 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 695 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 11773500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.335564 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 351 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 286 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 2343500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.062141 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 65 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 33737.864078 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36302.083333 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 737 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 10425000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.295411 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 309 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 261 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 1742500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.045889 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 48 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 20.125000 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 2490 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 33556.818182 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35318.181818 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 2050 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 14765000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.176707 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 440 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 319 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 4273500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.048594 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 121 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_avg_miss_latency 33725.440806 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35312.500000 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 2093 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 13389000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.159438 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 397 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 293 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 3672500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.041767 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 104 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.016240 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 66.517345 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.016245 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 66.538229 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 2490 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 33556.818182 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35318.181818 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 33725.440806 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35312.500000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 2050 # number of overall hits
-system.cpu.dcache.overall_miss_latency 14765000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.176707 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 440 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 319 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 4273500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.048594 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 121 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 2093 # number of overall hits
+system.cpu.dcache.overall_miss_latency 13389000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.159438 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 397 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 293 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 3672500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.041767 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 104 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 104 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 66.517345 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 66.538229 # Cycle average of tags in use
system.cpu.dcache.total_refs 2093 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 1153 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BlockedCycles 885 # Number of cycles decode is blocked
system.cpu.decode.DECODE:BranchMispred 150 # Number of times decode detected a branch misprediction
system.cpu.decode.DECODE:BranchResolved 267 # Number of times decode resolved a branch
system.cpu.decode.DECODE:DecodedInsts 10406 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 7618 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 1941 # Number of cycles decode is running
+system.cpu.decode.DECODE:IdleCycles 7574 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 1944 # Number of cycles decode is running
system.cpu.decode.DECODE:SquashCycles 570 # Number of cycles decode is squashing
system.cpu.decode.DECODE:SquashedInsts 416 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 73 # Number of cycles decode is unblocking
+system.cpu.decode.DECODE:UnblockCycles 70 # Number of cycles decode is unblocking
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.fetch.IcacheSquashes 225 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.Insts 11687 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 410 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.088496 # Number of branch fetches per cycle
+system.cpu.fetch.branchRate 0.089487 # Number of branch fetches per cycle
system.cpu.fetch.icacheStallCycles 1490 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 876 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 0.492499 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 11355 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.029238 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.423250 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rate 0.498018 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 11043 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.058317 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.450976 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 9285 81.77% 81.77% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 161 1.42% 83.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 189 1.66% 84.85% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 155 1.37% 86.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 202 1.78% 88.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 136 1.20% 89.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 272 2.40% 91.59% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 77 0.68% 92.27% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 878 7.73% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 8973 81.26% 81.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 161 1.46% 82.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 189 1.71% 84.42% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 155 1.40% 85.83% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 202 1.83% 87.66% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 136 1.23% 88.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 272 2.46% 91.35% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 77 0.70% 92.05% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 878 7.95% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 11355 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 11043 # Number of instructions fetched each cycle (Total)
system.cpu.icache.ReadReq_accesses 1490 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 36423.575130 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34778.614458 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_miss_latency 36422.279793 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34777.108434 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_hits 1104 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 14059500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency 14059000 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_rate 0.259060 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_misses 386 # number of ReadReq misses
system.cpu.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 11546500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency 11546000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.222819 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.demand_accesses 1490 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 36423.575130 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34778.614458 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency 36422.279793 # average overall miss latency
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system.cpu.icache.demand_hits 1104 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 14059500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency 14059000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_rate 0.259060 # miss rate for demand accesses
system.cpu.icache.demand_misses 386 # number of demand (read+write) misses
system.cpu.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 11546500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency 11546000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate 0.222819 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.078771 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 161.323458 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.078715 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 161.207549 # Average occupied blocks per context
system.cpu.icache.overall_accesses 1490 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 36423.575130 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34778.614458 # average overall mshr miss latency
+system.cpu.icache.overall_avg_miss_latency 36422.279793 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34777.108434 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_hits 1104 # number of overall hits
-system.cpu.icache.overall_miss_latency 14059500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency 14059000 # number of overall miss cycles
system.cpu.icache.overall_miss_rate 0.259060 # miss rate for overall accesses
system.cpu.icache.overall_misses 386 # number of overall misses
system.cpu.icache.overall_mshr_hits 54 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 11546500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency 11546000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_rate 0.222819 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 161.323458 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 161.207549 # Cycle average of tags in use
system.cpu.icache.total_refs 1104 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 12375 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.idleCycles 12424 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.iew.EXEC:branches 1261 # Number of branches executed
system.cpu.iew.EXEC:nop 0 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.328319 # Inst execution rate
+system.cpu.iew.EXEC:rate 0.331998 # Inst execution rate
system.cpu.iew.EXEC:refs 2813 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 1315 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 5889 # num instructions consuming a value
+system.cpu.iew.WB:consumers 5926 # num instructions consuming a value
system.cpu.iew.WB:count 7582 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.646290 # average fanout of values written-back
+system.cpu.iew.WB:fanout 0.645461 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 3806 # num instructions producing a value
-system.cpu.iew.WB:rate 0.319511 # insts written-back per cycle
+system.cpu.iew.WB:producers 3825 # num instructions producing a value
+system.cpu.iew.WB:rate 0.323092 # insts written-back per cycle
system.cpu.iew.WB:sent 7642 # cumulative count of insts sent to commit
system.cpu.iew.branchMispredicts 277 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewBlockCycles 117 # Number of cycles IEW is blocking
+system.cpu.iew.iewBlockCycles 130 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 1681 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions
system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.iewSquashCycles 570 # Number of cycles IEW is squashing
-system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking
+system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.forwLoads 30 # Number of loads that had data forwarded from stores
system.cpu.iew.memOrderViolationEvents 42 # Number of memory order violations
system.cpu.iew.predictedNotTakenIncorrect 201 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 76 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.244416 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.244416 # IPC: Total IPC of All Threads
+system.cpu.ipc 0.247156 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.247156 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntAlu 5126 63.37% 63.37% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued
system.cpu.iq.ISSUE:fu_full::MemWrite 69 45.10% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 11355 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 0.712373 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.391316 # Number of insts issued each cycle
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+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.732500 # Number of insts issued each cycle
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system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 8066 71.03% 71.03% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 1182 10.41% 81.44% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 820 7.22% 88.67% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 507 4.46% 93.13% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 388 3.42% 96.55% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 218 1.92% 98.47% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 121 1.07% 99.53% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::7 46 0.41% 99.94% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 7773 70.39% 70.39% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 1167 10.57% 80.96% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 813 7.36% 88.32% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 500 4.53% 92.85% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 391 3.54% 96.39% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 222 2.01% 98.40% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 124 1.12% 99.52% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::7 46 0.42% 99.94% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 7 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 11355 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 0.340877 # Inst issue rate
+system.cpu.iq.ISSUE:issued_per_cycle::total 11043 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.344697 # Inst issue rate
system.cpu.iq.iqInstsAdded 9163 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqInstsIssued 8089 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 22 # Number of non-speculative instructions added to the IQ
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 48 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34927.083333 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31750 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 1676500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34947.916667 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31770.833333 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_miss_latency 1677500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 48 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1524000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency 1525000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses 48 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 388 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency 34327.631579 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31150 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency 34326.315789 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31147.368421 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 8 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency 13044500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency 13044000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.979381 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 380 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 11837000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 11836000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.979381 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 380 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34264.705882 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31176.470588 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 582500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 530000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.022039 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.021053 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 436 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34394.859813 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34396.028037 # average overall miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 8 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 14721000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 14721500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.981651 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 428 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.005582 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 182.925254 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.005863 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 192.111326 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 436 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34394.859813 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34396.028037 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31217.289720 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 8 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 14721000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 14721500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.981651 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 428 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 363 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 380 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 182.925254 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 192.111326 # Cycle average of tags in use
system.cpu.l2cache.total_refs 8 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 1681 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 1450 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 23730 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 323 # Number of cycles rename is blocking
+system.cpu.numCycles 23467 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 312 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 5007 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 7 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 7801 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 213 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:IdleCycles 7756 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 194 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:RenameLookups 16232 # Number of register rename lookups that rename has made
system.cpu.rename.RENAME:RenamedInsts 9925 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 8708 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 1823 # Number of cycles rename is running
+system.cpu.rename.RENAME:RunCycles 1825 # Number of cycles rename is running
system.cpu.rename.RENAME:SquashCycles 570 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 263 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UnblockCycles 243 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 3701 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 575 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializeStallCycles 337 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 22 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 494 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:skidInsts 473 # count of insts added to the skid buffer
system.cpu.rename.RENAME:tempSerializingInsts 22 # count of temporary serializing insts renamed
-system.cpu.timesIdled 231 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 9 # Number of system calls
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/sparc/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Feb 25 2010 03:11:27
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:37:59
-M5 executing on SC2B0619
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/00.hello/sparc/linux/simple-timing
+M5 compiled Aug 26 2010 13:03:41
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:05:08
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Hello World!Exiting @ tick 29031000 because target called exit()
+Hello World!Exiting @ tick 28206000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 462498 # Simulator instruction rate (inst/s)
-host_mem_usage 190336 # Number of bytes of host memory used
+host_inst_rate 369934 # Simulator instruction rate (inst/s)
+host_mem_usage 207380 # Number of bytes of host memory used
host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 2452978454 # Simulator tick rate (ticks/s)
+host_tick_rate 1923223783 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 5340 # Number of instructions simulated
-sim_seconds 0.000029 # Number of seconds simulated
-sim_ticks 29031000 # Number of ticks simulated
+sim_seconds 0.000028 # Number of seconds simulated
+sim_ticks 28206000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 716 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 55222.222222 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52222.222222 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_accesses 673 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 577 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 5376000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.142645 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 96 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 5088000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.142645 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 96 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_hits 592 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 4536000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.120357 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 81 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 4293000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.120357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 81 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 9.288889 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 1389 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 55720 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52720 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1239 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 8358000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.107991 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 150 # number of demand (read+write) misses
+system.cpu.dcache.demand_avg_miss_latency 55688.888889 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 52688.888889 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 1254 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 7518000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.097192 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 135 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 7908000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.107991 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 150 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 7113000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.097192 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 135 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.020107 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 82.357482 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.020036 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 82.065697 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 1389 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 55720 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52720 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 55688.888889 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 52688.888889 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1239 # number of overall hits
-system.cpu.dcache.overall_miss_latency 8358000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.107991 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 150 # number of overall misses
+system.cpu.dcache.overall_hits 1254 # number of overall hits
+system.cpu.dcache.overall_miss_latency 7518000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.097192 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 135 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 7908000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.107991 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 150 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 7113000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.097192 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 135 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 82.357482 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 82.065697 # Cycle average of tags in use
system.cpu.dcache.total_refs 1254 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.057478 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 117.715481 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.057117 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 116.975932 # Average occupied blocks per context
system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55673.151751 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 117.715481 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 116.975932 # Cycle average of tags in use
system.cpu.icache.total_refs 5127 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_miss_latency 12320000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990354 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 308 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 15 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 780000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 15 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 600000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.010239 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.009740 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.004176 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 136.844792 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.004337 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 142.102892 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 392 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 293 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 308 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 136.844792 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 142.102892 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 58062 # number of cpu cycles simulated
+system.cpu.numCycles 56412 # number of cpu cycles simulated
system.cpu.num_insts 5340 # Number of instructions executed
system.cpu.num_refs 1402 # Number of memory references
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
+Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing/simout
+Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled May 2 2010 23:23:01
-M5 revision 674289bfe108 7074 default qtip tip updateauxvectorsstats.patch
-M5 started May 2 2010 23:23:02
-M5 executing on burrito
-command line: build/X86_SE/m5.fast -d build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/fast/quick/00.hello/x86/linux/simple-timing
+M5 compiled Aug 26 2010 13:20:12
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:33:02
+M5 executing on zizzer
+command line: build/X86_SE/m5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
-Exiting @ tick 29813000 because target called exit()
+Exiting @ tick 28768000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 734670 # Simulator instruction rate (inst/s)
-host_mem_usage 220588 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
-host_tick_rate 2255655595 # Simulator tick rate (ticks/s)
+host_inst_rate 397795 # Simulator instruction rate (inst/s)
+host_mem_usage 205892 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+host_tick_rate 1184355702 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 9561 # Number of instructions simulated
-sim_seconds 0.000030 # Number of seconds simulated
-sim_ticks 29813000 # Number of ticks simulated
+sim_seconds 0.000029 # Number of seconds simulated
+sim_ticks 28768000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 1056 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_accesses 934 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 836 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 5488000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.104925 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 98 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 5194000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.104925 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 98 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_hits 855 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 4424000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.084582 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 79 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 4187000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.084582 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 79 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 13.850746 # Average number of references to valid blocks.
system.cpu.dcache.demand_accesses 1990 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 1837 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 8568000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.076884 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 153 # number of demand (read+write) misses
+system.cpu.dcache.demand_hits 1856 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 7504000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.067337 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 134 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 8109000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.076884 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 153 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 7102000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.067337 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 134 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.019841 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 81.267134 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.019695 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 80.668870 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 1990 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 1837 # number of overall hits
-system.cpu.dcache.overall_miss_latency 8568000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.076884 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 153 # number of overall misses
+system.cpu.dcache.overall_hits 1856 # number of overall hits
+system.cpu.dcache.overall_miss_latency 7504000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.067337 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 134 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 8109000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.076884 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 153 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 7102000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.067337 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 134 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 134 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 81.267134 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 80.668870 # Cycle average of tags in use
system.cpu.dcache.total_refs 1856 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.052030 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 106.557747 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.051447 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 105.363985 # Average occupied blocks per context
system.cpu.icache.overall_accesses 6911 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474 # average overall mshr miss latency
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 106.557747 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 105.363985 # Cycle average of tags in use
system.cpu.icache.total_refs 6683 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_miss_latency 11280000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996466 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 282 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 988000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 760000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.003802 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.003546 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.003920 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 128.459536 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.004084 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 133.809342 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 362 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 263 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 282 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 128.459536 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 133.809342 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 59626 # number of cpu cycles simulated
+system.cpu.numCycles 57536 # number of cpu cycles simulated
system.cpu.num_insts 9561 # Number of instructions executed
system.cpu.num_refs 1990 # Number of memory references
system.cpu.workload.PROG:num_syscalls 11 # Number of system calls
-Redirecting stdout to build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing/simout
-Redirecting stderr to build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing/simerr
+Redirecting stdout to build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jun 6 2010 03:04:38
-M5 revision ba1a0193c050 7448 default tip
-M5 started Jun 6 2010 03:17:19
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 12:11:50
M5 executing on zizzer
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/01.hello-2T-smt/alpha/linux/o3-timing
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
Hello world!
Hello world!
-Exiting @ tick 14406500 because target called exit()
+Exiting @ tick 14139000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 70938 # Simulator instruction rate (inst/s)
-host_mem_usage 204908 # Number of bytes of host memory used
-host_seconds 0.18 # Real time elapsed on the host
-host_tick_rate 79897622 # Simulator tick rate (ticks/s)
+host_inst_rate 53800 # Simulator instruction rate (inst/s)
+host_mem_usage 205552 # Number of bytes of host memory used
+host_seconds 0.24 # Real time elapsed on the host
+host_tick_rate 59488297 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 12773 # Number of instructions simulated
sim_seconds 0.000014 # Number of seconds simulated
-sim_ticks 14406500 # Number of ticks simulated
+sim_ticks 14139000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.BPredUnit.BTBHits 801 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 4845 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 916 # Number of BTB hits
+system.cpu.BPredUnit.BTBLookups 4600 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 174 # Number of incorrect RAS predictions.
-system.cpu.BPredUnit.condIncorrect 1651 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 3171 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 5637 # Number of BP lookups
-system.cpu.BPredUnit.usedRAS 690 # Number of times the RAS was used to get a target.
+system.cpu.BPredUnit.condIncorrect 1521 # Number of conditional branches incorrect
+system.cpu.BPredUnit.condPredicted 3069 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 5341 # Number of BP lookups
+system.cpu.BPredUnit.usedRAS 654 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches::0 1051 # Number of branches committed
system.cpu.commit.COM:branches::1 1051 # Number of branches committed
system.cpu.commit.COM:branches::total 2102 # Number of branches committed
-system.cpu.commit.COM:bw_lim_events 135 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_lim_events 132 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited::0 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:bw_limited::1 0 # number of insts not committed due to BW limits
system.cpu.commit.COM:bw_limited::total 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 23178 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 0.552550 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 1.284564 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 22158 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.577985 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 1.311672 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 17373 74.95% 74.95% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 2862 12.35% 87.30% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 1369 5.91% 93.21% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 536 2.31% 95.52% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 355 1.53% 97.05% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 284 1.23% 98.28% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 169 0.73% 99.01% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::7 95 0.41% 99.42% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::8 135 0.58% 100.00% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 16375 73.90% 73.90% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 2877 12.98% 86.89% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 1274 5.75% 92.63% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 599 2.70% 95.34% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 362 1.63% 96.97% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 252 1.14% 98.11% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 188 0.85% 98.96% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::7 99 0.45% 99.40% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::8 132 0.60% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 23178 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 22158 # Number of insts commited each cycle
system.cpu.commit.COM:count::0 6404 # Number of instructions committed
system.cpu.commit.COM:count::1 6403 # Number of instructions committed
system.cpu.commit.COM:count::total 12807 # Number of instructions committed
system.cpu.commit.COM:swp_count::0 0 # Number of s/w prefetches committed
system.cpu.commit.COM:swp_count::1 0 # Number of s/w prefetches committed
system.cpu.commit.COM:swp_count::total 0 # Number of s/w prefetches committed
-system.cpu.commit.branchMispredicts 1214 # The number of times a branch was mispredicted
+system.cpu.commit.branchMispredicts 1116 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 11211 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 10253 # The number of squashed insts skipped by commit
system.cpu.committedInsts::0 6387 # Number of Instructions Simulated
system.cpu.committedInsts::1 6386 # Number of Instructions Simulated
system.cpu.committedInsts_total 12773 # Number of Instructions Simulated
-system.cpu.cpi::0 4.511351 # CPI: Cycles Per Instruction
-system.cpu.cpi::1 4.512058 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.255852 # CPI: Total CPI of All Threads
-system.cpu.dcache.ReadReq_accesses 3953 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::0 35613.003096 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 35613.003096 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36812.195122 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 3630 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency::0 11503000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11503000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.081710 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 323 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits::0 118 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 118 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency::0 7546500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 7546500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.051859 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051859 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses::0 205 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 205 # number of ReadReq MSHR misses
+system.cpu.cpi::0 4.427587 # CPI: Cycles Per Instruction
+system.cpu.cpi::1 4.428281 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.213967 # CPI: Total CPI of All Threads
+system.cpu.dcache.ReadReq_accesses 3796 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency::0 36145.962733 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 36145.962733 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36908.415842 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 3474 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency::0 11639000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 11639000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.084826 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 322 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits::0 120 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency::0 7455500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 7455500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.053214 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053214 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses::0 202 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_accesses 1730 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::0 33528.289474 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 33528.289474 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36083.333333 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 970 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency::0 25481500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 25481500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.439306 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 760 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits::0 586 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 586 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency::0 6278500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 6278500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.100578 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.100578 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses::0 174 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 174 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency::0 32784.604520 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 32784.604520 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36119.863014 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 1022 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency::0 23211500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 23211500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.409249 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 708 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits::0 562 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 562 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency::0 5273500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5273500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.084393 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses::0 146 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 13.282051 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 12.919540 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses 5683 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency::0 34150.046168 # average overall miss latency
+system.cpu.dcache.demand_accesses 5526 # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency::0 33835.436893 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::1 0 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 34150.046168 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::0 36477.572559 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 33835.436893 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::0 36577.586207 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
-system.cpu.dcache.demand_hits 4600 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency::0 36984500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_hits 4496 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency::0 34850500 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 36984500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.190568 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 1083 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits::0 704 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_miss_latency::total 34850500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.186392 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 1030 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits::0 682 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 704 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency::0 13825000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_hits::total 682 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency::0 12729000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 13825000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0 0.066690 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_latency::total 12729000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate::0 0.062975 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.066690 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses::0 379 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.062975 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses::0 348 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 379 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 348 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events::0 0 # number of times MSHR cap was activated
system.cpu.dcache.mshr_cap_events::1 0 # number of times MSHR cap was activated
system.cpu.dcache.mshr_cap_events::total 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.054473 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 223.120996 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses 5683 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency::0 34150.046168 # average overall miss latency
+system.cpu.dcache.occ_%::0 0.053836 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 220.510583 # Average occupied blocks per context
+system.cpu.dcache.overall_accesses 5526 # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency::0 33835.436893 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::1 0 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 34150.046168 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::0 36477.572559 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 33835.436893 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::0 36577.586207 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 4600 # number of overall hits
-system.cpu.dcache.overall_miss_latency::0 36984500 # number of overall miss cycles
+system.cpu.dcache.overall_hits 4496 # number of overall hits
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system.cpu.dcache.overall_miss_latency::1 0 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 36984500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.190568 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 1083 # number of overall misses
-system.cpu.dcache.overall_mshr_hits::0 704 # number of overall MSHR hits
+system.cpu.dcache.overall_miss_latency::total 34850500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.186392 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 1030 # number of overall misses
+system.cpu.dcache.overall_mshr_hits::0 682 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::1 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 704 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency::0 13825000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_hits::total 682 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency::0 12729000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 13825000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate::0 0.066690 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_latency::total 12729000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate::0 0.062975 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.066690 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses::0 379 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.062975 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses::0 348 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::1 0 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 379 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 348 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.replacements::0 0 # number of replacements
system.cpu.dcache.replacements::1 0 # number of replacements
system.cpu.dcache.replacements::total 0 # number of replacements
-system.cpu.dcache.sampled_refs 351 # Sample count of references to valid blocks.
+system.cpu.dcache.sampled_refs 348 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 223.120996 # Cycle average of tags in use
-system.cpu.dcache.total_refs 4662 # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse 220.510583 # Cycle average of tags in use
+system.cpu.dcache.total_refs 4496 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks::0 0 # number of writebacks
system.cpu.dcache.writebacks::1 0 # number of writebacks
system.cpu.dcache.writebacks::total 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 5062 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:BranchMispred 451 # Number of times decode detected a branch misprediction
-system.cpu.decode.DECODE:BranchResolved 595 # Number of times decode resolved a branch
-system.cpu.decode.DECODE:DecodedInsts 27842 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 34006 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 4930 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 2198 # Number of cycles decode is squashing
-system.cpu.decode.DECODE:SquashedInsts 677 # Number of squashed instructions handled by decode
-system.cpu.decode.DECODE:UnblockCycles 161 # Number of cycles decode is unblocking
-system.cpu.dtb.data_accesses 6328 # DTB accesses
+system.cpu.decode.DECODE:BlockedCycles 4667 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 414 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 569 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 26624 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 32585 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 4771 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 2039 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 734 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 167 # Number of cycles decode is unblocking
+system.cpu.dtb.data_accesses 6131 # DTB accesses
system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_hits 6178 # DTB hits
-system.cpu.dtb.data_misses 150 # DTB misses
+system.cpu.dtb.data_hits 5993 # DTB hits
+system.cpu.dtb.data_misses 138 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.read_accesses 4160 # DTB read accesses
+system.cpu.dtb.read_accesses 3997 # DTB read accesses
system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_hits 4072 # DTB read hits
-system.cpu.dtb.read_misses 88 # DTB read misses
-system.cpu.dtb.write_accesses 2168 # DTB write accesses
+system.cpu.dtb.read_hits 3913 # DTB read hits
+system.cpu.dtb.read_misses 84 # DTB read misses
+system.cpu.dtb.write_accesses 2134 # DTB write accesses
system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_hits 2106 # DTB write hits
-system.cpu.dtb.write_misses 62 # DTB write misses
-system.cpu.fetch.Branches 5637 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 4152 # Number of cache lines fetched
-system.cpu.fetch.Cycles 9523 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 615 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 31429 # Number of instructions fetch has processed
-system.cpu.fetch.SquashCycles 1766 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.195634 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 4152 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.predictedBranches 1491 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.090754 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 23259 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.351262 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.751825 # Number of instructions fetched each cycle (Total)
+system.cpu.dtb.write_hits 2080 # DTB write hits
+system.cpu.dtb.write_misses 54 # DTB write misses
+system.cpu.fetch.Branches 5341 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 3993 # Number of cache lines fetched
+system.cpu.fetch.Cycles 9162 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 611 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 29881 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 1641 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.188868 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 3993 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 1570 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 1.056650 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 22205 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.345688 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.736511 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 17946 77.16% 77.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 425 1.83% 78.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 330 1.42% 80.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 452 1.94% 82.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 406 1.75% 84.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 353 1.52% 85.61% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 452 1.94% 87.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 273 1.17% 88.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 2622 11.27% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 17092 76.97% 76.97% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 418 1.88% 78.86% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 346 1.56% 80.41% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 428 1.93% 82.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 443 2.00% 84.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 320 1.44% 85.78% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 433 1.95% 87.73% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 283 1.27% 89.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 2442 11.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 23259 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses 4152 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::0 35658.767773 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 35658.767773 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35482.171799 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 3308 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency::0 30096000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 30096000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.203276 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 844 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits::0 227 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 227 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency::0 21892500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 21892500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0 0.148603 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148603 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses::0 617 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 617 # number of ReadReq MSHR misses
+system.cpu.fetch.rateDist::total 22205 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 3993 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency::0 35767.942584 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 35767.942584 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35489.482201 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 3157 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency::0 29902000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 29902000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.209366 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 836 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits::0 218 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 218 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency::0 21932500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 21932500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::0 0.154771 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.154771 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses::0 618 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 618 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 5.361426 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 5.108414 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 4152 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency::0 35658.767773 # average overall miss latency
+system.cpu.icache.demand_accesses 3993 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency::0 35767.942584 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::1 0 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 35658.767773 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::0 35482.171799 # average overall mshr miss latency
+system.cpu.icache.demand_avg_miss_latency::total 35767.942584 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::0 35489.482201 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
-system.cpu.icache.demand_hits 3308 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency::0 30096000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_hits 3157 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency::0 29902000 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 30096000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.203276 # miss rate for demand accesses
-system.cpu.icache.demand_misses 844 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits::0 227 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.icache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency
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system.cpu.icache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles
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system.cpu.icache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.replacements::0 6 # number of replacements
system.cpu.icache.replacements::1 0 # number of replacements
system.cpu.icache.replacements::total 6 # number of replacements
-system.cpu.icache.sampled_refs 617 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks::0 0 # number of writebacks
system.cpu.icache.writebacks::1 0 # number of writebacks
system.cpu.icache.writebacks::total 0 # number of writebacks
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system.cpu.iew.WB:penalized::0 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized::1 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized::total 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.WB:penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
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system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
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system.cpu.iew.lsq.thread.0.rescheduledLoads 1 # Number of loads that were rescheduled
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system.cpu.iew.lsq.thread.1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
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system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled
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-system.cpu.iew.predictedNotTakenIncorrect 1143 # Number of branches that were predicted not taken incorrectly
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-system.cpu.ipc::0 0.221663 # IPC: Instructions Per Cycle
-system.cpu.ipc::1 0.221628 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.443291 # IPC: Total IPC of All Threads
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+system.cpu.ipc_total 0.451678 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
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-system.cpu.iq.ISSUE:FU_type_1::FloatMult 0 0.00% 67.28% # Type of FU issued
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-system.cpu.iq.ISSUE:FU_type_1::FloatSqrt 0 0.00% 67.28% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_1::total 10214 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_1::total 9979 # Type of FU issued
system.cpu.iq.ISSUE:FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type::IntAlu 13768 66.99% 67.01% # Type of FU issued
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system.cpu.iq.ISSUE:FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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-system.cpu.iq.ISSUE:fu_busy_cnt::0 79 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_cnt::1 88 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_cnt::total 167 # FU busy when requested
-system.cpu.iq.ISSUE:fu_busy_rate::0 0.003844 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_busy_rate::1 0.004282 # FU busy rate (busy events/executed inst)
-system.cpu.iq.ISSUE:fu_busy_rate::total 0.008126 # FU busy rate (busy events/executed inst)
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system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::IntAlu 9 5.39% 5.39% # attempts to use FU when none available
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-system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 5.39% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 5.39% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 5.39% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 5.39% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 5.39% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 5.39% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemRead 95 56.89% 62.28% # attempts to use FU when none available
-system.cpu.iq.ISSUE:fu_full::MemWrite 63 37.72% 100.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full::IntAlu 16 9.70% 9.70% # attempts to use FU when none available
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system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 14576 62.67% 62.67% # Number of insts issued each cycle
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-system.cpu.iq.ISSUE:issued_per_cycle::2 2342 10.07% 86.48% # Number of insts issued each cycle
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-system.cpu.iq.ISSUE:issued_per_cycle::5 568 2.44% 98.43% # Number of insts issued each cycle
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system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 23259 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 0.713230 # Inst issue rate
-system.cpu.iq.iqInstsAdded 23917 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 20551 # Number of instructions issued
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system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 9939 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 9000 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 5669 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 5071 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 4210 # ITB accesses
+system.cpu.itb.fetch_accesses 4049 # ITB accesses
system.cpu.itb.fetch_acv 0 # ITB acv
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-system.cpu.itb.fetch_misses 58 # ITB misses
+system.cpu.itb.fetch_hits 3993 # ITB hits
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system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.l2cache.ReadExReq_accesses 146 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34623.287671 # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34623.287671 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34643.835616 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34643.835616 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31544.520548 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency::0 5055000 # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total 5055000 # number of ReadExReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 146 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4605500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadReq_accesses 822 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency::0 34548.170732 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34548.170732 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31393.902439 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_accesses 820 # number of ReadReq accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_avg_miss_latency::total 34537.897311 # average ReadReq miss latency
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system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_miss_latency::total 28329500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate 0.997567 # miss rate for ReadReq accesses
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-system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25743000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25743000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997567 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997567 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses::0 820 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 28 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::0 34500 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 34500 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::0 31392.857143 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency::0 966000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::total 966000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
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-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::0 879000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 879000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses
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-system.cpu.l2cache.UpgradeReq_mshr_misses::0 28 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 28 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadReq_miss_latency::0 28252000 # number of ReadReq miss cycles
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system.cpu.l2cache.avg_blocked_cycles::no_mshrs 6750 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.002525 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.002445 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 27000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.demand_accesses 968 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency::0 34559.523810 # average overall miss latency
+system.cpu.l2cache.demand_accesses 966 # number of demand (read+write) accesses
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system.cpu.l2cache.demand_avg_miss_latency::1 0 # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34559.523810 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31416.666667 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 34553.941909 # average overall miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
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system.cpu.l2cache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total 33384500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate 0.997934 # miss rate for demand accesses
-system.cpu.l2cache.demand_misses 966 # number of demand (read+write) misses
+system.cpu.l2cache.demand_miss_latency::total 33310000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate 0.997930 # miss rate for demand accesses
+system.cpu.l2cache.demand_misses 964 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits::0 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency::0 30348500 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 30348500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate::0 0.997934 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_latency::total 30287500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate::0 0.997930 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.997934 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses::0 966 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.997930 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses::0 964 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 964 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events::0 0 # number of times MSHR cap was activated
system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated
system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.013217 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 433.083390 # Average occupied blocks per context
-system.cpu.l2cache.overall_accesses 968 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency::0 34559.523810 # average overall miss latency
+system.cpu.l2cache.occ_%::0 0.013480 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 441.702410 # Average occupied blocks per context
+system.cpu.l2cache.overall_accesses 966 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency::0 34553.941909 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::1 0 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34559.523810 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31416.666667 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 34553.941909 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31418.568465 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.overall_miss_latency::0 33384500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::0 33310000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::1 0 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total 33384500 # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate 0.997934 # miss rate for overall accesses
-system.cpu.l2cache.overall_misses 966 # number of overall misses
+system.cpu.l2cache.overall_miss_latency::total 33310000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate 0.997930 # miss rate for overall accesses
+system.cpu.l2cache.overall_misses 964 # number of overall misses
system.cpu.l2cache.overall_mshr_hits::0 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::1 0 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency::0 30348500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::0 30287500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 30348500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate::0 0.997934 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_latency::total 30287500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate::0 0.997930 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.997934 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses::0 966 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.997930 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses::0 964 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::1 0 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 966 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 964 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.replacements::0 0 # number of replacements
system.cpu.l2cache.replacements::1 0 # number of replacements
system.cpu.l2cache.replacements::total 0 # number of replacements
-system.cpu.l2cache.sampled_refs 792 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 818 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions
system.cpu.l2cache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 433.083390 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 441.702410 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks::0 0 # number of writebacks
system.cpu.l2cache.writebacks::1 0 # number of writebacks
system.cpu.l2cache.writebacks::total 0 # number of writebacks
-system.cpu.memDep0.conflictingLoads 48 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 33 # Number of conflicting stores.
-system.cpu.memDep0.insertedLoads 2570 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1336 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep1.conflictingLoads 27 # Number of conflicting loads.
-system.cpu.memDep1.conflictingStores 5 # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads 2459 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores 1269 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 28814 # number of cpu cycles simulated
-system.cpu.rename.RENAME:BlockCycles 2841 # Number of cycles rename is blocking
+system.cpu.memDep0.conflictingLoads 43 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores.
+system.cpu.memDep0.insertedLoads 2383 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 1294 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep1.conflictingLoads 22 # Number of conflicting loads.
+system.cpu.memDep1.conflictingStores 7 # Number of conflicting stores.
+system.cpu.memDep1.insertedLoads 2368 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep1.insertedStores 1232 # Number of stores inserted to the mem dependence unit.
+system.cpu.numCycles 28279 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 2728 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 9166 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 4 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 34469 # Number of cycles rename is idle
-system.cpu.rename.RENAME:LSQFullEvents 1383 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:IdleCycles 33046 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 1284 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full
-system.cpu.rename.RENAME:RenameLookups 33146 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 26493 # Number of instructions processed by rename
-system.cpu.rename.RENAME:RenamedOperands 19854 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 4562 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 2198 # Number of cycles rename is squashing
-system.cpu.rename.RENAME:UnblockCycles 1440 # Number of cycles rename is unblocking
-system.cpu.rename.RENAME:UndoneMaps 10688 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 847 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 3428 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 37 # count of temporary serializing insts renamed
-system.cpu.timesIdled 293 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:RenameLookups 31631 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 25294 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 18871 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 4411 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 2039 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 1326 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 9705 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 679 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 50 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 3216 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed
+system.cpu.timesIdled 276 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls
system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls
-Redirecting stdout to build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing/simout
-Redirecting stderr to build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing/simerr
+Redirecting stdout to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing/simout
+Redirecting stderr to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jun 6 2010 04:01:36
-M5 revision ba1a0193c050 7448 default tip
-M5 started Jun 6 2010 04:04:37
+M5 compiled Aug 26 2010 13:03:41
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:03:47
M5 executing on zizzer
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/o3-timing
+command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Begining test of difficult SPARC instructions...
LDTW: Passed
STTW: Passed
Done
-Exiting @ tick 27640500 because target called exit()
+Exiting @ tick 27419000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 74349 # Simulator instruction rate (inst/s)
-host_mem_usage 204528 # Number of bytes of host memory used
-host_seconds 0.19 # Real time elapsed on the host
-host_tick_rate 142076938 # Simulator tick rate (ticks/s)
+host_inst_rate 45017 # Simulator instruction rate (inst/s)
+host_mem_usage 207928 # Number of bytes of host memory used
+host_seconds 0.32 # Real time elapsed on the host
+host_tick_rate 85360538 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 14449 # Number of instructions simulated
-sim_seconds 0.000028 # Number of seconds simulated
-sim_ticks 27640500 # Number of ticks simulated
+sim_seconds 0.000027 # Number of seconds simulated
+sim_ticks 27419000 # Number of ticks simulated
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.BTBHits 4205 # Number of BTB hits
-system.cpu.BPredUnit.BTBLookups 9185 # Number of BTB lookups
+system.cpu.BPredUnit.BTBLookups 9180 # Number of BTB lookups
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.BPredUnit.condIncorrect 2913 # Number of conditional branches incorrect
-system.cpu.BPredUnit.condPredicted 11479 # Number of conditional branches predicted
-system.cpu.BPredUnit.lookups 11479 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 11474 # Number of conditional branches predicted
+system.cpu.BPredUnit.lookups 11474 # Number of BP lookups
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.commit.COM:branches 3359 # Number of branches committed
system.cpu.commit.COM:bw_lim_events 114 # number cycles where commit BW limit reached
system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.commit.COM:committed_per_cycle::samples 42520 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::mean 0.356891 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::stdev 0.964493 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::samples 41984 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::mean 0.361447 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::stdev 0.969782 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::0 34367 80.83% 80.83% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::1 4806 11.30% 92.13% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::2 1719 4.04% 96.17% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::3 713 1.68% 97.85% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::4 414 0.97% 98.82% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::5 146 0.34% 99.17% # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::6 193 0.45% 99.62% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::0 33831 80.58% 80.58% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::1 4806 11.45% 92.03% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::2 1719 4.09% 96.12% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::3 713 1.70% 97.82% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::4 414 0.99% 98.81% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::5 146 0.35% 99.15% # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::6 193 0.46% 99.61% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::7 48 0.11% 99.73% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::8 114 0.27% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.COM:committed_per_cycle::total 42520 # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle::total 41984 # Number of insts commited each cycle
system.cpu.commit.COM:count 15175 # Number of instructions committed
system.cpu.commit.COM:loads 2226 # Number of loads committed
system.cpu.commit.COM:membars 0 # Number of memory barriers committed
system.cpu.commit.branchMispredicts 2913 # The number of times a branch was mispredicted
system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.commitSquashedInsts 19910 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 19909 # The number of squashed insts skipped by commit
system.cpu.committedInsts 14449 # Number of Instructions Simulated
system.cpu.committedInsts_total 14449 # Number of Instructions Simulated
-system.cpu.cpi 3.826009 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.826009 # CPI: Total CPI of All Threads
+system.cpu.cpi 3.795349 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 3.795349 # CPI: Total CPI of All Threads
system.cpu.dcache.ReadReq_accesses 3842 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 35228.070175 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35561.538462 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits 3728 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 4016000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate 0.029672 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses 114 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_hits 49 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_miss_latency 2311500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_avg_miss_latency 35221.238938 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35546.153846 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits 3729 # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency 3980000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate 0.029412 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses 113 # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_hits 48 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_miss_latency 2310500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.016918 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_misses 65 # number of ReadReq MSHR misses
system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 31248.306998 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35612.745098 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 999 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 13843000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.307212 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 443 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_hits 341 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_miss_latency 3632500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_avg_miss_latency 31011.029412 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35620.481928 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 12652500 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.282940 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 408 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_hits 325 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_miss_latency 2956500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.057559 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 83 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 32.222973 # Average number of references to valid blocks.
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.demand_accesses 5284 # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 32062.836625 # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35592.814371 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 4727 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 17859000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.105413 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 557 # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits 390 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 5944000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.031605 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 167 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_avg_miss_latency 31924.184261 # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 35587.837838 # average overall mshr miss latency
+system.cpu.dcache.demand_hits 4763 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 16632500 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.098600 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 521 # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits 373 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency 5267000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.028009 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 148 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.026503 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 108.555093 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.026492 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 108.511216 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 5284 # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 32062.836625 # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35592.814371 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_miss_latency 31924.184261 # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 35587.837838 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 4727 # number of overall hits
-system.cpu.dcache.overall_miss_latency 17859000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.105413 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 557 # number of overall misses
-system.cpu.dcache.overall_mshr_hits 390 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 5944000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.031605 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 167 # number of overall MSHR misses
+system.cpu.dcache.overall_hits 4763 # number of overall hits
+system.cpu.dcache.overall_miss_latency 16632500 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.098600 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 521 # number of overall misses
+system.cpu.dcache.overall_mshr_hits 373 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency 5267000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.028009 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 148 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 148 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 108.555093 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 108.511216 # Cycle average of tags in use
system.cpu.dcache.total_refs 4769 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.decode.DECODE:BlockedCycles 7141 # Number of cycles decode is blocked
-system.cpu.decode.DECODE:DecodedInsts 51862 # Number of instructions handled by decode
-system.cpu.decode.DECODE:IdleCycles 20451 # Number of cycles decode is idle
-system.cpu.decode.DECODE:RunCycles 14795 # Number of cycles decode is running
-system.cpu.decode.DECODE:SquashCycles 4325 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:BlockedCycles 6598 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:DecodedInsts 51837 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 20462 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 14791 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 4324 # Number of cycles decode is squashing
system.cpu.decode.DECODE:UnblockCycles 133 # Number of cycles decode is unblocking
-system.cpu.fetch.Branches 11479 # Number of branches that fetch encountered
-system.cpu.fetch.CacheLines 7330 # Number of cache lines fetched
-system.cpu.fetch.Cycles 23798 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.IcacheSquashes 830 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.Insts 58419 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 11474 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 7329 # Number of cache lines fetched
+system.cpu.fetch.Cycles 23792 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.IcacheSquashes 833 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.Insts 58386 # Number of instructions fetch has processed
system.cpu.fetch.SquashCycles 3008 # Number of cycles fetch has spent squashing
-system.cpu.fetch.branchRate 0.207644 # Number of branch fetches per cycle
-system.cpu.fetch.icacheStallCycles 7330 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.branchRate 0.209231 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 7329 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.predictedBranches 4205 # Number of branches that fetch has predicted taken
-system.cpu.fetch.rate 1.056745 # Number of inst fetches per cycle
-system.cpu.fetch.rateDist::samples 46845 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.247070 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.396969 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rate 1.064680 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist::samples 46308 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.260819 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.406261 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 30399 64.89% 64.89% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 7442 15.89% 80.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1110 2.37% 83.15% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 985 2.10% 85.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1044 2.23% 87.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1211 2.59% 90.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 663 1.42% 91.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 335 0.72% 92.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 3656 7.80% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 29867 64.50% 64.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 7441 16.07% 80.56% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1110 2.40% 82.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 985 2.13% 85.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1044 2.25% 87.34% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1211 2.62% 89.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 663 1.43% 91.39% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 335 0.72% 92.11% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 3652 7.89% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 46845 # Number of instructions fetched each cycle (Total)
-system.cpu.icache.ReadReq_accesses 7330 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 33618.691589 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34870.473538 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits 6795 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 17986000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate 0.072988 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses 535 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_hits 176 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_miss_latency 12518500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.048977 # mshr miss rate for ReadReq accesses
+system.cpu.fetch.rateDist::total 46308 # Number of instructions fetched each cycle (Total)
+system.cpu.icache.ReadReq_accesses 7329 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 33501.855288 # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 34869.080780 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits 6790 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 18057500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate 0.073543 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses 539 # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_hits 180 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_miss_latency 12518000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate 0.048983 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_misses 359 # number of ReadReq MSHR misses
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.icache.avg_refs 18.980447 # Average number of references to valid blocks.
+system.cpu.icache.avg_refs 18.966480 # Average number of references to valid blocks.
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.demand_accesses 7330 # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 33618.691589 # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34870.473538 # average overall mshr miss latency
-system.cpu.icache.demand_hits 6795 # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency 17986000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate 0.072988 # miss rate for demand accesses
-system.cpu.icache.demand_misses 535 # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits 176 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency 12518500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate 0.048977 # mshr miss rate for demand accesses
+system.cpu.icache.demand_accesses 7329 # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 33501.855288 # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency
+system.cpu.icache.demand_hits 6790 # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency 18057500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate 0.073543 # miss rate for demand accesses
+system.cpu.icache.demand_misses 539 # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits 180 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency 12518000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate 0.048983 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_misses 359 # number of demand (read+write) MSHR misses
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.110625 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 226.560324 # Average occupied blocks per context
-system.cpu.icache.overall_accesses 7330 # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 33618.691589 # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34870.473538 # average overall mshr miss latency
+system.cpu.icache.occ_%::0 0.110645 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 226.601923 # Average occupied blocks per context
+system.cpu.icache.overall_accesses 7329 # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 33501.855288 # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 34869.080780 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits 6795 # number of overall hits
-system.cpu.icache.overall_miss_latency 17986000 # number of overall miss cycles
-system.cpu.icache.overall_miss_rate 0.072988 # miss rate for overall accesses
-system.cpu.icache.overall_misses 535 # number of overall misses
-system.cpu.icache.overall_mshr_hits 176 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency 12518500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate 0.048977 # mshr miss rate for overall accesses
+system.cpu.icache.overall_hits 6790 # number of overall hits
+system.cpu.icache.overall_miss_latency 18057500 # number of overall miss cycles
+system.cpu.icache.overall_miss_rate 0.073543 # miss rate for overall accesses
+system.cpu.icache.overall_misses 539 # number of overall misses
+system.cpu.icache.overall_mshr_hits 180 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency 12518000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate 0.048983 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_misses 359 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.replacements 1 # number of replacements
system.cpu.icache.sampled_refs 358 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 226.560324 # Cycle average of tags in use
-system.cpu.icache.total_refs 6795 # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse 226.601923 # Cycle average of tags in use
+system.cpu.icache.total_refs 6790 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idleCycles 8437 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.iew.EXEC:branches 4838 # Number of branches executed
+system.cpu.idleCycles 8531 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.iew.EXEC:branches 4839 # Number of branches executed
system.cpu.iew.EXEC:nop 2088 # number of nop insts executed
-system.cpu.iew.EXEC:rate 0.449477 # Inst execution rate
+system.cpu.iew.EXEC:rate 0.453126 # Inst execution rate
system.cpu.iew.EXEC:refs 6429 # number of memory reference insts executed
system.cpu.iew.EXEC:stores 2469 # Number of stores executed
system.cpu.iew.EXEC:swp 0 # number of swp insts executed
-system.cpu.iew.WB:consumers 13103 # num instructions consuming a value
-system.cpu.iew.WB:count 23891 # cumulative count of insts written-back
-system.cpu.iew.WB:fanout 0.824239 # average fanout of values written-back
+system.cpu.iew.WB:consumers 13105 # num instructions consuming a value
+system.cpu.iew.WB:count 23892 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.824189 # average fanout of values written-back
system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.iew.WB:producers 10800 # num instructions producing a value
-system.cpu.iew.WB:rate 0.432166 # insts written-back per cycle
-system.cpu.iew.WB:sent 24095 # cumulative count of insts sent to commit
-system.cpu.iew.branchMispredicts 3199 # Number of branch mispredicts detected at execute
+system.cpu.iew.WB:producers 10801 # num instructions producing a value
+system.cpu.iew.WB:rate 0.435675 # insts written-back per cycle
+system.cpu.iew.WB:sent 24096 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 3200 # Number of branch mispredicts detected at execute
system.cpu.iew.iewBlockCycles 24 # Number of cycles IEW is blocking
system.cpu.iew.iewDispLoadInsts 4967 # Number of dispatched load instructions
system.cpu.iew.iewDispNonSpecInsts 773 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewDispSquashedInsts 3043 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispSquashedInsts 3048 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispStoreInsts 3406 # Number of dispatched store instructions
-system.cpu.iew.iewDispatchedInsts 35166 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispatchedInsts 35165 # Number of instructions dispatched to IQ
system.cpu.iew.iewExecLoadInsts 3960 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 4355 # Number of squashed instructions skipped in execute
-system.cpu.iew.iewExecutedInsts 24848 # Number of executed instructions
+system.cpu.iew.iewExecSquashedInsts 4356 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 24849 # Number of executed instructions
system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.iewSquashCycles 4325 # Number of cycles IEW is squashing
+system.cpu.iew.iewSquashCycles 4324 # Number of cycles IEW is squashing
system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.lsq.thread.0.squashedLoads 2741 # Number of loads squashed
system.cpu.iew.lsq.thread.0.squashedStores 1958 # Number of stores squashed
system.cpu.iew.memOrderViolationEvents 53 # Number of memory order violations
-system.cpu.iew.predictedNotTakenIncorrect 814 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 815 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.predictedTakenIncorrect 2385 # Number of branches that were predicted taken incorrectly
-system.cpu.ipc 0.261369 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.261369 # IPC: Total IPC of All Threads
+system.cpu.ipc 0.263480 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.263480 # IPC: Total IPC of All Threads
system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::IntAlu 21370 73.18% 73.18% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::IntAlu 21372 73.18% 73.18% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntMult 0 0.00% 73.18% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 73.18% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 73.18% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::MemWrite 3111 10.65% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.ISSUE:FU_type_0::total 29203 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0::total 29205 # Type of FU issued
system.cpu.iq.ISSUE:fu_busy_cnt 177 # FU busy when requested
system.cpu.iq.ISSUE:fu_busy_rate 0.006061 # FU busy rate (busy events/executed inst)
system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::MemWrite 113 63.84% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.ISSUE:issued_per_cycle::samples 46845 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::mean 0.623396 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.283288 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::samples 46308 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::mean 0.630669 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.289103 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::0 33954 72.48% 72.48% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::1 5459 11.65% 84.13% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::2 3016 6.44% 90.57% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::3 2133 4.55% 95.13% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::4 995 2.12% 97.25% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::5 695 1.48% 98.73% # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::6 336 0.72% 99.45% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::0 33418 72.16% 72.16% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::1 5459 11.79% 83.95% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::2 3013 6.51% 90.46% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::3 2134 4.61% 95.07% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::4 995 2.15% 97.22% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::5 696 1.50% 98.72% # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle::6 336 0.73% 99.45% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::7 214 0.46% 99.91% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::8 43 0.09% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:issued_per_cycle::total 46845 # Number of insts issued each cycle
-system.cpu.iq.ISSUE:rate 0.528255 # Inst issue rate
-system.cpu.iq.iqInstsAdded 32305 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqInstsIssued 29203 # Number of instructions issued
+system.cpu.iq.ISSUE:issued_per_cycle::total 46308 # Number of insts issued each cycle
+system.cpu.iq.ISSUE:rate 0.532559 # Inst issue rate
+system.cpu.iq.iqInstsAdded 32304 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 29205 # Number of instructions issued
system.cpu.iq.iqNonSpecInstsAdded 773 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqSquashedInstsExamined 15689 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsExamined 15678 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued
system.cpu.iq.iqSquashedNonSpecRemoved 298 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.iqSquashedOperandsExamined 12321 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedOperandsExamined 12314 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.l2cache.ReadExReq_accesses 83 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34397.590361 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency 34391.566265 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31313.253012 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_miss_latency 2855000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency 2854500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_misses 83 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2599000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_misses 83 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadReq_accesses 424 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_avg_miss_latency 34219.047619 # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.761905 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31002.380952 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_hits 4 # number of ReadReq hits
system.cpu.l2cache.ReadReq_miss_latency 14372000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_rate 0.990566 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_misses 420 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 13022000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency 13021000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.990566 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 420 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 19 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 34342.105263 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31210.526316 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 652500 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 19 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 593000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 19 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.010000 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.009547 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.demand_accesses 507 # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency 34248.508946 # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31055.666004 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_miss_latency 34247.514911 # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency 31053.677932 # average overall mshr miss latency
system.cpu.l2cache.demand_hits 4 # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency 17227000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency 17226500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_rate 0.992110 # miss rate for demand accesses
system.cpu.l2cache.demand_misses 503 # number of demand (read+write) misses
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency 15621000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency 15620000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_rate 0.992110 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_misses 503 # number of demand (read+write) MSHR misses
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.007671 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 251.347828 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.008034 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 263.251984 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 507 # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency 34248.508946 # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31055.666004 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_miss_latency 34247.514911 # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency 31053.677932 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.overall_hits 4 # number of overall hits
-system.cpu.l2cache.overall_miss_latency 17227000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency 17226500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_rate 0.992110 # miss rate for overall accesses
system.cpu.l2cache.overall_misses 503 # number of overall misses
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency 15621000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency 15620000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_rate 0.992110 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_misses 503 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 419 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 251.347828 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 263.251984 # Cycle average of tags in use
system.cpu.l2cache.total_refs 4 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
system.cpu.memDep0.insertedLoads 4967 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 3406 # Number of stores inserted to the mem dependence unit.
-system.cpu.numCycles 55282 # number of cpu cycles simulated
+system.cpu.numCycles 54839 # number of cpu cycles simulated
system.cpu.rename.RENAME:BlockCycles 31 # Number of cycles rename is blocking
system.cpu.rename.RENAME:CommittedMaps 13832 # Number of HB maps that are committed
system.cpu.rename.RENAME:IQFullEvents 2 # Number of times rename has blocked due to IQ full
-system.cpu.rename.RENAME:IdleCycles 22239 # Number of cycles rename is idle
+system.cpu.rename.RENAME:IdleCycles 22249 # Number of cycles rename is idle
system.cpu.rename.RENAME:LSQFullEvents 3 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.RENAME:RenameLookups 74814 # Number of register rename lookups that rename has made
-system.cpu.rename.RENAME:RenamedInsts 42611 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenameLookups 74810 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 42608 # Number of instructions processed by rename
system.cpu.rename.RENAME:RenamedOperands 35749 # Number of destination operands rename has renamed
-system.cpu.rename.RENAME:RunCycles 13163 # Number of cycles rename is running
-system.cpu.rename.RENAME:SquashCycles 4325 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:RunCycles 13159 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 4324 # Number of cycles rename is squashing
system.cpu.rename.RENAME:UnblockCycles 313 # Number of cycles rename is unblocking
system.cpu.rename.RENAME:UndoneMaps 21917 # Number of HB maps that are undone due to squashing
-system.cpu.rename.RENAME:serializeStallCycles 6774 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializeStallCycles 6232 # count of cycles rename stalled for serializing inst
system.cpu.rename.RENAME:serializingInsts 888 # count of serializing insts renamed
-system.cpu.rename.RENAME:skidInsts 5153 # count of insts added to the skid buffer
-system.cpu.rename.RENAME:tempSerializingInsts 824 # count of temporary serializing insts renamed
-system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.rename.RENAME:skidInsts 5138 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 822 # count of temporary serializing insts renamed
+system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
---------- End Simulation Statistics ----------
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/insttest/bin/sparc/linux/insttest
+executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing/simout
+Redirecting stderr to build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Feb 25 2010 03:11:27
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 03:38:01
-M5 executing on SC2B0619
-command line: build/SPARC_SE/m5.fast -d build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/fast/quick/02.insttest/sparc/linux/simple-timing
+M5 compiled Aug 26 2010 13:03:41
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:03:44
+M5 executing on zizzer
+command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Begining test of difficult SPARC instructions...
LDTW: Passed
STTW: Passed
Done
-Exiting @ tick 42735000 because target called exit()
+Exiting @ tick 41800000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 227392 # Simulator instruction rate (inst/s)
-host_mem_usage 190044 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
-host_tick_rate 637540839 # Simulator tick rate (ticks/s)
+host_inst_rate 255958 # Simulator instruction rate (inst/s)
+host_mem_usage 207264 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
+host_tick_rate 701295215 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 15175 # Number of instructions simulated
-sim_seconds 0.000043 # Number of seconds simulated
-sim_ticks 42735000 # Number of ticks simulated
+sim_seconds 0.000042 # Number of seconds simulated
+sim_ticks 41800000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 2226 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 1340 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 5712000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.070735 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 102 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 5406000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.070735 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_hits 1357 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 4760000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.058946 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 85 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 4505000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.058946 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 85 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks.
system.cpu.dcache.demand_accesses 3668 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 3513 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 8680000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.042257 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 155 # number of demand (read+write) misses
+system.cpu.dcache.demand_hits 3530 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.037623 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 8215000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.042257 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 155 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.037623 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.023864 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 97.747327 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.023887 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 97.842991 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 3513 # number of overall hits
-system.cpu.dcache.overall_miss_latency 8680000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.042257 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 155 # number of overall misses
+system.cpu.dcache.overall_hits 3530 # number of overall hits
+system.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.037623 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 138 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 8215000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.042257 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 155 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.037623 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 97.747327 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 97.842991 # Cycle average of tags in use
system.cpu.dcache.total_refs 3536 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.074743 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 153.073222 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.074920 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 153.436702 # Average occupied blocks per context
system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 55700 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 52700 # average overall mshr miss latency
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 153.073222 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 153.436702 # Cycle average of tags in use
system.cpu.icache.total_refs 14941 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_miss_latency 13240000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993994 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 331 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 17 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 884000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 17 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 680000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 17 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs 0.006369 # Average number of references to valid blocks.
+system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks.
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.005323 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 174.433606 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.005622 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 184.236128 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 314 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 174.433606 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 184.236128 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 85470 # number of cpu cycles simulated
+system.cpu.numCycles 83600 # number of cpu cycles simulated
system.cpu.num_insts 15175 # Number of instructions executed
system.cpu.num_refs 3684 # Number of memory references
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/home/stever/m5/m5_system_2.0b3/binaries/console
+console=/dist/m5/system/binaries/console
init_param=0
-kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
+load_addr_mask=1099511627775
mem_mode=atomic
-pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
+pal=/dist/m5/system/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
[system.disk0.image.child]
type=RawDiskImage
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.terminal]
-Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout
-Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr
+Redirecting stdout to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout
+Redirecting stderr to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jun 16 2010 10:39:13
-M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats
-M5 started Jun 16 2010 10:44:34
-M5 executing on phenom
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
+M5 compiled Aug 26 2010 12:51:14
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 12:51:21
+M5 executing on zizzer
+command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
+ 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 97861500
Exiting @ tick 1870335522500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 3116744 # Simulator instruction rate (inst/s)
-host_mem_usage 276812 # Number of bytes of host memory used
-host_seconds 20.26 # Real time elapsed on the host
-host_tick_rate 92302855126 # Simulator tick rate (ticks/s)
+host_inst_rate 2244323 # Simulator instruction rate (inst/s)
+host_mem_usage 293120 # Number of bytes of host memory used
+host_seconds 28.14 # Real time elapsed on the host
+host_tick_rate 66466128576 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 63154034 # Number of instructions simulated
sim_seconds 1.870336 # Number of seconds simulated
system.cpu0.dcache.ReadReq_misses::total 1683563 # number of ReadReq misses
system.cpu0.dcache.StoreCondReq_accesses::0 187338 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 187338 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_hits::0 159838 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 159838 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_rate::0 0.146793 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_misses::0 27500 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 27500 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_hits::0 165851 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 165851 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_miss_rate::0 0.114696 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_misses::0 21487 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 21487 # number of StoreCondReq misses
system.cpu0.dcache.WriteReq_accesses::0 5748261 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 5748261 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_hits::0 5374453 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 5374453 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_rate::0 0.065030 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses::0 373808 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 373808 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_hits::0 5400040 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 5400040 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_rate::0 0.060578 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses::0 348221 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 348221 # number of WriteReq misses
system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs 6.629793 # Average number of references to valid blocks.
system.cpu0.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.dcache.demand_hits::0 12672559 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::0 12698146 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 12672559 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 12698146 # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate::0 0.139673 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::0 0.137936 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu0.dcache.demand_misses::0 2057371 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::0 2031784 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 2057371 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 2031784 # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits::0 12672559 # number of overall hits
+system.cpu0.dcache.overall_hits::0 12698146 # number of overall hits
system.cpu0.dcache.overall_hits::1 0 # number of overall hits
-system.cpu0.dcache.overall_hits::total 12672559 # number of overall hits
+system.cpu0.dcache.overall_hits::total 12698146 # number of overall hits
system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate::0 0.139673 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::0 0.137936 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu0.dcache.overall_misses::0 2057371 # number of overall misses
+system.cpu0.dcache.overall_misses::0 2031784 # number of overall misses
system.cpu0.dcache.overall_misses::1 0 # number of overall misses
-system.cpu0.dcache.overall_misses::total 2057371 # number of overall misses
+system.cpu0.dcache.overall_misses::total 2031784 # number of overall misses
system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
system.cpu0.dcache.tagsinuse 504.827058 # Cycle average of tags in use
system.cpu0.dcache.total_refs 13123502 # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks 396793 # number of writebacks
+system.cpu0.dcache.writebacks 419022 # number of writebacks
system.cpu0.dtb.data_accesses 698037 # DTB accesses
system.cpu0.dtb.data_acv 251 # DTB access violations
system.cpu0.dtb.data_hits 15091429 # DTB hits
system.cpu1.dcache.ReadReq_misses::total 41650 # number of ReadReq misses
system.cpu1.dcache.StoreCondReq_accesses::0 16345 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_hits::0 13438 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 13438 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_miss_rate::0 0.177853 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_misses::0 2907 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 2907 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_hits::0 13853 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 13853 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_miss_rate::0 0.152463 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_misses::0 2492 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 2492 # number of StoreCondReq misses
system.cpu1.dcache.WriteReq_accesses::0 733305 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_hits::0 702803 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 702803 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_rate::0 0.041595 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses::0 30502 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 30502 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_hits::0 703732 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 703732 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_rate::0 0.040328 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses::0 29573 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 29573 # number of WriteReq misses
system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks.
system.cpu1.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.dcache.demand_hits::0 1812118 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::0 1813047 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 1812118 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 1813047 # number of demand (read+write) hits
system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate::0 0.038292 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::0 0.037799 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu1.dcache.demand_misses::0 72152 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::0 71223 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 72152 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 71223 # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits::0 1812118 # number of overall hits
+system.cpu1.dcache.overall_hits::0 1813047 # number of overall hits
system.cpu1.dcache.overall_hits::1 0 # number of overall hits
-system.cpu1.dcache.overall_hits::total 1812118 # number of overall hits
+system.cpu1.dcache.overall_hits::total 1813047 # number of overall hits
system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate::0 0.038292 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::0 0.037799 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.dcache.overall_misses::0 72152 # number of overall misses
+system.cpu1.dcache.overall_misses::0 71223 # number of overall misses
system.cpu1.dcache.overall_misses::1 0 # number of overall misses
-system.cpu1.dcache.overall_misses::total 72152 # number of overall misses
+system.cpu1.dcache.overall_misses::total 71223 # number of overall misses
system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use
system.cpu1.dcache.total_refs 1834544 # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks 30848 # number of writebacks
+system.cpu1.dcache.writebacks 31228 # number of writebacks
system.cpu1.dtb.data_accesses 323622 # DTB accesses
system.cpu1.dtb.data_acv 116 # DTB access violations
system.cpu1.dtb.data_hits 1914885 # DTB hits
system.l2c.ReadExReq_accesses::0 282023 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::1 24224 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 306247 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 282023 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1 24224 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 306247 # number of ReadExReq misses
-system.l2c.ReadReq_accesses::0 2581928 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 142339 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2724267 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits::0 1623113 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 136618 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1759731 # number of ReadReq hits
-system.l2c.ReadReq_miss_rate::0 0.371356 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.040193 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 958815 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 5721 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 964536 # number of ReadReq misses
-system.l2c.SCUpgradeReq_accesses::0 26914 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::1 2297 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 29211 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::1 1 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_misses::0 26914 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::1 2297 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 29211 # number of SCUpgradeReq misses
-system.l2c.UpgradeReq_accesses::0 90515 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1 5281 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 95796 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 90515 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1 5281 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 95796 # number of UpgradeReq misses
-system.l2c.Writeback_accesses::0 427641 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 427641 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 427641 # number of Writeback hits
-system.l2c.Writeback_hits::total 427641 # number of Writeback hits
+system.l2c.ReadExReq_hits::0 1653 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::1 139 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 1792 # number of ReadExReq hits
+system.l2c.ReadExReq_miss_rate::0 0.994139 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1 0.994262 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0 280370 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1 24085 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 304455 # number of ReadExReq misses
+system.l2c.ReadReq_accesses::0 2581832 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1 142288 # number of ReadReq accesses(hits+misses)
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+system.l2c.ReadReq_hits::0 1623623 # number of ReadReq hits
+system.l2c.ReadReq_hits::1 136766 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1760389 # number of ReadReq hits
+system.l2c.ReadReq_miss_rate::0 0.371135 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1 0.038809 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0 958209 # number of ReadReq misses
+system.l2c.ReadReq_misses::1 5522 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 963731 # number of ReadReq misses
+system.l2c.SCUpgradeReq_accesses::0 20901 # number of SCUpgradeReq accesses(hits+misses)
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+system.l2c.SCUpgradeReq_accesses::total 22780 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_hits::0 3 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::1 4 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_miss_rate::0 0.999856 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::1 0.997871 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_misses::0 20898 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::1 1875 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 22773 # number of SCUpgradeReq misses
+system.l2c.UpgradeReq_accesses::0 64914 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1 4352 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 69266 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_hits::0 12 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::1 3 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 15 # number of UpgradeReq hits
+system.l2c.UpgradeReq_miss_rate::0 0.999815 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1 0.999311 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0 64902 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1 4349 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 69251 # number of UpgradeReq misses
+system.l2c.Writeback_accesses::0 450250 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 450250 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0 450250 # number of Writeback hits
+system.l2c.Writeback_hits::total 450250 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 1.788900 # Average number of references to valid blocks.
+system.l2c.avg_refs 1.817381 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 2863951 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 166563 # number of demand (read+write) accesses
+system.l2c.demand_accesses::0 2863855 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 166512 # number of demand (read+write) accesses
system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 3030514 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 3030367 # number of demand (read+write) accesses
system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
system.l2c.demand_avg_miss_latency::2 no_value # average overall miss latency
system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.demand_hits::0 1623113 # number of demand (read+write) hits
-system.l2c.demand_hits::1 136618 # number of demand (read+write) hits
+system.l2c.demand_hits::0 1625276 # number of demand (read+write) hits
+system.l2c.demand_hits::1 136905 # number of demand (read+write) hits
system.l2c.demand_hits::2 0 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1759731 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1762181 # number of demand (read+write) hits
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.433261 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.179782 # miss rate for demand accesses
+system.l2c.demand_miss_rate::0 0.432487 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.177807 # miss rate for demand accesses
system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses
system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
-system.l2c.demand_misses::0 1240838 # number of demand (read+write) misses
-system.l2c.demand_misses::1 29945 # number of demand (read+write) misses
+system.l2c.demand_misses::0 1238579 # number of demand (read+write) misses
+system.l2c.demand_misses::1 29607 # number of demand (read+write) misses
system.l2c.demand_misses::2 0 # number of demand (read+write) misses
-system.l2c.demand_misses::total 1270783 # number of demand (read+write) misses
+system.l2c.demand_misses::total 1268186 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.079636 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.003863 # Average percentage of cache occupancy
-system.l2c.occ_%::2 0.382298 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 5219.016701 # Average occupied blocks per context
-system.l2c.occ_blocks::1 253.146931 # Average occupied blocks per context
-system.l2c.occ_blocks::2 25054.312004 # Average occupied blocks per context
-system.l2c.overall_accesses::0 2863951 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 166563 # number of overall (read+write) accesses
+system.l2c.occ_%::0 0.144031 # Average percentage of cache occupancy
+system.l2c.occ_%::1 0.004095 # Average percentage of cache occupancy
+system.l2c.occ_%::2 0.343441 # Average percentage of cache occupancy
+system.l2c.occ_blocks::0 9439.247714 # Average occupied blocks per context
+system.l2c.occ_blocks::1 268.394267 # Average occupied blocks per context
+system.l2c.occ_blocks::2 22507.731761 # Average occupied blocks per context
+system.l2c.overall_accesses::0 2863855 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 166512 # number of overall (read+write) accesses
system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 3030514 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 3030367 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
system.l2c.overall_avg_miss_latency::2 no_value # average overall miss latency
system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 1623113 # number of overall hits
-system.l2c.overall_hits::1 136618 # number of overall hits
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system.l2c.overall_hits::2 0 # number of overall hits
-system.l2c.overall_hits::total 1759731 # number of overall hits
+system.l2c.overall_hits::total 1762181 # number of overall hits
system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.433261 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.179782 # miss rate for overall accesses
+system.l2c.overall_miss_rate::0 0.432487 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.177807 # miss rate for overall accesses
system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses
system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
-system.l2c.overall_misses::0 1240838 # number of overall misses
-system.l2c.overall_misses::1 29945 # number of overall misses
+system.l2c.overall_misses::0 1238579 # number of overall misses
+system.l2c.overall_misses::1 29607 # number of overall misses
system.l2c.overall_misses::2 0 # number of overall misses
-system.l2c.overall_misses::total 1270783 # number of overall misses
+system.l2c.overall_misses::total 1268186 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 1056803 # number of replacements
-system.l2c.sampled_refs 1091452 # Sample count of references to valid blocks.
+system.l2c.replacements 1055565 # number of replacements
+system.l2c.sampled_refs 1090545 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 30526.475636 # Cycle average of tags in use
-system.l2c.total_refs 1952499 # Total number of references to valid blocks.
+system.l2c.tagsinuse 32215.373742 # Cycle average of tags in use
+system.l2c.total_refs 1981936 # Total number of references to valid blocks.
system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 123882 # number of writebacks
+system.l2c.writebacks 123249 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/home/stever/m5/m5_system_2.0b3/binaries/console
+console=/dist/m5/system/binaries/console
init_param=0
-kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
+load_addr_mask=1099511627775
mem_mode=atomic
-pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
+pal=/dist/m5/system/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
[system.disk0.image.child]
type=RawDiskImage
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.terminal]
-Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout
-Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr
+Redirecting stdout to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout
+Redirecting stderr to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jun 16 2010 10:39:13
-M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats
-M5 started Jun 16 2010 10:39:16
-M5 executing on phenom
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
+M5 compiled Aug 26 2010 12:51:14
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 12:51:50
+M5 executing on zizzer
+command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
+ 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1829332258000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 3274924 # Simulator instruction rate (inst/s)
-host_mem_usage 275440 # Number of bytes of host memory used
-host_seconds 18.33 # Real time elapsed on the host
-host_tick_rate 99783911231 # Simulator tick rate (ticks/s)
+host_inst_rate 2897706 # Simulator instruction rate (inst/s)
+host_mem_usage 291728 # Number of bytes of host memory used
+host_seconds 20.72 # Real time elapsed on the host
+host_tick_rate 88290469218 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 60038305 # Number of instructions simulated
sim_seconds 1.829332 # Number of seconds simulated
system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses
system.cpu.dcache.StoreCondReq_accesses::0 199282 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_hits::0 169415 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 169415 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_miss_rate::0 0.149873 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses::0 29867 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 29867 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_hits::0 177079 # number of StoreCondReq hits
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+system.cpu.dcache.StoreCondReq_miss_rate::0 0.111415 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_misses::0 22203 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 22203 # number of StoreCondReq misses
system.cpu.dcache.WriteReq_accesses::0 6152574 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_hits::0 5753150 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 5753150 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_rate::0 0.064920 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses::0 399424 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 399424 # number of WriteReq misses
+system.cpu.dcache.WriteReq_hits::0 5781102 # number of WriteReq hits
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+system.cpu.dcache.WriteReq_miss_rate::0 0.060377 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses::0 371472 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 371472 # number of WriteReq misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 6.870767 # Average number of references to valid blocks.
system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.demand_hits::0 13560932 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::0 13588884 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 13560932 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 13588884 # number of demand (read+write) hits
system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate::0 0.135258 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::0 0.133476 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0 2121129 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::0 2093177 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2121129 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2093177 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0 13560932 # number of overall hits
+system.cpu.dcache.overall_hits::0 13588884 # number of overall hits
system.cpu.dcache.overall_hits::1 0 # number of overall hits
-system.cpu.dcache.overall_hits::total 13560932 # number of overall hits
+system.cpu.dcache.overall_hits::total 13588884 # number of overall hits
system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate::0 0.135258 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::0 0.133476 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.overall_misses::0 2121129 # number of overall misses
+system.cpu.dcache.overall_misses::0 2093177 # number of overall misses
system.cpu.dcache.overall_misses::1 0 # number of overall misses
-system.cpu.dcache.overall_misses::total 2121129 # number of overall misses
+system.cpu.dcache.overall_misses::total 2093177 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use
system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 428893 # number of writebacks
+system.cpu.dcache.writebacks 450979 # number of writebacks
system.cpu.dtb.data_accesses 1020787 # DTB accesses
system.cpu.dtb.data_acv 367 # DTB access violations
system.cpu.dtb.data_hits 16062925 # DTB hits
system.iocache.writebacks 41512 # number of writebacks
system.l2c.ReadExReq_accesses::0 304346 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 304346 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 304346 # number of ReadExReq misses
+system.l2c.ReadExReq_hits::0 1965 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 1965 # number of ReadExReq hits
+system.l2c.ReadExReq_miss_rate::0 0.993544 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0 302381 # number of ReadExReq misses
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system.l2c.ReadReq_accesses::0 2659071 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2659071 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_hits::0 1696652 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1696652 # number of ReadReq hits
-system.l2c.ReadReq_miss_rate::0 0.361938 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 962419 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 962419 # number of ReadReq misses
-system.l2c.SCUpgradeReq_accesses::0 29867 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 29867 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadReq_hits::0 1697753 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1697753 # number of ReadReq hits
+system.l2c.ReadReq_miss_rate::0 0.361524 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0 961318 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 961318 # number of ReadReq misses
+system.l2c.SCUpgradeReq_accesses::0 22203 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 22203 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_misses::0 29867 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 29867 # number of SCUpgradeReq misses
-system.l2c.UpgradeReq_accesses::0 95078 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 95078 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_misses::0 22203 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 22203 # number of SCUpgradeReq misses
+system.l2c.UpgradeReq_accesses::0 67126 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 67126 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 95078 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 95078 # number of UpgradeReq misses
-system.l2c.Writeback_accesses::0 428893 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 428893 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 428893 # number of Writeback hits
-system.l2c.Writeback_hits::total 428893 # number of Writeback hits
+system.l2c.UpgradeReq_misses::0 67126 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 67126 # number of UpgradeReq misses
+system.l2c.Writeback_accesses::0 450979 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 450979 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0 450979 # number of Writeback hits
+system.l2c.Writeback_hits::total 450979 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 1.727246 # Average number of references to valid blocks.
+system.l2c.avg_refs 1.759381 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.demand_avg_miss_latency::1 no_value # average overall miss latency
system.l2c.demand_avg_miss_latency::total no_value # average overall miss latency
system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.demand_hits::0 1696652 # number of demand (read+write) hits
+system.l2c.demand_hits::0 1699718 # number of demand (read+write) hits
system.l2c.demand_hits::1 0 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1696652 # number of demand (read+write) hits
+system.l2c.demand_hits::total 1699718 # number of demand (read+write) hits
system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.427468 # miss rate for demand accesses
+system.l2c.demand_miss_rate::0 0.426433 # miss rate for demand accesses
system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses
system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
-system.l2c.demand_misses::0 1266765 # number of demand (read+write) misses
+system.l2c.demand_misses::0 1263699 # number of demand (read+write) misses
system.l2c.demand_misses::1 0 # number of demand (read+write) misses
-system.l2c.demand_misses::total 1266765 # number of demand (read+write) misses
+system.l2c.demand_misses::total 1263699 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.077203 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.384049 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 5059.576308 # Average occupied blocks per context
-system.l2c.occ_blocks::1 25169.009297 # Average occupied blocks per context
+system.l2c.occ_%::0 0.141683 # Average percentage of cache occupancy
+system.l2c.occ_%::1 0.342776 # Average percentage of cache occupancy
+system.l2c.occ_blocks::0 9285.312813 # Average occupied blocks per context
+system.l2c.occ_blocks::1 22464.151503 # Average occupied blocks per context
system.l2c.overall_accesses::0 2963417 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2963417 # number of overall (read+write) accesses
system.l2c.overall_avg_miss_latency::total no_value # average overall miss latency
system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 1696652 # number of overall hits
+system.l2c.overall_hits::0 1699718 # number of overall hits
system.l2c.overall_hits::1 0 # number of overall hits
-system.l2c.overall_hits::total 1696652 # number of overall hits
+system.l2c.overall_hits::total 1699718 # number of overall hits
system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.427468 # miss rate for overall accesses
+system.l2c.overall_miss_rate::0 0.426433 # miss rate for overall accesses
system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses
system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
-system.l2c.overall_misses::0 1266765 # number of overall misses
+system.l2c.overall_misses::0 1263699 # number of overall misses
system.l2c.overall_misses::1 0 # number of overall misses
-system.l2c.overall_misses::total 1266765 # number of overall misses
+system.l2c.overall_misses::total 1263699 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 1050724 # number of replacements
-system.l2c.sampled_refs 1081067 # Sample count of references to valid blocks.
+system.l2c.replacements 1048986 # number of replacements
+system.l2c.sampled_refs 1079842 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 30228.585605 # Cycle average of tags in use
-system.l2c.total_refs 1867269 # Total number of references to valid blocks.
+system.l2c.tagsinuse 31749.464316 # Cycle average of tags in use
+system.l2c.total_refs 1899854 # Total number of references to valid blocks.
system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 119147 # number of writebacks
+system.l2c.writebacks 118452 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/home/stever/m5/m5_system_2.0b3/binaries/console
+console=/dist/m5/system/binaries/console
init_param=0
-kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
+load_addr_mask=1099511627775
mem_mode=timing
-pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
+pal=/dist/m5/system/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
[system.disk0.image.child]
type=RawDiskImage
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.terminal]
-Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout
-Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr
+Redirecting stdout to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout
+Redirecting stderr to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jun 16 2010 10:39:13
-M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats
-M5 started Jun 16 2010 10:43:55
-M5 executing on phenom
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
+M5 compiled Aug 26 2010 12:51:14
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 12:51:18
+M5 executing on zizzer
+command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
+ 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-info: Launching CPU 1 @ 591544000
-Exiting @ tick 1972135461000 because m5_exit instruction encountered
+info: Launching CPU 1 @ 591240000
+Exiting @ tick 1967163347000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 1520606 # Simulator instruction rate (inst/s)
-host_mem_usage 273632 # Number of bytes of host memory used
-host_seconds 39.08 # Real time elapsed on the host
-host_tick_rate 50467758461 # Simulator tick rate (ticks/s)
+host_inst_rate 1510892 # Simulator instruction rate (inst/s)
+host_mem_usage 289944 # Number of bytes of host memory used
+host_seconds 40.42 # Real time elapsed on the host
+host_tick_rate 48670449492 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 59420593 # Number of instructions simulated
-sim_seconds 1.972135 # Number of seconds simulated
-sim_ticks 1972135461000 # Number of ticks simulated
-system.cpu0.dcache.LoadLockedReq_accesses::0 192630 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 192630 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14259.465279 # average LoadLockedReq miss latency
+sim_insts 61066894 # Number of instructions simulated
+sim_seconds 1.967163 # Number of seconds simulated
+sim_ticks 1967163347000 # Number of ticks simulated
+system.cpu0.dcache.LoadLockedReq_accesses::0 150276 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 150276 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 11859.655689 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11259.465279 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_hits::0 175911 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 175911 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_miss_latency 238404000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.086793 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses::0 16719 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 16719 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 188247000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.086793 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 8859.655689 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_hits::0 136916 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 136916 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_miss_latency 158445000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.088903 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses::0 13360 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 13360 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 118365000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.088903 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_misses 16719 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.ReadReq_accesses::0 8488393 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 8488393 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency::0 25694.266311 # average ReadReq miss latency
+system.cpu0.dcache.LoadLockedReq_mshr_misses 13360 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.ReadReq_accesses::0 7279990 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 7279990 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency::0 26932.541490 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22694.226839 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23932.489517 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_hits::0 7449690 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 7449690 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency 26688711500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate::0 0.122367 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses::0 1038703 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 1038703 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency 23572561500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122367 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_hits::0 6346809 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 6346809 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_latency 25132936000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_rate::0 0.128184 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses::0 933181 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 933181 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency 22333344500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.128184 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses 1038703 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 883604000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.StoreCondReq_accesses::0 191666 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 191666 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 55344.484086 # average StoreCondReq miss latency
+system.cpu0.dcache.ReadReq_mshr_misses 933181 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 883599000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_accesses::0 149766 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 149766 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 42774.669320 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 52344.484086 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_hits::0 163357 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 163357 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_latency 1566747000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_rate::0 0.147700 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_misses::0 28309 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 28309 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1481820000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.147700 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 39774.669320 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_hits::0 132680 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 132680 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_miss_latency 730848000 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_rate::0 0.114085 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_misses::0 17086 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 17086 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency 679590000 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.114085 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_misses 28309 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses::0 5847430 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 5847430 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency::0 55891.373878 # average WriteReq miss latency
+system.cpu0.dcache.StoreCondReq_mshr_misses 17086 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.WriteReq_accesses::0 4822937 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 4822937 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_avg_miss_latency::0 54619.723929 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 52891.373878 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 51619.723929 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_hits::0 5468175 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 5468175 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency 21197083000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate::0 0.064858 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses::0 379255 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 379255 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_miss_latency 20059318000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.064858 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_hits::0 4533446 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 4533446 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency 15811918500 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate::0 0.060024 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses::0 289491 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 289491 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_miss_latency 14943445500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.060024 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses 379255 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1240870000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_misses 289491 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1351640000 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs 9.990826 # Average number of references to valid blocks.
+system.cpu0.dcache.avg_refs 9.594836 # Average number of references to valid blocks.
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.demand_accesses::0 14335823 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::0 12102927 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 14335823 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency::0 33770.954076 # average overall miss latency
+system.cpu0.dcache.demand_accesses::total 12102927 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency::0 33488.011912 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 30770.925161 # average overall mshr miss latency
-system.cpu0.dcache.demand_hits::0 12917865 # number of demand (read+write) hits
+system.cpu0.dcache.demand_avg_mshr_miss_latency 30487.972244 # average overall mshr miss latency
+system.cpu0.dcache.demand_hits::0 10880255 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 12917865 # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency 47885794500 # number of demand (read+write) miss cycles
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+system.cpu0.kern.callpal::total 146277 # number of callpals executed
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.hwrei 202896 # number of hwrei instructions executed
-system.cpu0.kern.inst.quiesce 6369 # number of quiesce instructions executed
-system.cpu0.kern.ipl_count::0 72641 40.60% 40.60% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 131 0.07% 40.68% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::22 1987 1.11% 41.79% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 6 0.00% 41.79% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 104141 58.21% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 178906 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 71272 49.27% 49.27% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 131 0.09% 49.36% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::22 1987 1.37% 50.73% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::30 6 0.00% 50.74% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 71266 49.26% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 144662 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1908230091000 96.76% 96.76% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 96186500 0.00% 96.76% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 576952000 0.03% 96.79% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 5442500 0.00% 96.79% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 63226031000 3.21% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1972134703000 # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used::0 0.981154 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.inst.hwrei 161605 # number of hwrei instructions executed
+system.cpu0.kern.inst.quiesce 6835 # number of quiesce instructions executed
+system.cpu0.kern.ipl_count::0 55380 40.11% 40.11% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21 131 0.09% 40.21% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::22 1982 1.44% 41.64% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::30 455 0.33% 41.97% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 80115 58.03% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 138063 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 54908 49.06% 49.06% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21 131 0.12% 49.17% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::22 1982 1.77% 50.94% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::30 455 0.41% 51.35% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::31 54453 48.65% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total 111929 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1909262510000 97.06% 97.06% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 87868000 0.00% 97.06% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 573921000 0.03% 97.09% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30 337802000 0.02% 97.11% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 56900501000 2.89% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1967162602000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used::0 0.991477 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.684322 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31 0.679685 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.mode_good::kernel 1231
system.cpu0.kern.mode_good::user 1232
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch::kernel 7237 # number of protection mode switches
+system.cpu0.kern.mode_switch::kernel 6788 # number of protection mode switches
system.cpu0.kern.mode_switch::user 1232 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
-system.cpu0.kern.mode_switch_good::kernel 0.170098 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.181349 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1968330503000 99.81% 99.81% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 3804198000 0.19% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::kernel 1963346065000 99.81% 99.81% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 3816535000 0.19% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context 3869 # number of times the context was actually changed
+system.cpu0.kern.swap_context 2976 # number of times the context was actually changed
system.cpu0.kern.syscall::2 6 2.68% 2.68% # number of syscalls executed
system.cpu0.kern.syscall::3 19 8.48% 11.16% # number of syscalls executed
system.cpu0.kern.syscall::4 3 1.34% 12.50% # number of syscalls executed
system.cpu0.kern.syscall::144 1 0.45% 99.11% # number of syscalls executed
system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed
system.cpu0.kern.syscall::total 224 # number of syscalls executed
-system.cpu0.not_idle_fraction 0.066840 # Percentage of non-idle cycles
-system.cpu0.numCycles 3944270922 # number of cpu cycles simulated
-system.cpu0.num_insts 54155641 # Number of instructions executed
-system.cpu0.num_refs 14946215 # Number of memory references
-system.cpu1.dcache.LoadLockedReq_accesses::0 12334 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 12334 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13303.501946 # average LoadLockedReq miss latency
+system.cpu0.not_idle_fraction 0.056942 # Percentage of non-idle cycles
+system.cpu0.numCycles 3934326694 # number of cpu cycles simulated
+system.cpu0.num_insts 47245816 # Number of instructions executed
+system.cpu0.num_refs 12627213 # Number of memory references
+system.cpu1.dcache.LoadLockedReq_accesses::0 61432 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 61432 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 10283.624203 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10303.501946 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_hits::0 11306 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 11306 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_miss_latency 13676000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.083347 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_misses::0 1028 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 1028 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10592000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.083347 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 7283.624203 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_hits::0 51863 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 51863 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_miss_latency 98404000 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.155766 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_misses::0 9569 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 9569 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 69697000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.155766 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_misses 1028 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.ReadReq_accesses::0 1020543 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 1020543 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency::0 15771.782317 # average ReadReq miss latency
+system.cpu1.dcache.LoadLockedReq_mshr_misses 9569 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.ReadReq_accesses::0 2468175 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 2468175 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_avg_miss_latency::0 13829.556740 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12771.684387 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10829.528932 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_hits::0 984803 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 984803 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_latency 563683500 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_rate::0 0.035021 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses::0 35740 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 35740 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency 456460000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035021 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_hits::0 2342312 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 2342312 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_latency 1740629500 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_rate::0 0.050994 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses::0 125863 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 125863 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency 1363037000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.050994 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_misses 35740 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses 125863 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 12526000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.StoreCondReq_accesses::0 12270 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 12270 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 46841.453344 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_accesses::0 60921 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 60921 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 35881.530265 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 43841.453344 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_hits::0 9848 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 9848 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_miss_latency 113450000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_rate::0 0.197392 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_misses::0 2422 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 2422 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency 106184000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.197392 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 32881.530265 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_hits::0 47407 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 47407 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_miss_latency 484903000 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_rate::0 0.221828 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_misses::0 13514 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 13514 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency 444361000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.221828 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_misses 2422 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.WriteReq_accesses::0 650008 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 650008 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency::0 54644.846691 # average WriteReq miss latency
+system.cpu1.dcache.StoreCondReq_mshr_misses 13514 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.WriteReq_accesses::0 1805806 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 1805806 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_avg_miss_latency::0 52324.342254 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 51644.846691 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 49324.342254 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_hits::0 623656 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 623656 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_latency 1440001000 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_rate::0 0.040541 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses::0 26352 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 26352 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_mshr_miss_latency 1360945000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.040541 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_hits::0 1713103 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 1713103 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_latency 4850623500 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_rate::0 0.051336 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses::0 92703 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 92703 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_mshr_miss_latency 4572514500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.051336 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_misses 26352 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 303019000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_misses 92703 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 413889500 # number of WriteReq MSHR uncacheable cycles
system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs 30.141759 # Average number of references to valid blocks.
+system.cpu1.dcache.avg_refs 23.182705 # Average number of references to valid blocks.
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.demand_accesses::0 1670551 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::0 4273981 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 1670551 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency::0 32269.608001 # average overall miss latency
+system.cpu1.dcache.demand_accesses::total 4273981 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency::0 30156.808470 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 29269.551633 # average overall mshr miss latency
-system.cpu1.dcache.demand_hits::0 1608459 # number of demand (read+write) hits
+system.cpu1.dcache.demand_avg_mshr_miss_latency 27156.792456 # average overall mshr miss latency
+system.cpu1.dcache.demand_hits::0 4055415 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 1608459 # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency 2003684500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate::0 0.037169 # miss rate for demand accesses
+system.cpu1.dcache.demand_hits::total 4055415 # number of demand (read+write) hits
+system.cpu1.dcache.demand_miss_latency 6591253000 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_rate::0 0.051139 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu1.dcache.demand_misses::0 62092 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::0 218566 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 62092 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 218566 # number of demand (read+write) misses
system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency 1817405000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate::0 0.037169 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_latency 5935551500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_rate::0 0.051139 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses 62092 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses 218566 # number of demand (read+write) MSHR misses
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0 0.759529 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_blocks::0 388.878897 # Average occupied blocks per context
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+system.cpu1.dcache.occ_%::0 0.916301 # Average percentage of cache occupancy
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system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
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system.cpu1.icache.writebacks 0 # number of writebacks
-system.cpu1.idle_fraction 0.994655 # Percentage of idle cycles
+system.cpu1.idle_fraction 0.984741 # Percentage of idle cycles
system.cpu1.itb.data_accesses 0 # DTB accesses
system.cpu1.itb.data_acv 0 # DTB access violations
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system.cpu1.itb.data_misses 0 # DTB misses
-system.cpu1.itb.fetch_accesses 1397517 # ITB accesses
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system.cpu1.itb.fetch_acv 41 # ITB acv
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system.cpu1.itb.write_hits 0 # DTB write hits
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system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
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+system.cpu1.kern.callpal::total 75623 # number of callpals executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
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-system.cpu1.kern.ipl_count::0 9173 31.84% 31.84% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::22 1980 6.87% 38.71% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::30 91 0.32% 39.03% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::31 17566 60.97% 100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count::total 28810 # number of times we switched to this ipl
-system.cpu1.kern.ipl_good::0 9165 45.13% 45.13% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::22 1980 9.75% 54.87% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::30 91 0.45% 55.32% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::31 9074 44.68% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good::total 20310 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1927968787500 97.78% 97.78% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 511194500 0.03% 97.81% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 58584000 0.00% 97.81% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 43145271000 2.19% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1971683837000 # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used::0 0.999128 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.hwrei 82618 # number of hwrei instructions executed
+system.cpu1.kern.inst.quiesce 2771 # number of quiesce instructions executed
+system.cpu1.kern.ipl_count::0 28203 38.56% 38.56% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::22 1977 2.70% 41.27% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::30 540 0.74% 42.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::31 42416 58.00% 100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count::total 73136 # number of times we switched to this ipl
+system.cpu1.kern.ipl_good::0 27298 48.25% 48.25% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::22 1977 3.49% 51.75% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::30 540 0.95% 52.70% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::31 26759 47.30% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good::total 56574 # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks::0 1915291540500 97.38% 97.38% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 515904000 0.03% 97.41% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 422495500 0.02% 97.43% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 50571037000 2.57% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1966800977000 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used::0 0.967911 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used::31 0.516566 # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.mode_good::kernel 532
-system.cpu1.kern.mode_good::user 516
-system.cpu1.kern.mode_good::idle 16
-system.cpu1.kern.mode_switch::kernel 880 # number of protection mode switches
-system.cpu1.kern.mode_switch::user 516 # number of protection mode switches
-system.cpu1.kern.mode_switch::idle 2081 # number of protection mode switches
-system.cpu1.kern.mode_switch_good::kernel 0.604545 # fraction of useful protection mode switches
+system.cpu1.kern.ipl_used::31 0.630870 # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.mode_good::kernel 981
+system.cpu1.kern.mode_good::user 517
+system.cpu1.kern.mode_good::idle 464
+system.cpu1.kern.mode_switch::kernel 2246 # number of protection mode switches
+system.cpu1.kern.mode_switch::user 517 # number of protection mode switches
+system.cpu1.kern.mode_switch::idle 2954 # number of protection mode switches
+system.cpu1.kern.mode_switch_good::kernel 0.436776 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::idle 0.007689 # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good::total 1.612234 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 4596640000 0.23% 0.23% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 1703543000 0.09% 0.32% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1964670722000 99.68% 100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context 366 # number of times the context was actually changed
+system.cpu1.kern.mode_switch_good::idle 0.157075 # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good::total 1.593852 # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks::kernel 23054472000 1.17% 1.17% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user 1704524000 0.09% 1.26% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle 1941246244000 98.74% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context 2160 # number of times the context was actually changed
system.cpu1.kern.syscall::2 2 1.96% 1.96% # number of syscalls executed
system.cpu1.kern.syscall::3 11 10.78% 12.75% # number of syscalls executed
system.cpu1.kern.syscall::4 1 0.98% 13.73% # number of syscalls executed
system.cpu1.kern.syscall::132 2 1.96% 99.02% # number of syscalls executed
system.cpu1.kern.syscall::144 1 0.98% 100.00% # number of syscalls executed
system.cpu1.kern.syscall::total 102 # number of syscalls executed
-system.cpu1.not_idle_fraction 0.005345 # Percentage of non-idle cycles
-system.cpu1.numCycles 3943367734 # number of cpu cycles simulated
-system.cpu1.num_insts 5264952 # Number of instructions executed
-system.cpu1.num_refs 1703740 # Number of memory references
+system.cpu1.not_idle_fraction 0.015259 # Percentage of non-idle cycles
+system.cpu1.numCycles 3933602014 # number of cpu cycles simulated
+system.cpu1.num_insts 13821078 # Number of instructions executed
+system.cpu1.num_refs 4410345 # Number of memory references
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.iocache.ReadReq_accesses::1 178 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::1 174 # number of ReadReq accesses(hits+misses)
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system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 115196.617978 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::1 115247.114943 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency 63196.617978 # average ReadReq mshr miss latency
-system.iocache.ReadReq_miss_latency 20504998 # number of ReadReq miss cycles
+system.iocache.ReadReq_avg_mshr_miss_latency 63247.114943 # average ReadReq mshr miss latency
+system.iocache.ReadReq_miss_latency 20052998 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_misses::1 178 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 178 # number of ReadReq misses
-system.iocache.ReadReq_mshr_miss_latency 11248998 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_misses::1 174 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
+system.iocache.ReadReq_mshr_miss_latency 11004998 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_misses 178 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses 174 # number of ReadReq MSHR misses
system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137902.310503 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137872.733106 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85898.702349 # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency 5730116806 # number of WriteReq miss cycles
+system.iocache.WriteReq_avg_mshr_miss_latency 85869.242491 # average WriteReq mshr miss latency
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system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency 3569262880 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency 3568038764 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles::no_mshrs 6169.706090 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 6165.774548 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs 64528956 # number of cycles access was blocked
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system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 41730 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 41730 # number of demand (read+write) accesses
+system.iocache.demand_accesses::1 41726 # number of demand (read+write) accesses
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system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137805.458998 # average overall miss latency
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system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 85801.866235 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 85774.906821 # average overall mshr miss latency
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 5750621804 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency 5748940804 # number of demand (read+write) miss cycles
system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 41730 # number of demand (read+write) misses
-system.iocache.demand_misses::total 41730 # number of demand (read+write) misses
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+system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency 3580511878 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency 3579043762 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.iocache.demand_mshr_misses 41730 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses 41726 # number of demand (read+write) MSHR misses
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.occ_%::1 0.036380 # Average percentage of cache occupancy
-system.iocache.occ_blocks::1 0.582075 # Average occupied blocks per context
+system.iocache.occ_%::1 0.036248 # Average percentage of cache occupancy
+system.iocache.occ_blocks::1 0.579966 # Average occupied blocks per context
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 41730 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 41730 # number of overall (read+write) accesses
+system.iocache.overall_accesses::1 41726 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137805.458998 # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 137778.382879 # average overall miss latency
system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 85801.866235 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 85774.906821 # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.iocache.overall_hits::0 0 # number of overall hits
system.iocache.overall_hits::1 0 # number of overall hits
system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.overall_miss_latency 5750621804 # number of overall miss cycles
+system.iocache.overall_miss_latency 5748940804 # number of overall miss cycles
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 41730 # number of overall misses
-system.iocache.overall_misses::total 41730 # number of overall misses
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system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency 3580511878 # number of overall MSHR miss cycles
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system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.iocache.overall_mshr_misses 41730 # number of overall MSHR misses
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system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.replacements 41698 # number of replacements
-system.iocache.sampled_refs 41714 # Sample count of references to valid blocks.
+system.iocache.replacements 41694 # number of replacements
+system.iocache.sampled_refs 41710 # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 0.582075 # Cycle average of tags in use
+system.iocache.tagsinuse 0.579966 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.warmup_cycle 1762323389000 # Cycle when the warmup percentage was hit.
+system.iocache.warmup_cycle 1759378217000 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 41520 # number of writebacks
-system.l2c.ReadExReq_accesses::0 285538 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1 21276 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 306814 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 55877.476903 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 749912.718556 # average ReadExReq miss latency
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+system.l2c.ReadExReq_avg_miss_latency::1 252326.309748 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40002.656333 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency 15955143000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 285538 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1 21276 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 306814 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 12273375000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0 1.074512 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1 14.420662 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_avg_mshr_miss_latency 40003.055004 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_hits::0 1864 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::1 187 # number of ReadExReq hits
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+system.l2c.ReadExReq_miss_latency 15388120000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate::0 0.992128 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1 0.996943 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0 234923 # number of ReadExReq misses
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+system.l2c.ReadExReq_misses::total 295908 # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency 11837224000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate::0 1.249680 # mshr miss rate for ReadExReq accesses
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system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 306814 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0 1969770 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 120535 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2090305 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0 52549.257150 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 5128541.212316 # average ReadReq miss latency
+system.l2c.ReadExReq_mshr_misses 295908 # number of ReadExReq MSHR misses
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+system.l2c.ReadReq_avg_miss_latency::1 5017624.332810 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40016.323583 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40016.414894 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0 1665469 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 117417 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1782886 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 15990791500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0 0.154486 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.025868 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 304301 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 3118 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 307419 # number of ReadReq misses
-system.l2c.ReadReq_mshr_hits 11 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency 12301338000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.156063 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 2.550363 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_hits::0 1310657 # number of ReadReq hits
+system.l2c.ReadReq_hits::1 450994 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1761651 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 15981133500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate::0 0.188299 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1 0.007013 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0 304048 # number of ReadReq misses
+system.l2c.ReadReq_misses::1 3185 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 307233 # number of ReadReq misses
+system.l2c.ReadReq_mshr_hits 12 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_miss_latency 12293883000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::0 0.190264 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1 0.676432 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 307408 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency 802543000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.SCUpgradeReq_accesses::0 27944 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::1 1988 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 29932 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_avg_miss_latency::0 55471.228171 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::1 779722.334004 # average SCUpgradeReq miss latency
+system.l2c.ReadReq_mshr_misses 307221 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency 802535000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.SCUpgradeReq_accesses::0 12669 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::1 8188 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 20857 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_avg_miss_latency::0 78597.820938 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::1 121582.804104 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40002.405452 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_miss_latency 1550088000 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40004.028004 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_hits::0 3 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_miss_latency 995520000 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_rate::0 0.999763 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::1 1 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_misses::0 27944 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::1 1988 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 29932 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_mshr_miss_latency 1197352000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.071142 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::1 15.056338 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_misses::0 12666 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::1 8188 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 20854 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_mshr_miss_latency 834244000 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.646065 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::1 2.546898 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_misses 29932 # number of SCUpgradeReq MSHR misses
-system.l2c.UpgradeReq_accesses::0 92926 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1 4380 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 97306 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0 52795.955922 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 1120118.036530 # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_mshr_misses 20854 # number of SCUpgradeReq MSHR misses
+system.l2c.UpgradeReq_accesses::0 46404 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1 25015 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 71419 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0 74757.458826 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1 138647.409244 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40006.114731 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency 4906117000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 92926 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1 4380 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 97306 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency 3892835000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0 1.047134 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1 22.215982 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40008.977591 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_hits::0 16 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::1 3 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 19 # number of UpgradeReq hits
+system.l2c.UpgradeReq_miss_latency 3467849000 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_rate::0 0.999655 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1 0.999880 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0 46388 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1 25012 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 71400 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency 2856641000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate::0 1.538660 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1 2.854287 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 97306 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses 71400 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 1394774000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0 430351 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 430351 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 430351 # number of Writeback hits
-system.l2c.Writeback_hits::total 430351 # number of Writeback hits
+system.l2c.WriteReq_mshr_uncacheable_latency 1594965500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses::0 436372 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 436372 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0 436372 # number of Writeback hits
+system.l2c.Writeback_hits::total 436372 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 4.554189 # Average number of references to valid blocks.
+system.l2c.avg_refs 4.549954 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 2255308 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 141811 # number of demand (read+write) accesses
+system.l2c.demand_accesses::0 1851492 # number of demand (read+write) accesses
+system.l2c.demand_accesses::1 515351 # number of demand (read+write) accesses
system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2397119 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 54160.431067 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 1309581.638928 # average overall miss latency
+system.l2c.demand_accesses::total 2366843 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0 58202.117554 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 488846.088515 # average overall miss latency
system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency
system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40009.496566 # average overall mshr miss latency
-system.l2c.demand_hits::0 1665469 # number of demand (read+write) hits
-system.l2c.demand_hits::1 117417 # number of demand (read+write) hits
+system.l2c.demand_avg_mshr_miss_latency 40009.860245 # average overall mshr miss latency
+system.l2c.demand_hits::0 1312521 # number of demand (read+write) hits
+system.l2c.demand_hits::1 451181 # number of demand (read+write) hits
system.l2c.demand_hits::2 0 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1782886 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 31945934500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.261534 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.172018 # miss rate for demand accesses
+system.l2c.demand_hits::total 1763702 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 31369253500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0 0.291101 # miss rate for demand accesses
+system.l2c.demand_miss_rate::1 0.124517 # miss rate for demand accesses
system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses
system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
-system.l2c.demand_misses::0 589839 # number of demand (read+write) misses
-system.l2c.demand_misses::1 24394 # number of demand (read+write) misses
+system.l2c.demand_misses::0 538971 # number of demand (read+write) misses
+system.l2c.demand_misses::1 64170 # number of demand (read+write) misses
system.l2c.demand_misses::2 0 # number of demand (read+write) misses
-system.l2c.demand_misses::total 614233 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 11 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 24574713000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0.272345 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 4.331272 # mshr miss rate for demand accesses
+system.l2c.demand_misses::total 603141 # number of demand (read+write) misses
+system.l2c.demand_mshr_hits 12 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency 24131107000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0 0.325753 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 1.170327 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 614222 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses 603129 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.090499 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.002713 # Average percentage of cache occupancy
-system.l2c.occ_%::2 0.377667 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 5930.966720 # Average occupied blocks per context
-system.l2c.occ_blocks::1 177.784506 # Average occupied blocks per context
-system.l2c.occ_blocks::2 24750.754224 # Average occupied blocks per context
-system.l2c.overall_accesses::0 2255308 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 141811 # number of overall (read+write) accesses
+system.l2c.occ_%::0 0.162138 # Average percentage of cache occupancy
+system.l2c.occ_%::1 0.003912 # Average percentage of cache occupancy
+system.l2c.occ_%::2 0.340573 # Average percentage of cache occupancy
+system.l2c.occ_blocks::0 10625.898715 # Average occupied blocks per context
+system.l2c.occ_blocks::1 256.359763 # Average occupied blocks per context
+system.l2c.occ_blocks::2 22319.780586 # Average occupied blocks per context
+system.l2c.overall_accesses::0 1851492 # number of overall (read+write) accesses
+system.l2c.overall_accesses::1 515351 # number of overall (read+write) accesses
system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2397119 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 54160.431067 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 1309581.638928 # average overall miss latency
+system.l2c.overall_accesses::total 2366843 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0 58202.117554 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 488846.088515 # average overall miss latency
system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency
system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40009.496566 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40009.860245 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 1665469 # number of overall hits
-system.l2c.overall_hits::1 117417 # number of overall hits
+system.l2c.overall_hits::0 1312521 # number of overall hits
+system.l2c.overall_hits::1 451181 # number of overall hits
system.l2c.overall_hits::2 0 # number of overall hits
-system.l2c.overall_hits::total 1782886 # number of overall hits
-system.l2c.overall_miss_latency 31945934500 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.261534 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.172018 # miss rate for overall accesses
+system.l2c.overall_hits::total 1763702 # number of overall hits
+system.l2c.overall_miss_latency 31369253500 # number of overall miss cycles
+system.l2c.overall_miss_rate::0 0.291101 # miss rate for overall accesses
+system.l2c.overall_miss_rate::1 0.124517 # miss rate for overall accesses
system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses
system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
-system.l2c.overall_misses::0 589839 # number of overall misses
-system.l2c.overall_misses::1 24394 # number of overall misses
+system.l2c.overall_misses::0 538971 # number of overall misses
+system.l2c.overall_misses::1 64170 # number of overall misses
system.l2c.overall_misses::2 0 # number of overall misses
-system.l2c.overall_misses::total 614233 # number of overall misses
-system.l2c.overall_mshr_hits 11 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 24574713000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 0.272345 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 4.331272 # mshr miss rate for overall accesses
+system.l2c.overall_misses::total 603141 # number of overall misses
+system.l2c.overall_mshr_hits 12 # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency 24131107000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0 0.325753 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 1.170327 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 614222 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 2197317000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_misses 603129 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 2397500500 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 399005 # number of replacements
-system.l2c.sampled_refs 430732 # Sample count of references to valid blocks.
+system.l2c.replacements 398396 # number of replacements
+system.l2c.sampled_refs 431420 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 30859.505450 # Cycle average of tags in use
-system.l2c.total_refs 1961635 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 10912833000 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 123162 # number of writebacks
+system.l2c.tagsinuse 33202.039064 # Cycle average of tags in use
+system.l2c.total_refs 1962941 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 10911264000 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 122806 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/home/stever/m5/m5_system_2.0b3/binaries/console
+console=/dist/m5/system/binaries/console
init_param=0
-kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
+load_addr_mask=1099511627775
mem_mode=timing
-pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal
+pal=/dist/m5/system/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
[system.disk0.image.child]
type=RawDiskImage
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.terminal]
-Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simout
-Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr
+Redirecting stdout to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simout
+Redirecting stderr to build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jun 16 2010 10:39:13
-M5 revision b85fd4ba5453 7466 default qtip tip llsc-fix-stats
-M5 started Jun 16 2010 10:44:55
-M5 executing on phenom
-command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing
+M5 compiled Aug 26 2010 12:51:14
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 12:51:16
+M5 executing on zizzer
+command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
+ 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1930164593000 because m5_exit instruction encountered
+Exiting @ tick 1927951878000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-host_inst_rate 1511189 # Simulator instruction rate (inst/s)
-host_mem_usage 272256 # Number of bytes of host memory used
-host_seconds 37.19 # Real time elapsed on the host
-host_tick_rate 51895589412 # Simulator tick rate (ticks/s)
+host_inst_rate 1563603 # Simulator instruction rate (inst/s)
+host_mem_usage 288804 # Number of bytes of host memory used
+host_seconds 35.93 # Real time elapsed on the host
+host_tick_rate 53658174093 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 56205703 # Number of instructions simulated
-sim_seconds 1.930165 # Number of seconds simulated
-sim_ticks 1930164593000 # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses::0 200404 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 200404 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14361.546017 # average LoadLockedReq miss latency
+sim_insts 56180319 # Number of instructions simulated
+sim_seconds 1.927952 # Number of seconds simulated
+sim_ticks 1927951878000 # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses::0 200373 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 200373 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14335.708080 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11361.546017 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits::0 183095 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 183095 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency 248584000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.086371 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses::0 17309 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 17309 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency 196657000 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.086371 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11335.708080 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_hits::0 183108 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 183108 # number of LoadLockedReq hits
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+system.cpu.dcache.LoadLockedReq_misses::total 17265 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency 195711000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.086164 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_misses 17309 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses::0 8888653 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 8888653 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency::0 25452.354477 # average ReadReq miss latency
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+system.cpu.dcache.ReadReq_accesses::0 8883579 # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.ReadReq_avg_miss_latency::0 25418.459915 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22452.311493 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22418.417380 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits::0 7818479 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 7818479 # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency 27238448000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate::0 0.120398 # miss rate for ReadReq accesses
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-system.cpu.dcache.ReadReq_misses::total 1070174 # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 24027880000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.120398 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_hits::0 7813872 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 7813872 # number of ReadReq hits
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system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses 1070174 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_uncacheable_latency 862763000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses::0 199383 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 199383 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_avg_miss_latency::0 56004.366085 # average StoreCondReq miss latency
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system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.366085 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_hits::0 169379 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 169379 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_miss_latency 1680355000 # number of StoreCondReq miss cycles
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-system.cpu.dcache.StoreCondReq_misses::0 30004 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 30004 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_mshr_miss_latency 1590343000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.150484 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 53004.626718 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_hits::0 177090 # number of StoreCondReq hits
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+system.cpu.dcache.StoreCondReq_misses::0 22262 # number of StoreCondReq misses
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system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_misses 30004 # number of StoreCondReq MSHR misses
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-system.cpu.dcache.WriteReq_accesses::total 6160337 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency::0 56004.022652 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53004.022652 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52757.232436 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits::0 5759482 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 5759482 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 22449492500 # number of WriteReq miss cycles
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-system.cpu.dcache.WriteReq_misses::0 400855 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 400855 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 21246927500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.065070 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 400855 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs 10.097318 # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs 10.097149 # Average number of references to valid blocks.
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.demand_accesses::0 15048990 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
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system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 30777.644424 # average overall mshr miss latency
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system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 13577961 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.demand_misses::0 1471029 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1471029 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 45274807500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate::0 0.097749 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_latency 43534129000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate::0 0.095764 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.occ_%::0 0.999969 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 511.984142 # Average occupied blocks per context
-system.cpu.dcache.overall_accesses::0 15048990 # number of overall (read+write) accesses
+system.cpu.dcache.occ_blocks::0 511.984152 # Average occupied blocks per context
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system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
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system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
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+system.cpu.dcache.overall_avg_mshr_miss_latency 30225.128426 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits::0 13577961 # number of overall hits
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system.cpu.dcache.overall_hits::1 0 # number of overall hits
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system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
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system.cpu.dcache.overall_misses::1 0 # number of overall misses
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system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
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system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.replacements 1391606 # number of replacements
-system.cpu.dcache.sampled_refs 1392118 # Sample count of references to valid blocks.
+system.cpu.dcache.replacements 1390845 # number of replacements
+system.cpu.dcache.sampled_refs 1391357 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 511.984142 # Cycle average of tags in use
-system.cpu.dcache.total_refs 14056658 # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle 84139000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks 430459 # number of writebacks
+system.cpu.dcache.tagsinuse 511.984152 # Cycle average of tags in use
+system.cpu.dcache.total_refs 14048739 # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle 84029000 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks 452168 # number of writebacks
system.cpu.dtb.data_accesses 1020784 # DTB accesses
system.cpu.dtb.data_acv 367 # DTB access violations
-system.cpu.dtb.data_hits 15429793 # DTB hits
+system.cpu.dtb.data_hits 15421062 # DTB hits
system.cpu.dtb.data_misses 11466 # DTB misses
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.read_accesses 728853 # DTB read accesses
system.cpu.dtb.read_acv 210 # DTB read access violations
-system.cpu.dtb.read_hits 9069700 # DTB read hits
+system.cpu.dtb.read_hits 9064565 # DTB read hits
system.cpu.dtb.read_misses 10324 # DTB read misses
system.cpu.dtb.write_accesses 291931 # DTB write accesses
system.cpu.dtb.write_acv 157 # DTB write access violations
-system.cpu.dtb.write_hits 6360093 # DTB write hits
+system.cpu.dtb.write_hits 6356497 # DTB write hits
system.cpu.dtb.write_misses 1142 # DTB write misses
-system.cpu.icache.ReadReq_accesses::0 56217537 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 56217537 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency::0 14711.221983 # average ReadReq miss latency
+system.cpu.icache.ReadReq_accesses::0 56192153 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 56192153 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency::0 14699.293599 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11710.491665 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits::0 55286436 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 55286436 # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency 13697633500 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate::0 0.016562 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses::0 931101 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 931101 # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency 10903650500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0 0.016562 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11698.559265 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits::0 55261378 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 55261378 # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency 13681735000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate::0 0.016564 # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses::0 930775 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 930775 # number of ReadReq misses
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
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-system.cpu.icache.demand_misses::total 931101 # number of demand (read+write) misses
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system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
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system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.993281 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 508.559728 # Average occupied blocks per context
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+system.cpu.icache.occ_%::0 0.993310 # Average percentage of cache occupancy
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system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses
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system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11710.491665 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits::0 55286436 # number of overall hits
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system.cpu.icache.overall_hits::1 0 # number of overall hits
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system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses
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system.cpu.icache.overall_misses::1 0 # number of overall misses
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system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
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-system.cpu.icache.overall_mshr_miss_rate::0 0.016562 # mshr miss rate for overall accesses
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system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses 931101 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses 930775 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.replacements 930429 # number of replacements
-system.cpu.icache.sampled_refs 930940 # Sample count of references to valid blocks.
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system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 508.559728 # Cycle average of tags in use
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+system.cpu.icache.warmup_cycle 38310365000 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.idle_fraction 0.929209 # Percentage of idle cycles
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system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.fetch_accesses 4982987 # ITB accesses
+system.cpu.itb.fetch_accesses 4982567 # ITB accesses
system.cpu.itb.fetch_acv 184 # ITB acv
-system.cpu.itb.fetch_hits 4977977 # ITB hits
+system.cpu.itb.fetch_hits 4977557 # ITB hits
system.cpu.itb.fetch_misses 5010 # ITB misses
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
-system.cpu.kern.callpal::swpctx 4171 2.16% 2.16% # number of callpals executed
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system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed
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-system.cpu.kern.callpal::swpipl 176257 91.22% 93.41% # number of callpals executed
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+system.cpu.kern.callpal::swpipl 176202 91.22% 93.41% # number of callpals executed
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system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal::rdusp 9 0.00% 96.96% # number of callpals executed
system.cpu.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed
-system.cpu.kern.callpal::rti 5169 2.68% 99.64% # number of callpals executed
+system.cpu.kern.callpal::rti 5167 2.67% 99.64% # number of callpals executed
system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
-system.cpu.kern.callpal::total 193221 # number of callpals executed
+system.cpu.kern.callpal::total 193169 # number of callpals executed
system.cpu.kern.inst.arm 0 # number of arm instructions executed
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-system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed
-system.cpu.kern.ipl_count::0 75001 40.87% 40.87% # number of times we switched to this ipl
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+system.cpu.kern.ipl_count::0 74979 40.87% 40.87% # number of times we switched to this ipl
system.cpu.kern.ipl_count::21 131 0.07% 40.94% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::22 1944 1.06% 42.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::31 106426 58.00% 100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_count::total 183502 # number of times we switched to this ipl
-system.cpu.kern.ipl_good::0 73634 49.31% 49.31% # number of times we switched to this ipl from a different ipl
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+system.cpu.kern.ipl_count::31 106391 58.00% 100.00% # number of times we switched to this ipl
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+system.cpu.kern.ipl_good::0 73612 49.31% 49.31% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::22 1944 1.30% 50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::31 73634 49.31% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good::total 149343 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1866810523000 96.72% 96.72% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::21 96331500 0.00% 96.72% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::22 565310500 0.03% 96.75% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 62691670000 3.25% 100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::total 1930163835000 # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used::0 0.981774 # fraction of swpipl calls that actually changed the ipl
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+system.cpu.kern.ipl_good::31 73612 49.31% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good::total 149297 # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks::0 1865248449500 96.75% 96.75% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::21 84324500 0.00% 96.75% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::22 564095000 0.03% 96.78% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 62054251000 3.22% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::total 1927951120000 # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used::0 0.981768 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used::31 0.691880 # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.mode_good::kernel 1911
+system.cpu.kern.ipl_used::31 0.691901 # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.mode_good::kernel 1914
system.cpu.kern.mode_good::user 1744
-system.cpu.kern.mode_good::idle 167
-system.cpu.kern.mode_switch::kernel 5917 # number of protection mode switches
+system.cpu.kern.mode_good::idle 170
+system.cpu.kern.mode_switch::kernel 5914 # number of protection mode switches
system.cpu.kern.mode_switch::user 1744 # number of protection mode switches
-system.cpu.kern.mode_switch::idle 2089 # number of protection mode switches
-system.cpu.kern.mode_switch_good::kernel 0.322968 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches
+system.cpu.kern.mode_switch_good::kernel 0.323639 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::idle 0.079943 # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good::total 1.402910 # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks::kernel 48447088000 2.51% 2.51% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::user 5539986000 0.29% 2.80% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1876176759000 97.20% 100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context 4172 # number of times the context was actually changed
+system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good::total 1.404746 # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks::kernel 47869140000 2.48% 2.48% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user 5515150000 0.29% 2.77% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1874566828000 97.23% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context 4178 # number of times the context was actually changed
system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
system.cpu.kern.syscall::total 326 # number of syscalls executed
-system.cpu.not_idle_fraction 0.070791 # Percentage of non-idle cycles
-system.cpu.numCycles 3860329186 # number of cpu cycles simulated
-system.cpu.num_insts 56205703 # Number of instructions executed
-system.cpu.num_refs 15677891 # Number of memory references
+system.cpu.not_idle_fraction 0.069690 # Percentage of non-idle cycles
+system.cpu.numCycles 3855903756 # number of cpu cycles simulated
+system.cpu.num_insts 56180319 # Number of instructions executed
+system.cpu.num_refs 15669216 # Number of memory references
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137876.559636 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::1 137846.765643 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85873.072921 # average WriteReq mshr miss latency
-system.iocache.WriteReq_miss_latency 5729046806 # number of WriteReq miss cycles
+system.iocache.WriteReq_avg_mshr_miss_latency 85843.300347 # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency 5727808806 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses
system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
-system.iocache.WriteReq_mshr_miss_latency 3568197926 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency 3566960816 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses
-system.iocache.avg_blocked_cycles::no_mshrs 6163.674943 # average number of cycles each access was blocked
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system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.blocked::no_mshrs 10472 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_mshrs 64546004 # number of cycles access was blocked
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system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses
system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137782.763427 # average overall miss latency
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system.iocache.demand_avg_miss_latency::total inf # average overall miss latency
-system.iocache.demand_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency 85749.642037 # average overall mshr miss latency
system.iocache.demand_hits::0 0 # number of demand (read+write) hits
system.iocache.demand_hits::1 0 # number of demand (read+write) hits
system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.demand_miss_latency 5748985804 # number of demand (read+write) miss cycles
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system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
system.iocache.demand_misses::1 41725 # number of demand (read+write) misses
system.iocache.demand_misses::total 41725 # number of demand (read+write) misses
system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.demand_mshr_miss_latency 3579140924 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency 3577903814 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.occ_%::1 0.084587 # Average percentage of cache occupancy
-system.iocache.occ_blocks::1 1.353399 # Average occupied blocks per context
+system.iocache.occ_%::1 0.084569 # Average percentage of cache occupancy
+system.iocache.occ_blocks::1 1.353112 # Average occupied blocks per context
system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137782.763427 # average overall miss latency
+system.iocache.overall_avg_miss_latency::1 137753.092966 # average overall miss latency
system.iocache.overall_avg_miss_latency::total inf # average overall miss latency
-system.iocache.overall_avg_mshr_miss_latency 85779.291168 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency 85749.642037 # average overall mshr miss latency
system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.iocache.overall_hits::0 0 # number of overall hits
system.iocache.overall_hits::1 0 # number of overall hits
system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.overall_miss_latency 5748985804 # number of overall miss cycles
+system.iocache.overall_miss_latency 5747747804 # number of overall miss cycles
system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
system.iocache.overall_misses::1 41725 # number of overall misses
system.iocache.overall_misses::total 41725 # number of overall misses
system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.overall_mshr_miss_latency 3579140924 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency 3577903814 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
system.iocache.replacements 41685 # number of replacements
system.iocache.sampled_refs 41701 # Sample count of references to valid blocks.
system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.tagsinuse 1.353399 # Cycle average of tags in use
+system.iocache.tagsinuse 1.353112 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.warmup_cycle 1762299470000 # Cycle when the warmup percentage was hit.
+system.iocache.warmup_cycle 1760339542000 # Cycle when the warmup percentage was hit.
system.iocache.writebacks 41512 # number of writebacks
-system.l2c.ReadExReq_accesses::0 304636 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 304636 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 52003.289171 # average ReadExReq miss latency
+system.l2c.ReadExReq_accesses::0 304386 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 304386 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency::0 52003.580327 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40003.289171 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency 15842074000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses::0 304636 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 304636 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 12186442000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_avg_mshr_miss_latency 40003.580327 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_hits::0 2179 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 2179 # number of ReadExReq hits
+system.l2c.ReadExReq_miss_latency 15715846000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_rate::0 0.992841 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_misses::0 302207 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 302207 # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency 12089362000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_rate::0 0.992841 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses 304636 # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses::0 2018564 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2018564 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency::0 52016.377161 # average ReadReq miss latency
+system.l2c.ReadExReq_mshr_misses 302207 # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses::0 2017728 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2017728 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency::0 52016.477812 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40016.359280 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 40016.459857 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits::0 1710971 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1710971 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 15999873500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0 0.152382 # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses::0 307593 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 307593 # number of ReadReq misses
-system.l2c.ReadReq_mshr_miss_latency 12308752000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.152382 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_hits::0 1711407 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 1711407 # number of ReadReq hits
+system.l2c.ReadReq_miss_latency 15933739500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate::0 0.151815 # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses::0 306321 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 306321 # number of ReadReq misses
+system.l2c.ReadReq_mshr_miss_latency 12257882000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::0 0.151815 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 307593 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses 306321 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_uncacheable_latency 772673000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.SCUpgradeReq_accesses::0 30004 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 30004 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_avg_miss_latency::0 52004.366085 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_accesses::0 22262 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 22262 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_avg_miss_latency::0 52004.626718 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::1 inf # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40004.366085 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_miss_latency 1560339000 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40004.626718 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_miss_latency 1157727000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_rate::0 1 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_misses::0 30004 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 30004 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_mshr_miss_latency 1200291000 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_misses::0 22262 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 22262 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_mshr_miss_latency 890583000 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_misses 30004 # number of SCUpgradeReq MSHR misses
-system.l2c.UpgradeReq_accesses::0 96219 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 96219 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency::0 52001.013313 # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_mshr_misses 22262 # number of SCUpgradeReq MSHR misses
+system.l2c.UpgradeReq_accesses::0 66236 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 66236 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency::0 52000.030195 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40006.391669 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency 5003485500 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40007.095839 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_miss_latency 3444274000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 96219 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 96219 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency 3849375000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_misses::0 66236 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 66236 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency 2649910000 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_rate::0 1 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 96219 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses 66236 # number of UpgradeReq MSHR misses
system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 1085299500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0 430459 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 430459 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 430459 # number of Writeback hits
-system.l2c.Writeback_hits::total 430459 # number of Writeback hits
+system.l2c.WriteReq_mshr_uncacheable_latency 1085051000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses::0 452168 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 452168 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_hits::0 452168 # number of Writeback hits
+system.l2c.Writeback_hits::total 452168 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 4.436562 # Average number of references to valid blocks.
+system.l2c.avg_refs 4.517115 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 2323200 # number of demand (read+write) accesses
+system.l2c.demand_accesses::0 2322114 # number of demand (read+write) accesses
system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2323200 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 52009.864773 # average overall miss latency
+system.l2c.demand_accesses::total 2322114 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0 52010.072667 # average overall miss latency
system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency
system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency
-system.l2c.demand_hits::0 1710971 # number of demand (read+write) hits
+system.l2c.demand_avg_mshr_miss_latency 40010.063629 # average overall mshr miss latency
+system.l2c.demand_hits::0 1713586 # number of demand (read+write) hits
system.l2c.demand_hits::1 0 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1710971 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 31841947500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.263528 # miss rate for demand accesses
+system.l2c.demand_hits::total 1713586 # number of demand (read+write) hits
+system.l2c.demand_miss_latency 31649585500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0 0.262058 # miss rate for demand accesses
system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses
system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
-system.l2c.demand_misses::0 612229 # number of demand (read+write) misses
+system.l2c.demand_misses::0 608528 # number of demand (read+write) misses
system.l2c.demand_misses::1 0 # number of demand (read+write) misses
-system.l2c.demand_misses::total 612229 # number of demand (read+write) misses
+system.l2c.demand_misses::total 608528 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 24495194000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0.263528 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_latency 24347244000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0 0.262058 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 612229 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses 608528 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.086363 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.380427 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 5659.865751 # Average occupied blocks per context
-system.l2c.occ_blocks::1 24931.678191 # Average occupied blocks per context
-system.l2c.overall_accesses::0 2323200 # number of overall (read+write) accesses
+system.l2c.occ_%::0 0.156745 # Average percentage of cache occupancy
+system.l2c.occ_%::1 0.334961 # Average percentage of cache occupancy
+system.l2c.occ_blocks::0 10272.459916 # Average occupied blocks per context
+system.l2c.occ_blocks::1 21951.974033 # Average occupied blocks per context
+system.l2c.overall_accesses::0 2322114 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2323200 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 52009.864773 # average overall miss latency
+system.l2c.overall_accesses::total 2322114 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0 52010.072667 # average overall miss latency
system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency
system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40009.855789 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 40010.063629 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.overall_hits::0 1710971 # number of overall hits
+system.l2c.overall_hits::0 1713586 # number of overall hits
system.l2c.overall_hits::1 0 # number of overall hits
-system.l2c.overall_hits::total 1710971 # number of overall hits
-system.l2c.overall_miss_latency 31841947500 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.263528 # miss rate for overall accesses
+system.l2c.overall_hits::total 1713586 # number of overall hits
+system.l2c.overall_miss_latency 31649585500 # number of overall miss cycles
+system.l2c.overall_miss_rate::0 0.262058 # miss rate for overall accesses
system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses
system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
-system.l2c.overall_misses::0 612229 # number of overall misses
+system.l2c.overall_misses::0 608528 # number of overall misses
system.l2c.overall_misses::1 0 # number of overall misses
-system.l2c.overall_misses::total 612229 # number of overall misses
+system.l2c.overall_misses::total 608528 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 24495194000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 0.263528 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_latency 24347244000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0 0.262058 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 612229 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency 1857972500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_misses 608528 # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency 1857724000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.replacements 394928 # number of replacements
-system.l2c.sampled_refs 425903 # Sample count of references to valid blocks.
+system.l2c.replacements 393234 # number of replacements
+system.l2c.sampled_refs 424575 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 30591.543942 # Cycle average of tags in use
-system.l2c.total_refs 1889545 # Total number of references to valid blocks.
-system.l2c.warmup_cycle 6968733000 # Cycle when the warmup percentage was hit.
-system.l2c.writebacks 119060 # number of writebacks
+system.l2c.tagsinuse 32224.433949 # Cycle average of tags in use
+system.l2c.total_refs 1917854 # Total number of references to valid blocks.
+system.l2c.warmup_cycle 6967096000 # Cycle when the warmup percentage was hit.
+system.l2c.writebacks 118566 # number of writebacks
system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post
system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post
system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post
type=EioProcess
chkpt=
errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
All Rights Reserved
-M5 compiled Feb 24 2010 23:12:40
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 02:33:34
-M5 executing on SC2B0619
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing
+M5 compiled Aug 26 2010 19:15:13
+M5 revision 85cafc6ccb42+ 7662+ default qtip tip sc-fail-fix
+M5 started Aug 26 2010 19:20:56
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
49508 bytes wasted
->Exiting @ tick 737389000 because a thread reached the max instruction count
+>Exiting @ tick 727929000 because a thread reached the max instruction count
---------- Begin Simulation Statistics ----------
-host_inst_rate 1409192 # Simulator instruction rate (inst/s)
-host_mem_usage 189184 # Number of bytes of host memory used
-host_seconds 0.36 # Real time elapsed on the host
-host_tick_rate 2076450214 # Simulator tick rate (ticks/s)
+host_inst_rate 1184343 # Simulator instruction rate (inst/s)
+host_mem_usage 203180 # Number of bytes of host memory used
+host_seconds 0.42 # Real time elapsed on the host
+host_tick_rate 1723169900 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 500001 # Number of instructions simulated
-sim_seconds 0.000737 # Number of seconds simulated
-sim_ticks 737389000 # Number of ticks simulated
+sim_seconds 0.000728 # Number of seconds simulated
+sim_ticks 727929000 # Number of ticks simulated
system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits 56029 # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency 17416000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses 311 # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency 16483000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency 7784000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency 7367000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks.
system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses
system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.demand_hits 180149 # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency 35056000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate 0.003463 # miss rate for demand accesses
-system.cpu.dcache.demand_misses 626 # number of demand (read+write) misses
+system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency 25424000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses
+system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency 33178000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate 0.003463 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses 626 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency 24062000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.occ_%::0 0.069937 # Average percentage of cache occupancy
-system.cpu.dcache.occ_blocks::0 286.463742 # Average occupied blocks per context
+system.cpu.dcache.occ_%::0 0.070111 # Average percentage of cache occupancy
+system.cpu.dcache.occ_blocks::0 287.175167 # Average occupied blocks per context
system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses
system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits 180149 # number of overall hits
-system.cpu.dcache.overall_miss_latency 35056000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate 0.003463 # miss rate for overall accesses
-system.cpu.dcache.overall_misses 626 # number of overall misses
+system.cpu.dcache.overall_hits 180321 # number of overall hits
+system.cpu.dcache.overall_miss_latency 25424000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses
+system.cpu.dcache.overall_misses 454 # number of overall misses
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency 33178000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate 0.003463 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses 626 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_miss_latency 24062000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks.
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse 286.463742 # Cycle average of tags in use
+system.cpu.dcache.tagsinuse 287.175167 # Cycle average of tags in use
system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.writebacks 0 # number of writebacks
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.icache.occ_%::0 0.129067 # Average percentage of cache occupancy
-system.cpu.icache.occ_blocks::0 264.328816 # Average occupied blocks per context
+system.cpu.icache.occ_%::0 0.129371 # Average percentage of cache occupancy
+system.cpu.icache.occ_blocks::0 264.952126 # Average occupied blocks per context
system.cpu.icache.overall_accesses 500020 # number of overall (read+write) accesses
system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
system.cpu.icache.replacements 0 # number of replacements
system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks.
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse 264.328816 # Cycle average of tags in use
+system.cpu.icache.tagsinuse 264.952126 # Cycle average of tags in use
system.cpu.icache.total_refs 499617 # Total number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_miss_latency 28720000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_accesses 172 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_avg_miss_latency 52000 # average UpgradeReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_miss_latency 8944000 # number of UpgradeReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_misses 172 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6880000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_misses 172 # number of UpgradeReq MSHR misses
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.occ_%::0 0.011298 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_blocks::0 370.220381 # Average occupied blocks per context
+system.cpu.l2cache.occ_%::0 0.014692 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_blocks::0 481.419470 # Average occupied blocks per context
system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses
system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.replacements 0 # number of replacements
-system.cpu.l2cache.sampled_refs 546 # Sample count of references to valid blocks.
+system.cpu.l2cache.sampled_refs 718 # Sample count of references to valid blocks.
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse 370.220381 # Cycle average of tags in use
+system.cpu.l2cache.tagsinuse 481.419470 # Cycle average of tags in use
system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
-system.cpu.numCycles 1474778 # number of cpu cycles simulated
+system.cpu.numCycles 1455858 # number of cpu cycles simulated
system.cpu.num_insts 500001 # Number of instructions executed
system.cpu.num_refs 182222 # Number of memory references
system.cpu.workload.PROG:num_syscalls 18 # Number of system calls
type=EioProcess
chkpt=
errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
type=EioProcess
chkpt=
errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
type=EioProcess
chkpt=
errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
type=EioProcess
chkpt=
errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
gzip: stdout: Broken pipe
gzip: stdout: Broken pipe
+
+gzip: stdout: Broken pipe
+
+gzip: stdout: Broken pipe
All Rights Reserved
-M5 compiled Feb 24 2010 23:12:40
-M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip
-M5 started Feb 25 2010 02:22:16
-M5 executing on SC2B0619
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp
+M5 compiled Aug 26 2010 19:15:13
+M5 revision 85cafc6ccb42+ 7662+ default qtip tip sc-fail-fix
+M5 started Aug 26 2010 19:20:56
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
main dictionary has 1245 entries
---------- Begin Simulation Statistics ----------
-host_inst_rate 1651065 # Simulator instruction rate (inst/s)
-host_mem_usage 1114084 # Number of bytes of host memory used
-host_seconds 1.21 # Real time elapsed on the host
-host_tick_rate 206342663 # Simulator tick rate (ticks/s)
+host_inst_rate 3552670 # Simulator instruction rate (inst/s)
+host_mem_usage 1128260 # Number of bytes of host memory used
+host_seconds 0.56 # Real time elapsed on the host
+host_tick_rate 443935332 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 2000004 # Number of instructions simulated
sim_seconds 0.000250 # Number of seconds simulated
system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses
system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_hits 56029 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_hits 56201 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses 139 # number of WriteReq misses
system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 180140 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits 180312 # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses
+system.cpu0.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
+system.cpu0.dcache.demand_misses 463 # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 180140 # number of overall hits
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system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
-system.cpu0.dcache.overall_misses 635 # number of overall misses
+system.cpu0.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
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system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses
system.cpu1.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_hits 56029 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses 311 # number of WriteReq misses
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+system.cpu1.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
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system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
system.cpu1.dcache.demand_accesses 180775 # number of demand (read+write) accesses
system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.dcache.demand_hits 180140 # number of demand (read+write) hits
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system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
-system.cpu1.dcache.demand_misses 635 # number of demand (read+write) misses
+system.cpu1.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
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system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits 180140 # number of overall hits
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system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
-system.cpu1.dcache.overall_misses 635 # number of overall misses
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system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses
system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_hits 56029 # number of WriteReq hits
-system.cpu2.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_misses 311 # number of WriteReq misses
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+system.cpu2.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
+system.cpu2.dcache.WriteReq_misses 139 # number of WriteReq misses
system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses
system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu2.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu2.dcache.demand_hits 180140 # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits 180312 # number of demand (read+write) hits
system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
-system.cpu2.dcache.demand_misses 635 # number of demand (read+write) misses
+system.cpu2.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses
+system.cpu2.dcache.demand_misses 463 # number of demand (read+write) misses
system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu2.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu2.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu2.dcache.overall_hits 180140 # number of overall hits
+system.cpu2.dcache.overall_hits 180312 # number of overall hits
system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu2.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
-system.cpu2.dcache.overall_misses 635 # number of overall misses
+system.cpu2.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses
+system.cpu2.dcache.overall_misses 463 # number of overall misses
system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu2.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu2.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses
system.cpu3.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_hits 56029 # number of WriteReq hits
-system.cpu3.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_misses 311 # number of WriteReq misses
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+system.cpu3.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses
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system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu3.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
system.cpu3.dcache.demand_accesses 180775 # number of demand (read+write) accesses
system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu3.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu3.dcache.demand_hits 180140 # number of demand (read+write) hits
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system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
-system.cpu3.dcache.demand_misses 635 # number of demand (read+write) misses
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system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu3.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu3.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu3.dcache.overall_hits 180140 # number of overall hits
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system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu3.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
-system.cpu3.dcache.overall_misses 635 # number of overall misses
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system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu3.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu3.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.l2c.ReadReq_misses::2 718 # number of ReadReq misses
system.l2c.ReadReq_misses::3 718 # number of ReadReq misses
system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses
-system.l2c.UpgradeReq_accesses::0 172 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1 172 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::2 172 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::3 172 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 688 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 172 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1 172 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::2 172 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::3 172 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 688 # number of UpgradeReq misses
system.l2c.Writeback_accesses::0 116 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0 116 # number of Writeback hits
system.l2c.Writeback_hits::total 116 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 0.120000 # Average number of references to valid blocks.
+system.l2c.avg_refs 0.113233 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.005715 # Average percentage of cache occupancy
-system.l2c.occ_%::1 0.005715 # Average percentage of cache occupancy
-system.l2c.occ_%::2 0.005715 # Average percentage of cache occupancy
-system.l2c.occ_%::3 0.005715 # Average percentage of cache occupancy
-system.l2c.occ_%::4 0.000475 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 374.558766 # Average occupied blocks per context
-system.l2c.occ_blocks::1 374.558766 # Average occupied blocks per context
-system.l2c.occ_blocks::2 374.558766 # Average occupied blocks per context
-system.l2c.occ_blocks::3 374.558766 # Average occupied blocks per context
-system.l2c.occ_blocks::4 31.139534 # Average occupied blocks per context
+system.l2c.occ_%::0 0.007421 # Average percentage of cache occupancy
+system.l2c.occ_%::1 0.007421 # Average percentage of cache occupancy
+system.l2c.occ_%::2 0.007421 # Average percentage of cache occupancy
+system.l2c.occ_%::3 0.007421 # Average percentage of cache occupancy
+system.l2c.occ_%::4 0.000267 # Average percentage of cache occupancy
+system.l2c.occ_blocks::0 486.328367 # Average occupied blocks per context
+system.l2c.occ_blocks::1 486.328367 # Average occupied blocks per context
+system.l2c.occ_blocks::2 486.328367 # Average occupied blocks per context
+system.l2c.occ_blocks::3 486.328367 # Average occupied blocks per context
+system.l2c.occ_blocks::4 17.466765 # Average occupied blocks per context
system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses
system.l2c.overall_accesses::2 926 # number of overall (read+write) accesses
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.replacements 0 # number of replacements
-system.l2c.sampled_refs 2300 # Sample count of references to valid blocks.
+system.l2c.sampled_refs 2932 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 1529.374598 # Cycle average of tags in use
-system.l2c.total_refs 276 # Total number of references to valid blocks.
+system.l2c.tagsinuse 1962.780232 # Cycle average of tags in use
+system.l2c.total_refs 332 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 0 # number of writebacks
type=EioProcess
chkpt=
errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
type=EioProcess
chkpt=
errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
type=EioProcess
chkpt=
errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
type=EioProcess
chkpt=
errout=cerr
-file=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
+file=/dist/m5/regression/test-progs/anagram/bin/alpha/eio/anagram-vshort.eio.gz
input=None
max_stack_size=67108864
output=cout
All Rights Reserved
-M5 compiled Jul 1 2010 14:37:40
-M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate
-M5 started Jul 1 2010 14:37:50
-M5 executing on phenom
+M5 compiled Aug 26 2010 19:15:13
+M5 revision 85cafc6ccb42+ 7662+ default qtip tip sc-fail-fix
+M5 started Aug 26 2010 19:20:56
+M5 executing on zizzer
command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
49508 bytes wasted
49508 bytes wasted
49508 bytes wasted
->>>>Exiting @ tick 738387000 because a thread reached the max instruction count
+>>>>Exiting @ tick 728920000 because a thread reached the max instruction count
---------- Begin Simulation Statistics ----------
-host_inst_rate 1240283 # Simulator instruction rate (inst/s)
-host_mem_usage 197852 # Number of bytes of host memory used
-host_seconds 1.61 # Real time elapsed on the host
-host_tick_rate 457858198 # Simulator tick rate (ticks/s)
+host_inst_rate 1077320 # Simulator instruction rate (inst/s)
+host_mem_usage 210756 # Number of bytes of host memory used
+host_seconds 1.86 # Real time elapsed on the host
+host_tick_rate 392590905 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
-sim_insts 1999941 # Number of instructions simulated
-sim_seconds 0.000738 # Number of seconds simulated
-sim_ticks 738387000 # Number of ticks simulated
+sim_insts 1999954 # Number of instructions simulated
+sim_seconds 0.000729 # Number of seconds simulated
+sim_ticks 728920000 # Number of ticks simulated
system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency 54876.543210 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51876.543210 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency 54891.975309 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51891.975309 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency 17780000 # number of ReadReq miss cycles
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system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency 16808000 # number of ReadReq MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency 56051.446945 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53051.446945 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_hits 56029 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency 17432000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate 0.005520 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 311 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_miss_latency 16499000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate 0.005520 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses 311 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_avg_miss_latency 56064.748201 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53064.748201 # average WriteReq mshr miss latency
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system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 55451.968504 # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 180140 # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency 35212000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.003513 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 635 # number of demand (read+write) misses
+system.cpu0.dcache.demand_avg_miss_latency 55244.060475 # average overall miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 52244.060475 # average overall mshr miss latency
+system.cpu0.dcache.demand_hits 180312 # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency 25578000 # number of demand (read+write) miss cycles
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system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency 33307000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate 0.003513 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses 635 # number of demand (read+write) MSHR misses
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system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0 0.533049 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_blocks::0 272.921161 # Average occupied blocks per context
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system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 55451.968504 # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 52451.968504 # average overall mshr miss latency
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system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 180140 # number of overall hits
-system.cpu0.dcache.overall_miss_latency 35212000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate 0.003513 # miss rate for overall accesses
-system.cpu0.dcache.overall_misses 635 # number of overall misses
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system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency 33307000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate 0.003513 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses 635 # number of overall MSHR misses
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system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.dcache.replacements 61 # number of replacements
system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse 272.921161 # Cycle average of tags in use
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system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks 29 # number of writebacks
system.cpu0.dtb.write_hits 56340 # DTB write hits
system.cpu0.dtb.write_misses 10 # DTB write misses
system.cpu0.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency 50710.583153 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47710.583153 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency 50699.784017 # average ReadReq miss latency
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system.cpu0.icache.ReadReq_hits 499557 # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_latency 23479000 # number of ReadReq miss cycles
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system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_miss_latency 22090000 # number of ReadReq MSHR miss cycles
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system.cpu0.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.demand_accesses 500020 # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency 50710.583153 # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency
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system.cpu0.icache.demand_hits 499557 # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency 23479000 # number of demand (read+write) miss cycles
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system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses
system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses
system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency 22090000 # number of demand (read+write) MSHR miss cycles
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system.cpu0.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.occ_%::0 0.421796 # Average percentage of cache occupancy
-system.cpu0.icache.occ_blocks::0 215.959580 # Average occupied blocks per context
+system.cpu0.icache.occ_%::0 0.422639 # Average percentage of cache occupancy
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system.cpu0.icache.overall_accesses 500020 # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency 50710.583153 # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 47710.583153 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_miss_latency 50699.784017 # average overall miss latency
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system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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system.cpu3.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses
system.cpu3.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses
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+system.l2c.overall_miss_latency 178290000 # number of overall miss cycles
system.l2c.overall_miss_rate::0 0.925486 # miss rate for overall accesses
system.l2c.overall_miss_rate::1 0.925486 # miss rate for overall accesses
system.l2c.overall_miss_rate::2 0.925486 # miss rate for overall accesses
system.l2c.overall_misses::3 857 # number of overall misses
system.l2c.overall_misses::total 3428 # number of overall misses
system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 137148000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency 137154000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_rate::0 3.701944 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::1 3.701944 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::2 3.701944 # mshr miss rate for overall accesses
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.replacements 0 # number of replacements
-system.l2c.sampled_refs 2300 # Sample count of references to valid blocks.
+system.l2c.sampled_refs 2932 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 1511.572121 # Cycle average of tags in use
-system.l2c.total_refs 276 # Total number of references to valid blocks.
+system.l2c.tagsinuse 1943.298536 # Cycle average of tags in use
+system.l2c.total_refs 332 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 0 # number of writebacks
+Redirecting stdout to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simout
+Redirecting stderr to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jul 1 2010 14:40:18
-M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate
-M5 started Jul 1 2010 14:40:33
-M5 executing on phenom
+M5 compiled Aug 26 2010 13:03:41
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:03:47
+M5 executing on zizzer
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
[Iteration 10, Thread 2] Critical section done, previously next=1, now next=2
Iteration 10 completed
PASSED :-)
-Exiting @ tick 217002500 because target called exit()
+Exiting @ tick 216428500 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 52624 # Simulator instruction rate (inst/s)
-host_mem_usage 204896 # Number of bytes of host memory used
-host_seconds 8.25 # Real time elapsed on the host
-host_tick_rate 26298944 # Simulator tick rate (ticks/s)
+host_inst_rate 29197 # Simulator instruction rate (inst/s)
+host_mem_usage 217900 # Number of bytes of host memory used
+host_seconds 14.87 # Real time elapsed on the host
+host_tick_rate 14552660 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 434213 # Number of instructions simulated
-sim_seconds 0.000217 # Number of seconds simulated
-sim_ticks 217002500 # Number of ticks simulated
+sim_seconds 0.000216 # Number of seconds simulated
+sim_ticks 216428500 # Number of ticks simulated
system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.BPredUnit.BTBHits 44089 # Number of BTB hits
-system.cpu0.BPredUnit.BTBLookups 68672 # Number of BTB lookups
+system.cpu0.BPredUnit.BTBLookups 68668 # Number of BTB lookups
system.cpu0.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu0.BPredUnit.condIncorrect 42322 # Number of conditional branches incorrect
-system.cpu0.BPredUnit.condPredicted 70853 # Number of conditional branches predicted
-system.cpu0.BPredUnit.lookups 70853 # Number of BP lookups
+system.cpu0.BPredUnit.condPredicted 70848 # Number of conditional branches predicted
+system.cpu0.BPredUnit.lookups 70848 # Number of BP lookups
system.cpu0.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu0.commit.COM:branches 23275 # Number of branches committed
-system.cpu0.commit.COM:bw_lim_events 181 # number cycles where commit BW limit reached
+system.cpu0.commit.COM:bw_lim_events 180 # number cycles where commit BW limit reached
system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.commit.COM:committed_per_cycle::samples 371561 # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::mean 0.368389 # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::stdev 0.674594 # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::samples 370366 # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::mean 0.369578 # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::stdev 0.675268 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::0 264099 71.08% 71.08% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::1 83154 22.38% 93.46% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::2 22390 6.03% 99.48% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::3 687 0.18% 99.67% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::4 334 0.09% 99.76% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::0 262900 70.98% 70.98% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::1 83158 22.45% 93.44% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::2 22390 6.05% 99.48% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::3 687 0.19% 99.67% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::4 335 0.09% 99.76% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::5 230 0.06% 99.82% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::6 452 0.12% 99.94% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::7 34 0.01% 99.95% # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::8 181 0.05% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::8 180 0.05% 100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle::total 371561 # Number of insts commited each cycle
+system.cpu0.commit.COM:committed_per_cycle::total 370366 # Number of insts commited each cycle
system.cpu0.commit.COM:count 136879 # Number of instructions committed
system.cpu0.commit.COM:loads 41762 # Number of loads committed
system.cpu0.commit.COM:membars 84 # Number of memory barriers committed
system.cpu0.commit.commitSquashedInsts 179861 # The number of squashed insts skipped by commit
system.cpu0.committedInsts 116789 # Number of Instructions Simulated
system.cpu0.committedInsts_total 116789 # Number of Instructions Simulated
-system.cpu0.cpi 3.716155 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 3.716155 # CPI: Total CPI of All Threads
+system.cpu0.cpi 3.706325 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 3.706325 # CPI: Total CPI of All Threads
system.cpu0.dcache.ReadReq_accesses 24665 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency 30305.031447 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency 30381.703470 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 24070.175439 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_hits 24347 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency 9637000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate 0.012893 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses 318 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_hits 90 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_hits 24348 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_latency 9631000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_rate 0.012852 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses 317 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_mshr_hits 89 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_miss_latency 5488000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate 0.009244 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_misses 228 # number of ReadReq MSHR misses
system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses
system.cpu0.dcache.WriteReq_accesses 21345 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency 45805.892548 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 38962.500000 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_hits 20768 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency 26430000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate 0.027032 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 577 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_hits 377 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_miss_latency 7792500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate 0.009370 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses 200 # number of WriteReq MSHR misses
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 22000 # average number of cycles each access was blocked
+system.cpu0.dcache.WriteReq_avg_miss_latency 44931.354360 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36030.726257 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_hits 20806 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency 24218000 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate 0.025252 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses 539 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_hits 360 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_miss_latency 6449500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate 0.008386 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_misses 179 # number of WriteReq MSHR misses
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 25250 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs 162.931818 # Average number of references to valid blocks.
-system.cpu0.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
+system.cpu0.dcache.avg_refs 162.926136 # Average number of references to valid blocks.
+system.cpu0.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_mshrs 66000 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_mshrs 50500 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.demand_accesses 46010 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 40298.324022 # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 31029.205607 # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 45115 # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency 36067000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.019452 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 895 # number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits 467 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency 13280500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate 0.009302 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses 428 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_avg_miss_latency 39543.224299 # average overall miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 29330.466830 # average overall mshr miss latency
+system.cpu0.dcache.demand_hits 45154 # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency 33849000 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate 0.018605 # miss rate for demand accesses
+system.cpu0.dcache.demand_misses 856 # number of demand (read+write) misses
+system.cpu0.dcache.demand_mshr_hits 449 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_miss_latency 11937500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate 0.008846 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_misses 407 # number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.occ_%::0 0.284939 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_%::1 -0.008000 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_blocks::0 145.888773 # Average occupied blocks per context
-system.cpu0.dcache.occ_blocks::1 -4.096255 # Average occupied blocks per context
+system.cpu0.dcache.occ_%::0 0.285120 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_%::1 -0.014413 # Average percentage of cache occupancy
+system.cpu0.dcache.occ_blocks::0 145.981294 # Average occupied blocks per context
+system.cpu0.dcache.occ_blocks::1 -7.379294 # Average occupied blocks per context
system.cpu0.dcache.overall_accesses 46010 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 40298.324022 # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 31029.205607 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_miss_latency 39543.224299 # average overall miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 29330.466830 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 45115 # number of overall hits
-system.cpu0.dcache.overall_miss_latency 36067000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate 0.019452 # miss rate for overall accesses
-system.cpu0.dcache.overall_misses 895 # number of overall misses
-system.cpu0.dcache.overall_mshr_hits 467 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency 13280500 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate 0.009302 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses 428 # number of overall MSHR misses
+system.cpu0.dcache.overall_hits 45154 # number of overall hits
+system.cpu0.dcache.overall_miss_latency 33849000 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate 0.018605 # miss rate for overall accesses
+system.cpu0.dcache.overall_misses 856 # number of overall misses
+system.cpu0.dcache.overall_mshr_hits 449 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_miss_latency 11937500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate 0.008846 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_misses 407 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.dcache.replacements 10 # number of replacements
system.cpu0.dcache.sampled_refs 176 # Sample count of references to valid blocks.
system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse 141.792519 # Cycle average of tags in use
-system.cpu0.dcache.total_refs 28676 # Total number of references to valid blocks.
+system.cpu0.dcache.tagsinuse 138.602000 # Cycle average of tags in use
+system.cpu0.dcache.total_refs 28675 # Total number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.writebacks 6 # number of writebacks
-system.cpu0.decode.DECODE:BlockedCycles 52836 # Number of cycles decode is blocked
-system.cpu0.decode.DECODE:DecodedInsts 451840 # Number of instructions handled by decode
-system.cpu0.decode.DECODE:IdleCycles 164219 # Number of cycles decode is idle
-system.cpu0.decode.DECODE:RunCycles 154431 # Number of cycles decode is running
+system.cpu0.decode.DECODE:BlockedCycles 52020 # Number of cycles decode is blocked
+system.cpu0.decode.DECODE:DecodedInsts 451824 # Number of instructions handled by decode
+system.cpu0.decode.DECODE:IdleCycles 163842 # Number of cycles decode is idle
+system.cpu0.decode.DECODE:RunCycles 154430 # Number of cycles decode is running
system.cpu0.decode.DECODE:SquashCycles 44292 # Number of cycles decode is squashing
-system.cpu0.decode.DECODE:UnblockCycles 75 # Number of cycles decode is unblocking
-system.cpu0.fetch.Branches 70853 # Number of branches that fetch encountered
-system.cpu0.fetch.CacheLines 87025 # Number of cache lines fetched
-system.cpu0.fetch.Cycles 242792 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.IcacheSquashes 20665 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.Insts 457882 # Number of instructions fetch has processed
+system.cpu0.decode.DECODE:UnblockCycles 74 # Number of cycles decode is unblocking
+system.cpu0.fetch.Branches 70848 # Number of branches that fetch encountered
+system.cpu0.fetch.CacheLines 87024 # Number of cache lines fetched
+system.cpu0.fetch.Cycles 242789 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.IcacheSquashes 20667 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.Insts 457866 # Number of instructions fetch has processed
system.cpu0.fetch.SquashCycles 42477 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.branchRate 0.163254 # Number of branch fetches per cycle
-system.cpu0.fetch.icacheStallCycles 87025 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.branchRate 0.163675 # Number of branch fetches per cycle
+system.cpu0.fetch.icacheStallCycles 87024 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.predictedBranches 44089 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.rate 1.055013 # Number of inst fetches per cycle
-system.cpu0.fetch.rateDist::samples 415853 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 1.101067 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.125993 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rate 1.057774 # Number of inst fetches per cycle
+system.cpu0.fetch.rateDist::samples 414658 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.104202 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.128179 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 260123 62.55% 62.55% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 86799 20.87% 83.42% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 1004 0.24% 83.67% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 21052 5.06% 88.73% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 1074 0.26% 88.99% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 20905 5.03% 94.01% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 680 0.16% 94.18% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 710 0.17% 94.35% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 23506 5.65% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 258930 62.44% 62.44% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 86799 20.93% 83.38% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 1004 0.24% 83.62% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 21052 5.08% 88.70% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 1074 0.26% 88.95% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 20905 5.04% 94.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 680 0.16% 94.16% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 710 0.17% 94.33% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 23504 5.67% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 415853 # Number of instructions fetched each cycle (Total)
-system.cpu0.icache.ReadReq_accesses 87025 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency 37067.241379 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 35094.029851 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_hits 86155 # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_latency 32248500 # number of ReadReq miss cycles
+system.cpu0.fetch.rateDist::total 414658 # Number of instructions fetched each cycle (Total)
+system.cpu0.icache.ReadReq_accesses 87024 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_avg_miss_latency 37020.114943 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 35068.011958 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_hits 86154 # number of ReadReq hits
+system.cpu0.icache.ReadReq_miss_latency 32207500 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_rate 0.009997 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_misses 870 # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_hits 200 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_miss_latency 23513000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate 0.007699 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_misses 670 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_hits 201 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_miss_latency 23460500 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate 0.007688 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_misses 669 # number of ReadReq MSHR misses
system.cpu0.icache.avg_blocked_cycles::no_mshrs 10250 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs 128.781764 # Average number of references to valid blocks.
+system.cpu0.icache.avg_refs 128.973054 # Average number of references to valid blocks.
system.cpu0.icache.blocked::no_mshrs 2 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_mshrs 20500 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.demand_accesses 87025 # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency 37067.241379 # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 35094.029851 # average overall mshr miss latency
-system.cpu0.icache.demand_hits 86155 # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency 32248500 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_accesses 87024 # number of demand (read+write) accesses
+system.cpu0.icache.demand_avg_miss_latency 37020.114943 # average overall miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency 35068.011958 # average overall mshr miss latency
+system.cpu0.icache.demand_hits 86154 # number of demand (read+write) hits
+system.cpu0.icache.demand_miss_latency 32207500 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_rate 0.009997 # miss rate for demand accesses
system.cpu0.icache.demand_misses 870 # number of demand (read+write) misses
-system.cpu0.icache.demand_mshr_hits 200 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency 23513000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate 0.007699 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses 670 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_hits 201 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_miss_latency 23460500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_rate 0.007688 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_misses 669 # number of demand (read+write) MSHR misses
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.occ_%::0 0.526442 # Average percentage of cache occupancy
-system.cpu0.icache.occ_blocks::0 269.538121 # Average occupied blocks per context
-system.cpu0.icache.overall_accesses 87025 # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency 37067.241379 # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 35094.029851 # average overall mshr miss latency
+system.cpu0.icache.occ_%::0 0.526858 # Average percentage of cache occupancy
+system.cpu0.icache.occ_blocks::0 269.751047 # Average occupied blocks per context
+system.cpu0.icache.overall_accesses 87024 # number of overall (read+write) accesses
+system.cpu0.icache.overall_avg_miss_latency 37020.114943 # average overall miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 35068.011958 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits 86155 # number of overall hits
-system.cpu0.icache.overall_miss_latency 32248500 # number of overall miss cycles
+system.cpu0.icache.overall_hits 86154 # number of overall hits
+system.cpu0.icache.overall_miss_latency 32207500 # number of overall miss cycles
system.cpu0.icache.overall_miss_rate 0.009997 # miss rate for overall accesses
system.cpu0.icache.overall_misses 870 # number of overall misses
-system.cpu0.icache.overall_mshr_hits 200 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency 23513000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate 0.007699 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses 670 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_hits 201 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_miss_latency 23460500 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_rate 0.007688 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_misses 669 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu0.icache.replacements 363 # number of replacements
-system.cpu0.icache.sampled_refs 669 # Sample count of references to valid blocks.
+system.cpu0.icache.sampled_refs 668 # Sample count of references to valid blocks.
system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse 269.538121 # Cycle average of tags in use
-system.cpu0.icache.total_refs 86155 # Total number of references to valid blocks.
+system.cpu0.icache.tagsinuse 269.751047 # Cycle average of tags in use
+system.cpu0.icache.total_refs 86154 # Total number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu0.icache.writebacks 0 # number of writebacks
-system.cpu0.idleCycles 18153 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.idleCycles 18200 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.iew.EXEC:branches 44503 # Number of branches executed
system.cpu0.iew.EXEC:nop 59775 # number of nop insts executed
-system.cpu0.iew.EXEC:rate 0.434987 # Inst execution rate
+system.cpu0.iew.EXEC:rate 0.436141 # Inst execution rate
system.cpu0.iew.EXEC:refs 66647 # number of memory reference insts executed
system.cpu0.iew.EXEC:stores 22312 # Number of stores executed
system.cpu0.iew.EXEC:swp 0 # number of swp insts executed
system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.iew.WB:producers 92594 # num instructions producing a value
-system.cpu0.iew.WB:rate 0.431358 # insts written-back per cycle
+system.cpu0.iew.WB:rate 0.432502 # insts written-back per cycle
system.cpu0.iew.WB:sent 187507 # cumulative count of insts sent to commit
system.cpu0.iew.branchMispredicts 42628 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewBlockCycles 24 # Number of cycles IEW is blocking
system.cpu0.iew.iewSquashCycles 44292 # Number of cycles IEW is squashing
system.cpu0.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking
system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread.0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread.0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.lsq.thread.0.forwLoads 19578 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread.0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.memOrderViolationEvents 197 # Number of memory order violations
system.cpu0.iew.predictedNotTakenIncorrect 962 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.predictedTakenIncorrect 41666 # Number of branches that were predicted taken incorrectly
-system.cpu0.ipc 0.269095 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.269095 # IPC: Total IPC of All Threads
+system.cpu0.ipc 0.269809 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.269809 # IPC: Total IPC of All Threads
system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntAlu 164239 70.86% 70.86% # Type of FU issued
system.cpu0.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.86% # Type of FU issued
system.cpu0.iq.ISSUE:fu_full::MemWrite 68 51.13% 100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.ISSUE:issued_per_cycle::samples 415853 # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.557327 # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::stdev 0.948090 # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::samples 414658 # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.558933 # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::stdev 0.948995 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::0 281858 67.78% 67.78% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::1 66212 15.92% 83.70% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::2 42876 10.31% 94.01% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::3 21783 5.24% 99.25% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::0 280664 67.69% 67.69% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::1 66211 15.97% 83.65% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::2 42876 10.34% 93.99% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::3 21783 5.25% 99.25% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::4 1770 0.43% 99.67% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::5 926 0.22% 99.90% # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::6 279 0.07% 99.96% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::5 925 0.22% 99.90% # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:issued_per_cycle::6 280 0.07% 99.96% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::7 123 0.03% 99.99% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::8 26 0.01% 100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:issued_per_cycle::total 415853 # Number of insts issued each cycle
-system.cpu0.iq.ISSUE:rate 0.534016 # Inst issue rate
+system.cpu0.iq.ISSUE:issued_per_cycle::total 414658 # Number of insts issued each cycle
+system.cpu0.iq.ISSUE:rate 0.535432 # Inst issue rate
system.cpu0.iq.iqInstsAdded 236227 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqInstsIssued 231766 # Number of instructions issued
system.cpu0.iq.iqNonSpecInstsAdded 20775 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqSquashedInstsExamined 98225 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedInstsExamined 98222 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedNonSpecRemoved 20216 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.iqSquashedOperandsExamined 15756 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.memDep0.conflictingStores 107 # Number of conflicting stores.
system.cpu0.memDep0.insertedLoads 45739 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 43021 # Number of stores inserted to the mem dependence unit.
-system.cpu0.numCycles 434006 # number of cpu cycles simulated
+system.cpu0.numCycles 432858 # number of cpu cycles simulated
system.cpu0.rename.RENAME:BlockCycles 32 # Number of cycles rename is blocking
system.cpu0.rename.RENAME:CommittedMaps 96356 # Number of HB maps that are committed
-system.cpu0.rename.RENAME:IdleCycles 185616 # Number of cycles rename is idle
+system.cpu0.rename.RENAME:IdleCycles 185237 # Number of cycles rename is idle
system.cpu0.rename.RENAME:LSQFullEvents 5 # Number of times rename has blocked due to LSQ full
system.cpu0.rename.RENAME:RenameLookups 505980 # Number of register rename lookups that rename has made
system.cpu0.rename.RENAME:RenamedInsts 324358 # Number of instructions processed by rename
system.cpu0.rename.RENAME:RenamedOperands 242034 # Number of destination operands rename has renamed
-system.cpu0.rename.RENAME:RunCycles 133139 # Number of cycles rename is running
+system.cpu0.rename.RENAME:RunCycles 133140 # Number of cycles rename is running
system.cpu0.rename.RENAME:SquashCycles 44292 # Number of cycles rename is squashing
-system.cpu0.rename.RENAME:UnblockCycles 355 # Number of cycles rename is unblocking
+system.cpu0.rename.RENAME:UnblockCycles 353 # Number of cycles rename is unblocking
system.cpu0.rename.RENAME:UndoneMaps 145678 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.RENAME:serializeStallCycles 52419 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RENAME:serializeStallCycles 51604 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RENAME:serializingInsts 20781 # count of serializing insts renamed
-system.cpu0.rename.RENAME:skidInsts 83231 # count of insts added to the skid buffer
-system.cpu0.rename.RENAME:tempSerializingInsts 20770 # count of temporary serializing insts renamed
-system.cpu0.timesIdled 339 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.rename.RENAME:skidInsts 83212 # count of insts added to the skid buffer
+system.cpu0.rename.RENAME:tempSerializingInsts 20768 # count of temporary serializing insts renamed
+system.cpu0.timesIdled 340 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls
system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.BPredUnit.BTBHits 53713 # Number of BTB hits
system.cpu1.commit.commitSquashedInsts 134332 # The number of squashed insts skipped by commit
system.cpu1.committedInsts 102085 # Number of Instructions Simulated
system.cpu1.committedInsts_total 102085 # Number of Instructions Simulated
-system.cpu1.cpi 3.876926 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 3.876926 # CPI: Total CPI of All Threads
+system.cpu1.cpi 3.872714 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 3.872714 # CPI: Total CPI of All Threads
system.cpu1.dcache.ReadReq_accesses 28866 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_avg_miss_latency 18882.352941 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 16694.285714 # average ReadReq mshr miss latency
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.occ_%::0 0.053188 # Average percentage of cache occupancy
-system.cpu1.dcache.occ_blocks::0 27.232391 # Average occupied blocks per context
+system.cpu1.dcache.occ_%::0 0.053273 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_%::1 -0.013192 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_blocks::0 27.275525 # Average occupied blocks per context
+system.cpu1.dcache.occ_blocks::1 -6.754298 # Average occupied blocks per context
system.cpu1.dcache.overall_accesses 39333 # number of overall (read+write) accesses
system.cpu1.dcache.overall_avg_miss_latency 20707.207207 # average overall miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency 16197.552448 # average overall mshr miss latency
system.cpu1.dcache.replacements 2 # number of replacements
system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks.
system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse 27.232391 # Cycle average of tags in use
+system.cpu1.dcache.tagsinuse 20.521228 # Cycle average of tags in use
system.cpu1.dcache.total_refs 21040 # Total number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.writebacks 1 # number of writebacks
system.cpu1.fetch.IcacheSquashes 9132 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.Insts 410532 # Number of instructions fetch has processed
system.cpu1.fetch.SquashCycles 29946 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.branchRate 0.211405 # Number of branch fetches per cycle
+system.cpu1.fetch.branchRate 0.211635 # Number of branch fetches per cycle
system.cpu1.fetch.icacheStallCycles 82467 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.predictedBranches 53713 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.rate 1.037284 # Number of inst fetches per cycle
-system.cpu1.fetch.rateDist::samples 392867 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.044964 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 1.945559 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rate 1.038412 # Number of inst fetches per cycle
+system.cpu1.fetch.rateDist::samples 392437 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.046109 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 1.946317 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 235421 59.92% 59.92% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 84908 21.61% 81.54% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 20175 5.14% 86.67% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 13313 3.39% 90.06% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 2697 0.69% 90.75% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 17066 4.34% 95.09% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1329 0.34% 95.43% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 2421 0.62% 96.05% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 15537 3.95% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 234991 59.88% 59.88% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 84908 21.64% 81.52% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 20175 5.14% 86.66% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 13313 3.39% 90.05% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 2697 0.69% 90.74% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 17066 4.35% 95.09% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1329 0.34% 95.42% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 2421 0.62% 96.04% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 15537 3.96% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 392867 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::total 392437 # Number of instructions fetched each cycle (Total)
system.cpu1.icache.ReadReq_accesses 82467 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_avg_miss_latency 14489.768076 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11935.534591 # average ReadReq mshr miss latency
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.occ_%::0 0.182938 # Average percentage of cache occupancy
-system.cpu1.icache.occ_blocks::0 93.664377 # Average occupied blocks per context
+system.cpu1.icache.occ_%::0 0.183206 # Average percentage of cache occupancy
+system.cpu1.icache.occ_blocks::0 93.801528 # Average occupied blocks per context
system.cpu1.icache.overall_accesses 82467 # number of overall (read+write) accesses
system.cpu1.icache.overall_avg_miss_latency 14489.768076 # average overall miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency 11935.534591 # average overall mshr miss latency
system.cpu1.icache.replacements 524 # number of replacements
system.cpu1.icache.sampled_refs 636 # Sample count of references to valid blocks.
system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse 93.664377 # Cycle average of tags in use
+system.cpu1.icache.tagsinuse 93.801528 # Cycle average of tags in use
system.cpu1.icache.total_refs 81734 # Total number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.icache.writebacks 0 # number of writebacks
system.cpu1.idleCycles 2909 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.iew.EXEC:branches 36547 # Number of branches executed
system.cpu1.iew.EXEC:nop 47873 # number of nop insts executed
-system.cpu1.iew.EXEC:rate 0.410224 # Inst execution rate
+system.cpu1.iew.EXEC:rate 0.410671 # Inst execution rate
system.cpu1.iew.EXEC:refs 47615 # number of memory reference insts executed
system.cpu1.iew.EXEC:stores 12164 # Number of stores executed
system.cpu1.iew.EXEC:swp 0 # number of swp insts executed
system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.iew.WB:producers 73225 # num instructions producing a value
-system.cpu1.iew.WB:rate 0.401065 # insts written-back per cycle
+system.cpu1.iew.WB:rate 0.401501 # insts written-back per cycle
system.cpu1.iew.WB:sent 158983 # cumulative count of insts sent to commit
system.cpu1.iew.branchMispredicts 30400 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
system.cpu1.iew.memOrderViolationEvents 694 # Number of memory order violations
system.cpu1.iew.predictedNotTakenIncorrect 1033 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.predictedTakenIncorrect 29367 # Number of branches that were predicted taken incorrectly
-system.cpu1.ipc 0.257936 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.257936 # IPC: Total IPC of All Threads
+system.cpu1.ipc 0.258217 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.258217 # IPC: Total IPC of All Threads
system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntAlu 137441 70.15% 70.15% # Type of FU issued
system.cpu1.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.15% # Type of FU issued
system.cpu1.iq.ISSUE:fu_full::MemWrite 145 77.96% 100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.ISSUE:issued_per_cycle::samples 392867 # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.498716 # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::stdev 0.955880 # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::samples 392437 # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.499262 # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::stdev 0.956261 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::0 276221 70.31% 70.31% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::1 71375 18.17% 88.48% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::0 275791 70.28% 70.28% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::1 71375 18.19% 88.46% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::2 23368 5.95% 94.42% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::3 13587 3.46% 97.88% # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::4 5437 1.38% 99.27% # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:issued_per_cycle::4 5437 1.39% 99.27% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::5 2194 0.56% 99.83% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::6 490 0.12% 99.95% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::7 161 0.04% 99.99% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:issued_per_cycle::total 392867 # Number of insts issued each cycle
-system.cpu1.iq.ISSUE:rate 0.495050 # Inst issue rate
+system.cpu1.iq.ISSUE:issued_per_cycle::total 392437 # Number of insts issued each cycle
+system.cpu1.iq.ISSUE:rate 0.495589 # Inst issue rate
system.cpu1.iq.iqInstsAdded 196258 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqInstsIssued 195929 # Number of instructions issued
system.cpu1.iq.iqNonSpecInstsAdded 17531 # Number of non-speculative instructions added to the IQ
system.cpu1.memDep0.conflictingStores 87 # Number of conflicting stores.
system.cpu1.memDep0.insertedLoads 39543 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 20654 # Number of stores inserted to the mem dependence unit.
-system.cpu1.numCycles 395776 # number of cpu cycles simulated
+system.cpu1.numCycles 395346 # number of cpu cycles simulated
system.cpu1.rename.RENAME:CommittedMaps 85194 # Number of HB maps that are committed
system.cpu1.rename.RENAME:IdleCycles 186916 # Number of cycles rename is idle
system.cpu1.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full
system.cpu2.commit.commitSquashedInsts 138030 # The number of squashed insts skipped by commit
system.cpu2.committedInsts 104211 # Number of Instructions Simulated
system.cpu2.committedInsts_total 104211 # Number of Instructions Simulated
-system.cpu2.cpi 3.794734 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 3.794734 # CPI: Total CPI of All Threads
+system.cpu2.cpi 3.790608 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 3.790608 # CPI: Total CPI of All Threads
system.cpu2.dcache.ReadReq_accesses 28582 # number of ReadReq accesses(hits+misses)
system.cpu2.dcache.ReadReq_avg_miss_latency 19289.473684 # average ReadReq miss latency
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 17373.563218 # average ReadReq mshr miss latency
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.dcache.occ_%::0 0.056939 # Average percentage of cache occupancy
-system.cpu2.dcache.occ_blocks::0 29.152957 # Average occupied blocks per context
+system.cpu2.dcache.occ_%::0 0.057032 # Average percentage of cache occupancy
+system.cpu2.dcache.occ_%::1 -0.010468 # Average percentage of cache occupancy
+system.cpu2.dcache.occ_blocks::0 29.200191 # Average occupied blocks per context
+system.cpu2.dcache.occ_blocks::1 -5.359479 # Average occupied blocks per context
system.cpu2.dcache.overall_accesses 39944 # number of overall (read+write) accesses
system.cpu2.dcache.overall_avg_miss_latency 21080.118694 # average overall miss latency
system.cpu2.dcache.overall_avg_mshr_miss_latency 16776.408451 # average overall mshr miss latency
system.cpu2.dcache.replacements 2 # number of replacements
system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks.
system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu2.dcache.tagsinuse 29.152957 # Cycle average of tags in use
+system.cpu2.dcache.tagsinuse 23.840712 # Cycle average of tags in use
system.cpu2.dcache.total_refs 21963 # Total number of references to valid blocks.
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.dcache.writebacks 1 # number of writebacks
system.cpu2.fetch.IcacheSquashes 10044 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.Insts 412447 # Number of instructions fetch has processed
system.cpu2.fetch.SquashCycles 30579 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.branchRate 0.205860 # Number of branch fetches per cycle
+system.cpu2.fetch.branchRate 0.206084 # Number of branch fetches per cycle
system.cpu2.fetch.icacheStallCycles 81347 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.predictedBranches 52073 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.rate 1.042974 # Number of inst fetches per cycle
-system.cpu2.fetch.rateDist::samples 390306 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.056727 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 1.974128 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rate 1.044109 # Number of inst fetches per cycle
+system.cpu2.fetch.rateDist::samples 389876 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.057893 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 1.974904 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 234764 60.15% 60.15% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 83865 21.49% 81.64% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 17837 4.57% 86.21% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 14411 3.69% 89.90% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 2742 0.70% 90.60% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 234334 60.10% 60.10% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 83865 21.51% 81.62% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 17837 4.58% 86.19% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 14411 3.70% 89.89% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 2742 0.70% 90.59% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 16550 4.24% 94.84% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 1358 0.35% 95.19% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 2423 0.62% 95.81% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 16356 4.19% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 1358 0.35% 95.18% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 2423 0.62% 95.80% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 16356 4.20% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 390306 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::total 389876 # Number of instructions fetched each cycle (Total)
system.cpu2.icache.ReadReq_accesses 81347 # number of ReadReq accesses(hits+misses)
system.cpu2.icache.ReadReq_avg_miss_latency 18963.235294 # average ReadReq miss latency
system.cpu2.icache.ReadReq_avg_mshr_miss_latency 16003.955696 # average ReadReq mshr miss latency
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.icache.occ_%::0 0.191179 # Average percentage of cache occupancy
-system.cpu2.icache.occ_blocks::0 97.883584 # Average occupied blocks per context
+system.cpu2.icache.occ_%::0 0.191472 # Average percentage of cache occupancy
+system.cpu2.icache.occ_blocks::0 98.033912 # Average occupied blocks per context
system.cpu2.icache.overall_accesses 81347 # number of overall (read+write) accesses
system.cpu2.icache.overall_avg_miss_latency 18963.235294 # average overall miss latency
system.cpu2.icache.overall_avg_mshr_miss_latency 16003.955696 # average overall mshr miss latency
system.cpu2.icache.replacements 522 # number of replacements
system.cpu2.icache.sampled_refs 632 # Sample count of references to valid blocks.
system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu2.icache.tagsinuse 97.883584 # Cycle average of tags in use
+system.cpu2.icache.tagsinuse 98.033912 # Cycle average of tags in use
system.cpu2.icache.total_refs 80599 # Total number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu2.icache.writebacks 0 # number of writebacks
system.cpu2.idleCycles 5147 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.iew.EXEC:branches 37149 # Number of branches executed
system.cpu2.iew.EXEC:nop 47058 # number of nop insts executed
-system.cpu2.iew.EXEC:rate 0.419532 # Inst execution rate
+system.cpu2.iew.EXEC:rate 0.419988 # Inst execution rate
system.cpu2.iew.EXEC:refs 49104 # number of memory reference insts executed
system.cpu2.iew.EXEC:stores 13043 # Number of stores executed
system.cpu2.iew.EXEC:swp 0 # number of swp insts executed
system.cpu2.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.iew.WB:producers 75620 # num instructions producing a value
-system.cpu2.iew.WB:rate 0.410403 # insts written-back per cycle
+system.cpu2.iew.WB:rate 0.410849 # insts written-back per cycle
system.cpu2.iew.WB:sent 162544 # cumulative count of insts sent to commit
system.cpu2.iew.branchMispredicts 31026 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
system.cpu2.iew.memOrderViolationEvents 698 # Number of memory order violations
system.cpu2.iew.predictedNotTakenIncorrect 1011 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.predictedTakenIncorrect 30015 # Number of branches that were predicted taken incorrectly
-system.cpu2.ipc 0.263523 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.263523 # IPC: Total IPC of All Threads
+system.cpu2.ipc 0.263810 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.263810 # IPC: Total IPC of All Threads
system.cpu2.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::IntAlu 141339 70.63% 70.63% # Type of FU issued
system.cpu2.iq.ISSUE:FU_type_0::IntMult 0 0.00% 70.63% # Type of FU issued
system.cpu2.iq.ISSUE:fu_full::MemWrite 145 80.11% 100.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu2.iq.ISSUE:issued_per_cycle::samples 390306 # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::mean 0.512741 # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::stdev 0.969063 # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::samples 389876 # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::mean 0.513307 # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::stdev 0.969448 # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::0 272942 69.93% 69.93% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::1 69416 17.79% 87.72% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::2 25173 6.45% 94.16% # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::3 14490 3.71% 97.88% # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::0 272512 69.90% 69.90% # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::1 69416 17.80% 87.70% # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::2 25173 6.46% 94.16% # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:issued_per_cycle::3 14490 3.72% 97.87% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::4 5424 1.39% 99.27% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::5 2186 0.56% 99.83% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::6 485 0.12% 99.95% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:issued_per_cycle::total 390306 # Number of insts issued each cycle
-system.cpu2.iq.ISSUE:rate 0.506068 # Inst issue rate
+system.cpu2.iq.ISSUE:issued_per_cycle::total 389876 # Number of insts issued each cycle
+system.cpu2.iq.ISSUE:rate 0.506619 # Inst issue rate
system.cpu2.iq.iqInstsAdded 201728 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqInstsIssued 200126 # Number of instructions issued
system.cpu2.iq.iqNonSpecInstsAdded 17248 # Number of non-speculative instructions added to the IQ
system.cpu2.memDep0.conflictingStores 92 # Number of conflicting stores.
system.cpu2.memDep0.insertedLoads 40176 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 22433 # Number of stores inserted to the mem dependence unit.
-system.cpu2.numCycles 395453 # number of cpu cycles simulated
+system.cpu2.numCycles 395023 # number of cpu cycles simulated
system.cpu2.rename.RENAME:CommittedMaps 87600 # Number of HB maps that are committed
system.cpu2.rename.RENAME:IdleCycles 183597 # Number of cycles rename is idle
system.cpu2.rename.RENAME:RenameLookups 458439 # Number of register rename lookups that rename has made
system.cpu3.commit.commitSquashedInsts 152378 # The number of squashed insts skipped by commit
system.cpu3.committedInsts 111128 # Number of Instructions Simulated
system.cpu3.committedInsts_total 111128 # Number of Instructions Simulated
-system.cpu3.cpi 3.555675 # CPI: Cycles Per Instruction
-system.cpu3.cpi_total 3.555675 # CPI: Total CPI of All Threads
+system.cpu3.cpi 3.551805 # CPI: Cycles Per Instruction
+system.cpu3.cpi_total 3.551805 # CPI: Total CPI of All Threads
system.cpu3.dcache.ReadReq_accesses 28485 # number of ReadReq accesses(hits+misses)
system.cpu3.dcache.ReadReq_avg_miss_latency 16678.947368 # average ReadReq miss latency
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 14832.258065 # average ReadReq mshr miss latency
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.dcache.occ_%::0 0.054820 # Average percentage of cache occupancy
-system.cpu3.dcache.occ_blocks::0 28.067737 # Average occupied blocks per context
+system.cpu3.dcache.occ_%::0 0.054908 # Average percentage of cache occupancy
+system.cpu3.dcache.occ_%::1 -0.015654 # Average percentage of cache occupancy
+system.cpu3.dcache.occ_blocks::0 28.113086 # Average occupied blocks per context
+system.cpu3.dcache.occ_blocks::1 -8.014642 # Average occupied blocks per context
system.cpu3.dcache.overall_accesses 42223 # number of overall (read+write) accesses
system.cpu3.dcache.overall_avg_miss_latency 19067.398119 # average overall miss latency
system.cpu3.dcache.overall_avg_mshr_miss_latency 14707.865169 # average overall mshr miss latency
system.cpu3.dcache.replacements 2 # number of replacements
system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks.
system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu3.dcache.tagsinuse 28.067737 # Cycle average of tags in use
+system.cpu3.dcache.tagsinuse 20.098444 # Cycle average of tags in use
system.cpu3.dcache.total_refs 24305 # Total number of references to valid blocks.
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.dcache.writebacks 1 # number of writebacks
system.cpu3.fetch.IcacheSquashes 12405 # Number of outstanding Icache misses that were squashed
system.cpu3.fetch.Insts 435938 # Number of instructions fetch has processed
system.cpu3.fetch.SquashCycles 32818 # Number of cycles fetch has spent squashing
-system.cpu3.fetch.branchRate 0.208197 # Number of branch fetches per cycle
+system.cpu3.fetch.branchRate 0.208424 # Number of branch fetches per cycle
system.cpu3.fetch.icacheStallCycles 80954 # Number of cycles fetch is stalled on an Icache miss
system.cpu3.fetch.predictedBranches 48405 # Number of branches that fetch has predicted taken
-system.cpu3.fetch.rate 1.103263 # Number of inst fetches per cycle
-system.cpu3.fetch.rateDist::samples 392614 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean 1.110348 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev 2.081451 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rate 1.104465 # Number of inst fetches per cycle
+system.cpu3.fetch.rateDist::samples 392184 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.111565 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 2.082267 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0 237879 60.59% 60.59% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1 82939 21.12% 81.71% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2 12394 3.16% 84.87% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3 15941 4.06% 88.93% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4 2706 0.69% 89.62% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5 16830 4.29% 93.91% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 237449 60.55% 60.55% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 82939 21.15% 81.69% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 12394 3.16% 84.85% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3 15941 4.06% 88.92% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4 2706 0.69% 89.61% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 16830 4.29% 93.90% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::6 1787 0.46% 94.36% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7 2412 0.61% 94.98% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8 19726 5.02% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 2412 0.62% 94.97% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 19726 5.03% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total 392614 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::total 392184 # Number of instructions fetched each cycle (Total)
system.cpu3.icache.ReadReq_accesses 80954 # number of ReadReq accesses(hits+misses)
system.cpu3.icache.ReadReq_avg_miss_latency 13933.423913 # average ReadReq miss latency
system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11485.915493 # average ReadReq mshr miss latency
system.cpu3.icache.fast_writes 0 # number of fast writes performed
system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.icache.occ_%::0 0.188794 # Average percentage of cache occupancy
-system.cpu3.icache.occ_blocks::0 96.662446 # Average occupied blocks per context
+system.cpu3.icache.occ_%::0 0.189077 # Average percentage of cache occupancy
+system.cpu3.icache.occ_blocks::0 96.807549 # Average occupied blocks per context
system.cpu3.icache.overall_accesses 80954 # number of overall (read+write) accesses
system.cpu3.icache.overall_avg_miss_latency 13933.423913 # average overall miss latency
system.cpu3.icache.overall_avg_mshr_miss_latency 11485.915493 # average overall mshr miss latency
system.cpu3.icache.replacements 527 # number of replacements
system.cpu3.icache.sampled_refs 639 # Sample count of references to valid blocks.
system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu3.icache.tagsinuse 96.662446 # Cycle average of tags in use
+system.cpu3.icache.tagsinuse 96.807549 # Cycle average of tags in use
system.cpu3.icache.total_refs 80218 # Total number of references to valid blocks.
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu3.icache.writebacks 0 # number of writebacks
system.cpu3.idleCycles 2521 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.iew.EXEC:branches 39408 # Number of branches executed
system.cpu3.iew.EXEC:nop 47237 # number of nop insts executed
-system.cpu3.iew.EXEC:rate 0.449348 # Inst execution rate
+system.cpu3.iew.EXEC:rate 0.449837 # Inst execution rate
system.cpu3.iew.EXEC:refs 53769 # number of memory reference insts executed
system.cpu3.iew.EXEC:stores 15425 # Number of stores executed
system.cpu3.iew.EXEC:swp 0 # number of swp insts executed
system.cpu3.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu3.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.iew.WB:producers 82697 # num instructions producing a value
-system.cpu3.iew.WB:rate 0.440189 # insts written-back per cycle
+system.cpu3.iew.WB:rate 0.440668 # insts written-back per cycle
system.cpu3.iew.WB:sent 174194 # cumulative count of insts sent to commit
system.cpu3.iew.branchMispredicts 33269 # Number of branch mispredicts detected at execute
system.cpu3.iew.iewBlockCycles 0 # Number of cycles IEW is blocking
system.cpu3.iew.memOrderViolationEvents 701 # Number of memory order violations
system.cpu3.iew.predictedNotTakenIncorrect 1030 # Number of branches that were predicted not taken incorrectly
system.cpu3.iew.predictedTakenIncorrect 32239 # Number of branches that were predicted taken incorrectly
-system.cpu3.ipc 0.281241 # IPC: Instructions Per Cycle
-system.cpu3.ipc_total 0.281241 # IPC: Total IPC of All Threads
+system.cpu3.ipc 0.281547 # IPC: Instructions Per Cycle
+system.cpu3.ipc_total 0.281547 # IPC: Total IPC of All Threads
system.cpu3.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::IntAlu 153538 71.57% 71.57% # Type of FU issued
system.cpu3.iq.ISSUE:FU_type_0::IntMult 0 0.00% 71.57% # Type of FU issued
system.cpu3.iq.ISSUE:fu_full::MemWrite 145 77.96% 100.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu3.iq.ISSUE:issued_per_cycle::samples 392614 # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::mean 0.546409 # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::stdev 0.998842 # Number of insts issued each cycle
+system.cpu3.iq.ISSUE:issued_per_cycle::samples 392184 # Number of insts issued each cycle
+system.cpu3.iq.ISSUE:issued_per_cycle::mean 0.547009 # Number of insts issued each cycle
+system.cpu3.iq.ISSUE:issued_per_cycle::stdev 0.999225 # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::0 270914 69.00% 69.00% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::1 66150 16.85% 85.85% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::2 30383 7.74% 93.59% # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::3 16859 4.29% 97.88% # Number of insts issued each cycle
+system.cpu3.iq.ISSUE:issued_per_cycle::0 270484 68.97% 68.97% # Number of insts issued each cycle
+system.cpu3.iq.ISSUE:issued_per_cycle::1 66150 16.87% 85.84% # Number of insts issued each cycle
+system.cpu3.iq.ISSUE:issued_per_cycle::2 30383 7.75% 93.58% # Number of insts issued each cycle
+system.cpu3.iq.ISSUE:issued_per_cycle::3 16859 4.30% 97.88% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::4 5420 1.38% 99.26% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::5 2202 0.56% 99.83% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::6 491 0.13% 99.95% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:issued_per_cycle::total 392614 # Number of insts issued each cycle
-system.cpu3.iq.ISSUE:rate 0.542923 # Inst issue rate
+system.cpu3.iq.ISSUE:issued_per_cycle::total 392184 # Number of insts issued each cycle
+system.cpu3.iq.ISSUE:rate 0.543515 # Inst issue rate
system.cpu3.iq.iqInstsAdded 219886 # Number of instructions added to the IQ (excludes non-spec)
system.cpu3.iq.iqInstsIssued 214528 # Number of instructions issued
system.cpu3.iq.iqNonSpecInstsAdded 17591 # Number of non-speculative instructions added to the IQ
system.cpu3.memDep0.conflictingStores 96 # Number of conflicting stores.
system.cpu3.memDep0.insertedLoads 43341 # Number of loads inserted to the mem dependence unit.
system.cpu3.memDep0.insertedStores 27172 # Number of stores inserted to the mem dependence unit.
-system.cpu3.numCycles 395135 # number of cpu cycles simulated
+system.cpu3.numCycles 394705 # number of cpu cycles simulated
system.cpu3.rename.RENAME:CommittedMaps 94626 # Number of HB maps that are committed
system.cpu3.rename.RENAME:IdleCycles 180043 # Number of cycles rename is idle
system.cpu3.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full
system.l2c.ReadExReq_accesses::2 13 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::3 12 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency::0 73122.340426 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 572791.666667 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::2 528730.769231 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::3 572791.666667 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 1747436.442990 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40312.977099 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency 6873500 # number of ReadExReq miss cycles
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+system.l2c.ReadExReq_avg_miss_latency::total 1747309.328969 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40309.160305 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency 6873000 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_misses::2 13 # number of ReadExReq misses
system.l2c.ReadExReq_misses::3 12 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency 5281000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency 5280500 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_rate::0 1.393617 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::1 10.916667 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::2 10.076923 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::3 10.916667 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 33.303873 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_misses 131 # number of ReadExReq MSHR misses
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system.l2c.ReadReq_accesses::1 650 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::2 646 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::3 653 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2701 # number of ReadReq accesses(hits+misses)
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-system.l2c.ReadReq_avg_miss_latency::1 2229653.846154 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::2 362318.750000 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::3 4830916.666667 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 7486314.864571 # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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+system.l2c.ReadReq_avg_miss_latency::total 7473281.536775 # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 39996.370236 # average ReadReq mshr miss latency
system.l2c.ReadReq_hits::0 295 # number of ReadReq hits
system.l2c.ReadReq_hits::1 637 # number of ReadReq hits
system.l2c.ReadReq_hits::2 566 # number of ReadReq hits
system.l2c.ReadReq_hits::3 647 # number of ReadReq hits
system.l2c.ReadReq_hits::total 2145 # number of ReadReq hits
-system.l2c.ReadReq_miss_latency 28985500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate::0 0.607713 # miss rate for ReadReq accesses
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system.l2c.ReadReq_miss_rate::1 0.020000 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::2 0.123839 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::3 0.009188 # miss rate for ReadReq accesses
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system.l2c.ReadReq_misses::1 13 # number of ReadReq misses
system.l2c.ReadReq_misses::2 80 # number of ReadReq misses
system.l2c.ReadReq_misses::3 6 # number of ReadReq misses
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system.l2c.ReadReq_mshr_hits 4 # number of ReadReq MSHR hits
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-system.l2c.ReadReq_mshr_miss_rate::3 0.845329 # mshr miss rate for ReadReq accesses
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-system.l2c.ReadReq_mshr_misses 552 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_accesses::0 53 # number of UpgradeReq accesses(hits+misses)
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system.l2c.UpgradeReq_accesses::1 21 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::2 21 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::3 22 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 117 # number of UpgradeReq accesses(hits+misses)
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-system.l2c.UpgradeReq_avg_miss_latency::1 62333.333333 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::2 62333.333333 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::3 59500 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 208864.779874 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40038.461538 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency 1309000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
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+system.l2c.UpgradeReq_avg_miss_latency::2 7500 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::3 7159.090909 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 27784.090909 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_hits::0 3 # number of UpgradeReq hits
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system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 53 # number of UpgradeReq misses
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system.l2c.UpgradeReq_misses::1 21 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::2 21 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::3 22 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 117 # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency 4684500 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_rate::0 2.207547 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1 5.571429 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::2 5.571429 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::3 5.318182 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 18.668586 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses 117 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_misses::total 92 # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency 3680000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_rate::0 2.967742 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1 4.380952 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::2 4.380952 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::3 4.181818 # mshr miss rate for UpgradeReq accesses
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system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0 9 # number of Writeback hits
system.l2c.Writeback_hits::total 9 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 4.003738 # Average number of references to valid blocks.
+system.l2c.avg_refs 3.873418 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 846 # number of demand (read+write) accesses
+system.l2c.demand_accesses::0 845 # number of demand (read+write) accesses
system.l2c.demand_accesses::1 662 # number of demand (read+write) accesses
system.l2c.demand_accesses::2 659 # number of demand (read+write) accesses
system.l2c.demand_accesses::3 665 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2832 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 65079.854809 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 1434360 # average overall miss latency
-system.l2c.demand_avg_miss_latency::2 385580.645161 # average overall miss latency
-system.l2c.demand_avg_miss_latency::3 1992166.666667 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 3877187.166637 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40060.029283 # average overall mshr miss latency
+system.l2c.demand_accesses::total 2831 # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency::0 65104.545455 # average overall miss latency
+system.l2c.demand_avg_miss_latency::1 1432300 # average overall miss latency
+system.l2c.demand_avg_miss_latency::2 385026.881720 # average overall miss latency
+system.l2c.demand_avg_miss_latency::3 1989305.555556 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 3871736.982731 # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency 40056.451613 # average overall mshr miss latency
system.l2c.demand_hits::0 295 # number of demand (read+write) hits
system.l2c.demand_hits::1 637 # number of demand (read+write) hits
system.l2c.demand_hits::2 566 # number of demand (read+write) hits
system.l2c.demand_hits::3 647 # number of demand (read+write) hits
system.l2c.demand_hits::total 2145 # number of demand (read+write) hits
-system.l2c.demand_miss_latency 35859000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate::0 0.651300 # miss rate for demand accesses
+system.l2c.demand_miss_latency 35807500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate::0 0.650888 # miss rate for demand accesses
system.l2c.demand_miss_rate::1 0.037764 # miss rate for demand accesses
system.l2c.demand_miss_rate::2 0.141123 # miss rate for demand accesses
system.l2c.demand_miss_rate::3 0.027068 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.857255 # miss rate for demand accesses
-system.l2c.demand_misses::0 551 # number of demand (read+write) misses
+system.l2c.demand_miss_rate::total 0.856843 # miss rate for demand accesses
+system.l2c.demand_misses::0 550 # number of demand (read+write) misses
system.l2c.demand_misses::1 25 # number of demand (read+write) misses
system.l2c.demand_misses::2 93 # number of demand (read+write) misses
system.l2c.demand_misses::3 18 # number of demand (read+write) misses
-system.l2c.demand_misses::total 687 # number of demand (read+write) misses
+system.l2c.demand_misses::total 686 # number of demand (read+write) misses
system.l2c.demand_mshr_hits 4 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 27361000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 0.807329 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 1.031722 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2 1.036419 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::3 1.027068 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 3.902537 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses 683 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_miss_latency 27318500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate::0 0.807101 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1 1.030211 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::2 1.034901 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::3 1.025564 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 3.897777 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses 682 # number of demand (read+write) MSHR misses
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.005570 # Average percentage of cache occupancy
+system.l2c.occ_%::0 0.005838 # Average percentage of cache occupancy
system.l2c.occ_%::1 0.000152 # Average percentage of cache occupancy
-system.l2c.occ_%::2 0.001067 # Average percentage of cache occupancy
+system.l2c.occ_%::2 0.001069 # Average percentage of cache occupancy
system.l2c.occ_%::3 0.000056 # Average percentage of cache occupancy
system.l2c.occ_%::4 0.000091 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 365.031703 # Average occupied blocks per context
-system.l2c.occ_blocks::1 9.942146 # Average occupied blocks per context
-system.l2c.occ_blocks::2 69.921003 # Average occupied blocks per context
-system.l2c.occ_blocks::3 3.643564 # Average occupied blocks per context
-system.l2c.occ_blocks::4 5.939892 # Average occupied blocks per context
-system.l2c.overall_accesses::0 846 # number of overall (read+write) accesses
+system.l2c.occ_blocks::0 382.596816 # Average occupied blocks per context
+system.l2c.occ_blocks::1 9.957586 # Average occupied blocks per context
+system.l2c.occ_blocks::2 70.028959 # Average occupied blocks per context
+system.l2c.occ_blocks::3 3.647267 # Average occupied blocks per context
+system.l2c.occ_blocks::4 5.949685 # Average occupied blocks per context
+system.l2c.overall_accesses::0 845 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 662 # number of overall (read+write) accesses
system.l2c.overall_accesses::2 659 # number of overall (read+write) accesses
system.l2c.overall_accesses::3 665 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2832 # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency::0 65079.854809 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 1434360 # average overall miss latency
-system.l2c.overall_avg_miss_latency::2 385580.645161 # average overall miss latency
-system.l2c.overall_avg_miss_latency::3 1992166.666667 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 3877187.166637 # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 40060.029283 # average overall mshr miss latency
+system.l2c.overall_accesses::total 2831 # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency::0 65104.545455 # average overall miss latency
+system.l2c.overall_avg_miss_latency::1 1432300 # average overall miss latency
+system.l2c.overall_avg_miss_latency::2 385026.881720 # average overall miss latency
+system.l2c.overall_avg_miss_latency::3 1989305.555556 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 3871736.982731 # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 40056.451613 # average overall mshr miss latency
system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.l2c.overall_hits::0 295 # number of overall hits
system.l2c.overall_hits::1 637 # number of overall hits
system.l2c.overall_hits::2 566 # number of overall hits
system.l2c.overall_hits::3 647 # number of overall hits
system.l2c.overall_hits::total 2145 # number of overall hits
-system.l2c.overall_miss_latency 35859000 # number of overall miss cycles
-system.l2c.overall_miss_rate::0 0.651300 # miss rate for overall accesses
+system.l2c.overall_miss_latency 35807500 # number of overall miss cycles
+system.l2c.overall_miss_rate::0 0.650888 # miss rate for overall accesses
system.l2c.overall_miss_rate::1 0.037764 # miss rate for overall accesses
system.l2c.overall_miss_rate::2 0.141123 # miss rate for overall accesses
system.l2c.overall_miss_rate::3 0.027068 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.857255 # miss rate for overall accesses
-system.l2c.overall_misses::0 551 # number of overall misses
+system.l2c.overall_miss_rate::total 0.856843 # miss rate for overall accesses
+system.l2c.overall_misses::0 550 # number of overall misses
system.l2c.overall_misses::1 25 # number of overall misses
system.l2c.overall_misses::2 93 # number of overall misses
system.l2c.overall_misses::3 18 # number of overall misses
-system.l2c.overall_misses::total 687 # number of overall misses
+system.l2c.overall_misses::total 686 # number of overall misses
system.l2c.overall_mshr_hits 4 # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency 27361000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate::0 0.807329 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 1.031722 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2 1.036419 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::3 1.027068 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 3.902537 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses 683 # number of overall MSHR misses
+system.l2c.overall_mshr_miss_latency 27318500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate::0 0.807101 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1 1.030211 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::2 1.034901 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::3 1.025564 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 3.897777 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses 682 # number of overall MSHR misses
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.replacements 0 # number of replacements
-system.l2c.sampled_refs 535 # Sample count of references to valid blocks.
+system.l2c.sampled_refs 553 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 454.478308 # Cycle average of tags in use
+system.l2c.tagsinuse 472.180314 # Cycle average of tags in use
system.l2c.total_refs 2142 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 0 # number of writebacks
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simout
+Redirecting stderr to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jul 1 2010 14:40:18
-M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate
-M5 started Jul 1 2010 14:40:33
-M5 executing on phenom
+M5 compiled Aug 26 2010 13:03:41
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:04:32
+M5 executing on zizzer
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
---------- Begin Simulation Statistics ----------
-host_inst_rate 339283 # Simulator instruction rate (inst/s)
-host_mem_usage 1120212 # Number of bytes of host memory used
-host_seconds 2.00 # Real time elapsed on the host
-host_tick_rate 43931389 # Simulator tick rate (ticks/s)
+host_inst_rate 1027581 # Simulator instruction rate (inst/s)
+host_mem_usage 1133204 # Number of bytes of host memory used
+host_seconds 0.66 # Real time elapsed on the host
+host_tick_rate 133016942 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 677340 # Number of instructions simulated
sim_seconds 0.000088 # Number of seconds simulated
system.cpu0.dcache.SwapReq_miss_rate 0.642857 # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_misses 27 # number of SwapReq misses
system.cpu0.dcache.WriteReq_accesses 27755 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_hits 27561 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_rate 0.006990 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 194 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_hits 27578 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_rate 0.006377 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses 177 # number of WriteReq misses
system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs 362.347059 # Average number of references to valid blocks.
system.cpu0.dcache.demand_accesses 82337 # number of demand (read+write) accesses
system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.dcache.demand_hits 81992 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits 82009 # number of demand (read+write) hits
system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.004190 # miss rate for demand accesses
-system.cpu0.dcache.demand_misses 345 # number of demand (read+write) misses
+system.cpu0.dcache.demand_miss_rate 0.003984 # miss rate for demand accesses
+system.cpu0.dcache.demand_misses 328 # number of demand (read+write) misses
system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 81992 # number of overall hits
+system.cpu0.dcache.overall_hits 82009 # number of overall hits
system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate 0.004190 # miss rate for overall accesses
-system.cpu0.dcache.overall_misses 345 # number of overall misses
+system.cpu0.dcache.overall_miss_rate 0.003984 # miss rate for overall accesses
+system.cpu0.dcache.overall_misses 328 # number of overall misses
system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
system.l2c.ReadReq_misses::2 3 # number of ReadReq misses
system.l2c.ReadReq_misses::3 3 # number of ReadReq misses
system.l2c.ReadReq_misses::total 423 # number of ReadReq misses
-system.l2c.UpgradeReq_accesses::0 48 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0 31 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::1 19 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::2 20 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::3 19 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 106 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_accesses::total 89 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_hits::0 2 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
+system.l2c.UpgradeReq_miss_rate::0 0.935484 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::3 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 4 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses::0 48 # number of UpgradeReq misses
+system.l2c.UpgradeReq_miss_rate::total 3.935484 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_misses::0 29 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::1 19 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::2 20 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::3 19 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 106 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses
system.l2c.Writeback_accesses::0 9 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_hits::0 9 # number of Writeback hits
system.l2c.Writeback_hits::total 9 # number of Writeback hits
system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 2.968447 # Average number of references to valid blocks.
+system.l2c.avg_refs 2.870892 # Average number of references to valid blocks.
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.occ_%::0 0.004314 # Average percentage of cache occupancy
+system.l2c.occ_%::0 0.004495 # Average percentage of cache occupancy
system.l2c.occ_%::1 0.001011 # Average percentage of cache occupancy
system.l2c.occ_%::2 0.000044 # Average percentage of cache occupancy
system.l2c.occ_%::3 0.000029 # Average percentage of cache occupancy
system.l2c.occ_%::4 0.000098 # Average percentage of cache occupancy
-system.l2c.occ_blocks::0 282.753459 # Average occupied blocks per context
+system.l2c.occ_blocks::0 294.613840 # Average occupied blocks per context
system.l2c.occ_blocks::1 66.228089 # Average occupied blocks per context
system.l2c.occ_blocks::2 2.865859 # Average occupied blocks per context
system.l2c.occ_blocks::3 1.883074 # Average occupied blocks per context
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.replacements 0 # number of replacements
-system.l2c.sampled_refs 412 # Sample count of references to valid blocks.
+system.l2c.sampled_refs 426 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 360.120529 # Cycle average of tags in use
+system.l2c.tagsinuse 371.980910 # Cycle average of tags in use
system.l2c.total_refs 1223 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 0 # number of writebacks
env=
errout=cerr
euid=100
-executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
gid=100
input=cin
max_stack_size=67108864
+Redirecting stdout to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simout
+Redirecting stderr to build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Jul 1 2010 14:40:18
-M5 revision acd9f15a9c7c 7493 default qtip tip simobj-parent-fix-stats-udpate
-M5 started Jul 1 2010 14:40:36
-M5 executing on phenom
+M5 compiled Aug 26 2010 13:03:41
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 13:03:45
+M5 executing on zizzer
command line: build/SPARC_SE/m5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3
Iteration 10 completed
PASSED :-)
-Exiting @ tick 263312000 because target called exit()
+Exiting @ tick 262295000 because target called exit()
---------- Begin Simulation Statistics ----------
-host_inst_rate 940671 # Simulator instruction rate (inst/s)
-host_mem_usage 202704 # Number of bytes of host memory used
-host_seconds 0.69 # Real time elapsed on the host
-host_tick_rate 380696818 # Simulator tick rate (ticks/s)
+host_inst_rate 583465 # Simulator instruction rate (inst/s)
+host_mem_usage 215700 # Number of bytes of host memory used
+host_seconds 1.12 # Real time elapsed on the host
+host_tick_rate 235218525 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_insts 650423 # Number of instructions simulated
-sim_seconds 0.000263 # Number of seconds simulated
-sim_ticks 263312000 # Number of ticks simulated
+sim_seconds 0.000262 # Number of seconds simulated
+sim_ticks 262295000 # Number of ticks simulated
system.cpu0.dcache.ReadReq_accesses 48920 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_avg_miss_latency 29314.814815 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 26314.814815 # average ReadReq mshr miss latency
system.cpu0.dcache.SwapReq_mshr_miss_rate 0.619048 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_misses 26 # number of SwapReq MSHR misses
system.cpu0.dcache.WriteReq_accesses 24924 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency 41030 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 38030 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_hits 24724 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency 8206000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate 0.008024 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 200 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_miss_latency 7606000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate 0.008024 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses 200 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_avg_miss_latency 39191.256831 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36191.256831 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_hits 24741 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency 7172000 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate 0.007342 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses 183 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_miss_latency 6623000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate 0.007342 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_misses 183 # number of WriteReq MSHR misses
system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.dcache.avg_refs 329.464706 # Average number of references to valid blocks.
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.demand_accesses 73844 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 35787.292818 # average overall miss latency
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+system.l2c.occ_blocks::0 286.079338 # Average occupied blocks per context
+system.l2c.occ_blocks::1 57.730266 # Average occupied blocks per context
+system.l2c.occ_blocks::2 2.608262 # Average occupied blocks per context
+system.l2c.occ_blocks::3 1.731871 # Average occupied blocks per context
+system.l2c.occ_blocks::4 5.597892 # Average occupied blocks per context
system.l2c.overall_accesses::0 637 # number of overall (read+write) accesses
system.l2c.overall_accesses::1 383 # number of overall (read+write) accesses
system.l2c.overall_accesses::2 382 # number of overall (read+write) accesses
system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.l2c.replacements 0 # number of replacements
-system.l2c.sampled_refs 412 # Sample count of references to valid blocks.
+system.l2c.sampled_refs 427 # Sample count of references to valid blocks.
system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse 340.827042 # Cycle average of tags in use
+system.l2c.tagsinuse 353.747628 # Cycle average of tags in use
system.l2c.total_refs 1217 # Total number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.writebacks 0 # number of writebacks
-system.cpu2: completed 10000 read accesses @26695905
-system.cpu6: completed 10000 read accesses @26791606
-system.cpu5: completed 10000 read accesses @26792650
-system.cpu1: completed 10000 read accesses @26942582
-system.cpu7: completed 10000 read accesses @27101805
-system.cpu3: completed 10000 read accesses @27218798
-system.cpu0: completed 10000 read accesses @27391241
-system.cpu4: completed 10000 read accesses @27569488
-system.cpu6: completed 20000 read accesses @53349763
-system.cpu2: completed 20000 read accesses @53503744
-system.cpu5: completed 20000 read accesses @53714174
-system.cpu7: completed 20000 read accesses @53950546
-system.cpu3: completed 20000 read accesses @54185930
-system.cpu0: completed 20000 read accesses @54225484
-system.cpu1: completed 20000 read accesses @54276231
-system.cpu4: completed 20000 read accesses @54597598
-system.cpu0: completed 30000 read accesses @80866924
-system.cpu7: completed 30000 read accesses @80945592
-system.cpu6: completed 30000 read accesses @81027764
-system.cpu2: completed 30000 read accesses @81035060
-system.cpu4: completed 30000 read accesses @81318103
-system.cpu5: completed 30000 read accesses @81377684
-system.cpu3: completed 30000 read accesses @81429000
-system.cpu1: completed 30000 read accesses @81820011
-system.cpu2: completed 40000 read accesses @106813760
-system.cpu3: completed 40000 read accesses @106974444
-system.cpu6: completed 40000 read accesses @106993530
-system.cpu7: completed 40000 read accesses @107261306
-system.cpu5: completed 40000 read accesses @107310319
-system.cpu0: completed 40000 read accesses @107652944
-system.cpu1: completed 40000 read accesses @107852182
-system.cpu4: completed 40000 read accesses @108023308
-system.cpu2: completed 50000 read accesses @133853751
-system.cpu6: completed 50000 read accesses @134086054
-system.cpu3: completed 50000 read accesses @134273902
-system.cpu7: completed 50000 read accesses @134574750
-system.cpu0: completed 50000 read accesses @134577823
-system.cpu1: completed 50000 read accesses @134778033
-system.cpu5: completed 50000 read accesses @134896821
-system.cpu4: completed 50000 read accesses @135759299
-system.cpu2: completed 60000 read accesses @161211555
-system.cpu3: completed 60000 read accesses @161581369
-system.cpu6: completed 60000 read accesses @161831828
-system.cpu0: completed 60000 read accesses @161942121
-system.cpu1: completed 60000 read accesses @162215822
-system.cpu7: completed 60000 read accesses @162487402
-system.cpu5: completed 60000 read accesses @162758928
-system.cpu4: completed 60000 read accesses @162827113
-system.cpu2: completed 70000 read accesses @188493937
-system.cpu1: completed 70000 read accesses @189035964
-system.cpu3: completed 70000 read accesses @189157397
-system.cpu6: completed 70000 read accesses @189252661
-system.cpu0: completed 70000 read accesses @189257028
-system.cpu7: completed 70000 read accesses @189348164
-system.cpu5: completed 70000 read accesses @189769120
-system.cpu4: completed 70000 read accesses @191028989
-system.cpu2: completed 80000 read accesses @215328997
-system.cpu7: completed 80000 read accesses @216072978
-system.cpu1: completed 80000 read accesses @216240482
-system.cpu6: completed 80000 read accesses @216413258
-system.cpu3: completed 80000 read accesses @216551338
-system.cpu5: completed 80000 read accesses @216884718
-system.cpu0: completed 80000 read accesses @216894493
-system.cpu4: completed 80000 read accesses @218108705
-system.cpu2: completed 90000 read accesses @242508064
-system.cpu7: completed 90000 read accesses @242698389
-system.cpu1: completed 90000 read accesses @242967798
-system.cpu5: completed 90000 read accesses @243529194
-system.cpu3: completed 90000 read accesses @243598064
-system.cpu6: completed 90000 read accesses @243621284
-system.cpu0: completed 90000 read accesses @244529131
-system.cpu4: completed 90000 read accesses @246008618
-system.cpu2: completed 100000 read accesses @269223994
+system.cpu4: completed 10000 read accesses @26562477
+system.cpu0: completed 10000 read accesses @26652602
+system.cpu6: completed 10000 read accesses @26653472
+system.cpu1: completed 10000 read accesses @27123929
+system.cpu2: completed 10000 read accesses @27264228
+system.cpu5: completed 10000 read accesses @27378204
+system.cpu3: completed 10000 read accesses @27427879
+system.cpu7: completed 10000 read accesses @27467412
+system.cpu4: completed 20000 read accesses @53181289
+system.cpu2: completed 20000 read accesses @53547298
+system.cpu0: completed 20000 read accesses @53713168
+system.cpu5: completed 20000 read accesses @54003765
+system.cpu6: completed 20000 read accesses @54078034
+system.cpu1: completed 20000 read accesses @54428010
+system.cpu7: completed 20000 read accesses @54428201
+system.cpu3: completed 20000 read accesses @54538530
+system.cpu2: completed 30000 read accesses @79806624
+system.cpu4: completed 30000 read accesses @80477319
+system.cpu0: completed 30000 read accesses @80890126
+system.cpu6: completed 30000 read accesses @80990962
+system.cpu5: completed 30000 read accesses @81492903
+system.cpu1: completed 30000 read accesses @81521875
+system.cpu7: completed 30000 read accesses @81619556
+system.cpu3: completed 30000 read accesses @82646612
+system.cpu2: completed 40000 read accesses @105920590
+system.cpu4: completed 40000 read accesses @106535590
+system.cpu0: completed 40000 read accesses @106901597
+system.cpu6: completed 40000 read accesses @107068434
+system.cpu5: completed 40000 read accesses @107463528
+system.cpu7: completed 40000 read accesses @108151860
+system.cpu1: completed 40000 read accesses @108295057
+system.cpu3: completed 40000 read accesses @109438245
+system.cpu2: completed 50000 read accesses @132968913
+system.cpu4: completed 50000 read accesses @133752042
+system.cpu0: completed 50000 read accesses @133897400
+system.cpu6: completed 50000 read accesses @134191909
+system.cpu5: completed 50000 read accesses @135041964
+system.cpu7: completed 50000 read accesses @135432848
+system.cpu1: completed 50000 read accesses @136127784
+system.cpu3: completed 50000 read accesses @137167267
+system.cpu2: completed 60000 read accesses @160901546
+system.cpu4: completed 60000 read accesses @161170032
+system.cpu6: completed 60000 read accesses @161540559
+system.cpu0: completed 60000 read accesses @161693235
+system.cpu5: completed 60000 read accesses @161854598
+system.cpu1: completed 60000 read accesses @163372166
+system.cpu7: completed 60000 read accesses @163560871
+system.cpu3: completed 60000 read accesses @163979808
+system.cpu2: completed 70000 read accesses @188319198
+system.cpu5: completed 70000 read accesses @188516414
+system.cpu4: completed 70000 read accesses @188575474
+system.cpu6: completed 70000 read accesses @188767860
+system.cpu0: completed 70000 read accesses @189199394
+system.cpu3: completed 70000 read accesses @191117524
+system.cpu7: completed 70000 read accesses @191140120
+system.cpu1: completed 70000 read accesses @191152245
+system.cpu2: completed 80000 read accesses @215320174
+system.cpu4: completed 80000 read accesses @215525158
+system.cpu6: completed 80000 read accesses @215775319
+system.cpu5: completed 80000 read accesses @215842805
+system.cpu0: completed 80000 read accesses @216807334
+system.cpu3: completed 80000 read accesses @218320776
+system.cpu1: completed 80000 read accesses @218370718
+system.cpu7: completed 80000 read accesses @218390295
+system.cpu2: completed 90000 read accesses @241936829
+system.cpu4: completed 90000 read accesses @242559490
+system.cpu6: completed 90000 read accesses @242752208
+system.cpu5: completed 90000 read accesses @242972513
+system.cpu0: completed 90000 read accesses @243685265
+system.cpu1: completed 90000 read accesses @244981315
+system.cpu3: completed 90000 read accesses @245492671
+system.cpu7: completed 90000 read accesses @245612294
+system.cpu2: completed 100000 read accesses @268782974
hack: be nice to actually delete the event here
+Redirecting stdout to build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest/simout
+Redirecting stderr to build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest/simerr
M5 Simulator System
Copyright (c) 2001-2008
All Rights Reserved
-M5 compiled Aug 20 2010 12:21:09
-M5 revision c4b5df973361+ 7570+ default qtip tip brad/regress_updates
-M5 started Aug 20 2010 12:21:31
-M5 executing on SC2B0629
-command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest
+M5 compiled Aug 26 2010 11:51:59
+M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
+M5 started Aug 26 2010 11:52:02
+M5 executing on zizzer
+command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 269223994 because maximum number of loads reached
+Exiting @ tick 268782974 because maximum number of loads reached
---------- Begin Simulation Statistics ----------
-host_mem_usage 328092 # Number of bytes of host memory used
-host_seconds 194.79 # Real time elapsed on the host
-host_tick_rate 1382135 # Simulator tick rate (ticks/s)
+host_mem_usage 330984 # Number of bytes of host memory used
+host_seconds 227.97 # Real time elapsed on the host
+host_tick_rate 1179002 # Simulator tick rate (ticks/s)
sim_freq 1000000000000 # Frequency of simulated ticks
sim_seconds 0.000269 # Number of seconds simulated
-sim_ticks 269223994 # Number of ticks simulated
-system.cpu0.l1c.ReadReq_accesses 44447 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_avg_miss_latency 35088.024234 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 34084.129987 # average ReadReq mshr miss latency
+sim_ticks 268782974 # Number of ticks simulated
+system.cpu0.l1c.ReadReq_accesses 44543 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_avg_miss_latency 36123.721103 # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 35119.772902 # average ReadReq mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.ReadReq_hits 7474 # number of ReadReq hits
-system.cpu0.l1c.ReadReq_miss_latency 1297309520 # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_rate 0.831845 # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_misses 36973 # number of ReadReq misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency 1260192538 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate 0.831845 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_misses 36973 # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 822421052 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_accesses 24198 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_avg_miss_latency 49598.993348 # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 48595.207082 # average WriteReq mshr miss latency
+system.cpu0.l1c.ReadReq_hits 7515 # number of ReadReq hits
+system.cpu0.l1c.ReadReq_miss_latency 1337589145 # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_rate 0.831287 # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_misses 37028 # number of ReadReq misses
+system.cpu0.l1c.ReadReq_mshr_miss_latency 1300414951 # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate 0.831287 # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_misses 37028 # number of ReadReq MSHR misses
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 858196470 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_accesses 24111 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_avg_miss_latency 46338.684471 # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 45334.813405 # average WriteReq mshr miss latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_hits 898 # number of WriteReq hits
-system.cpu0.l1c.WriteReq_miss_latency 1155656545 # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_rate 0.962889 # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_misses 23300 # number of WriteReq misses
-system.cpu0.l1c.WriteReq_mshr_miss_latency 1132268325 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_rate 0.962889 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_misses 23300 # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 529109628 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3801.306186 # average number of cycles each access was blocked
+system.cpu0.l1c.WriteReq_hits 1045 # number of WriteReq hits
+system.cpu0.l1c.WriteReq_miss_latency 1068848096 # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_rate 0.956659 # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_misses 23066 # number of WriteReq misses
+system.cpu0.l1c.WriteReq_mshr_miss_latency 1045692806 # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_rate 0.956659 # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_misses 23066 # number of WriteReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 565288628 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3782.376120 # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu0.l1c.avg_refs 0.409698 # Average number of references to valid blocks.
-system.cpu0.l1c.blocked::no_mshrs 69363 # number of cycles access was blocked
+system.cpu0.l1c.avg_refs 0.409032 # Average number of references to valid blocks.
+system.cpu0.l1c.blocked::no_mshrs 69095 # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked_cycles::no_mshrs 263670001 # number of cycles access was blocked
+system.cpu0.l1c.blocked_cycles::no_mshrs 261343278 # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
-system.cpu0.l1c.demand_accesses 68645 # number of demand (read+write) accesses
-system.cpu0.l1c.demand_avg_miss_latency 40697.593699 # average overall miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency 39693.741194 # average overall mshr miss latency
-system.cpu0.l1c.demand_hits 8372 # number of demand (read+write) hits
-system.cpu0.l1c.demand_miss_latency 2452966065 # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_rate 0.878039 # miss rate for demand accesses
-system.cpu0.l1c.demand_misses 60273 # number of demand (read+write) misses
+system.cpu0.l1c.demand_accesses 68654 # number of demand (read+write) accesses
+system.cpu0.l1c.demand_avg_miss_latency 40044.550887 # average overall miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency 39040.632293 # average overall mshr miss latency
+system.cpu0.l1c.demand_hits 8560 # number of demand (read+write) hits
+system.cpu0.l1c.demand_miss_latency 2406437241 # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_rate 0.875317 # miss rate for demand accesses
+system.cpu0.l1c.demand_misses 60094 # number of demand (read+write) misses
system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.l1c.demand_mshr_miss_latency 2392460863 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_rate 0.878039 # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_misses 60273 # number of demand (read+write) MSHR misses
+system.cpu0.l1c.demand_mshr_miss_latency 2346107757 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_rate 0.875317 # mshr miss rate for demand accesses
+system.cpu0.l1c.demand_mshr_misses 60094 # number of demand (read+write) MSHR misses
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.l1c.occ_%::0 0.676527 # Average percentage of cache occupancy
-system.cpu0.l1c.occ_%::1 -0.006962 # Average percentage of cache occupancy
-system.cpu0.l1c.occ_blocks::0 346.381949 # Average occupied blocks per context
-system.cpu0.l1c.occ_blocks::1 -3.564360 # Average occupied blocks per context
-system.cpu0.l1c.overall_accesses 68645 # number of overall (read+write) accesses
-system.cpu0.l1c.overall_avg_miss_latency 40697.593699 # average overall miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency 39693.741194 # average overall mshr miss latency
+system.cpu0.l1c.occ_%::0 0.677077 # Average percentage of cache occupancy
+system.cpu0.l1c.occ_%::1 -0.479198 # Average percentage of cache occupancy
+system.cpu0.l1c.occ_blocks::0 346.663656 # Average occupied blocks per context
+system.cpu0.l1c.occ_blocks::1 -245.349451 # Average occupied blocks per context
+system.cpu0.l1c.overall_accesses 68654 # number of overall (read+write) accesses
+system.cpu0.l1c.overall_avg_miss_latency 40044.550887 # average overall miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency 39040.632293 # average overall mshr miss latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_hits 8372 # number of overall hits
-system.cpu0.l1c.overall_miss_latency 2452966065 # number of overall miss cycles
-system.cpu0.l1c.overall_miss_rate 0.878039 # miss rate for overall accesses
-system.cpu0.l1c.overall_misses 60273 # number of overall misses
+system.cpu0.l1c.overall_hits 8560 # number of overall hits
+system.cpu0.l1c.overall_miss_latency 2406437241 # number of overall miss cycles
+system.cpu0.l1c.overall_miss_rate 0.875317 # miss rate for overall accesses
+system.cpu0.l1c.overall_misses 60094 # number of overall misses
system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.l1c.overall_mshr_miss_latency 2392460863 # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_rate 0.878039 # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_misses 60273 # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_uncacheable_latency 1351530680 # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_miss_latency 2346107757 # number of overall MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_rate 0.875317 # mshr miss rate for overall accesses
+system.cpu0.l1c.overall_mshr_misses 60094 # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_uncacheable_latency 1423485098 # number of overall MSHR uncacheable cycles
system.cpu0.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.l1c.replacements 27642 # number of replacements
-system.cpu0.l1c.sampled_refs 27984 # Sample count of references to valid blocks.
+system.cpu0.l1c.replacements 27651 # number of replacements
+system.cpu0.l1c.sampled_refs 28010 # Sample count of references to valid blocks.
system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu0.l1c.tagsinuse 342.817588 # Cycle average of tags in use
-system.cpu0.l1c.total_refs 11465 # Total number of references to valid blocks.
+system.cpu0.l1c.tagsinuse 101.314205 # Cycle average of tags in use
+system.cpu0.l1c.total_refs 11457 # Total number of references to valid blocks.
system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.writebacks 10964 # number of writebacks
+system.cpu0.l1c.writebacks 10896 # number of writebacks
system.cpu0.num_copies 0 # number of copy accesses completed
-system.cpu0.num_reads 98887 # number of read accesses completed
-system.cpu0.num_writes 53455 # number of write accesses completed
-system.cpu1.l1c.ReadReq_accesses 44742 # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_avg_miss_latency 35246.657121 # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34242.680675 # average ReadReq mshr miss latency
+system.cpu0.num_reads 99124 # number of read accesses completed
+system.cpu0.num_writes 53367 # number of write accesses completed
+system.cpu1.l1c.ReadReq_accesses 44692 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_avg_miss_latency 36448.304577 # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 35444.437717 # average ReadReq mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.ReadReq_hits 7551 # number of ReadReq hits
-system.cpu1.l1c.ReadReq_miss_latency 1310858425 # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_rate 0.831232 # miss rate for ReadReq accesses
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system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
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system.cpu7.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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-system.l2c.ReadReq_mshr_miss_rate::0 2.712183 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 2.689960 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::2 2.707143 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::3 2.664133 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::4 2.719144 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::5 2.698993 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::6 2.717083 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::7 2.681758 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 21.590396 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses 46617 # number of ReadReq MSHR misses
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-system.l2c.UpgradeReq_accesses::7 2359 # number of UpgradeReq accesses(hits+misses)
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-system.l2c.UpgradeReq_avg_miss_latency::1 222645.489315 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::2 228219.091194 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::3 226698.981794 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::4 224505.763852 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::5 217152.746491 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::6 217152.746491 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::7 216416.323442 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 1770778.378702 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.703945 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency 510526107 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses
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-system.l2c.UpgradeReq_misses::3 2252 # number of UpgradeReq misses
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-system.l2c.UpgradeReq_misses::total 18459 # number of UpgradeReq misses
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-system.l2c.UpgradeReq_mshr_miss_rate::1 8.025294 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::2 8.226196 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::3 8.171403 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::4 8.092348 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::5 7.827308 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::6 7.827308 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::7 7.800763 # mshr miss rate for UpgradeReq accesses
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+system.l2c.ReadReq_misses::2 6017 # number of ReadReq misses
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+system.l2c.ReadReq_misses::4 5927 # number of ReadReq misses
+system.l2c.ReadReq_misses::5 6018 # number of ReadReq misses
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+system.l2c.ReadReq_mshr_misses 46503 # number of ReadReq MSHR misses
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+system.l2c.UpgradeReq_avg_miss_latency::1 172466.495596 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::2 171159.931235 # average UpgradeReq miss latency
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+system.l2c.UpgradeReq_avg_miss_latency::4 174412.376485 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::5 178006.328485 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::6 177898.511205 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::7 168315.439542 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 1388338.493339 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 39999.820703 # average UpgradeReq mshr miss latency
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+system.l2c.UpgradeReq_hits::1 475 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::2 515 # number of UpgradeReq hits
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+system.l2c.UpgradeReq_mshr_miss_rate::6 6.412744 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::7 6.113327 # mshr miss rate for UpgradeReq accesses
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system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency 1720878838 # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses::0 86764 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 86764 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_hits::0 86764 # number of Writeback hits
-system.l2c.Writeback_hits::total 86764 # number of Writeback hits
-system.l2c.avg_blocked_cycles::no_mshrs 6575.500000 # average number of cycles each access was blocked
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+system.l2c.Writeback_accesses::0 86531 # number of Writeback accesses(hits+misses)
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+system.l2c.Writeback_hits::0 86531 # number of Writeback hits
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+system.l2c.avg_blocked_cycles::no_mshrs 6964.928571 # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.avg_refs 2.025850 # Average number of references to valid blocks.
-system.l2c.blocked::no_mshrs 22 # number of cycles access was blocked
+system.l2c.avg_refs 1.997257 # Average number of references to valid blocks.
+system.l2c.blocked::no_mshrs 14 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_mshrs 144661 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_mshrs 97509 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.demand_accesses::0 26600 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 26618 # number of demand (read+write) accesses
-system.l2c.demand_accesses::2 26533 # number of demand (read+write) accesses
-system.l2c.demand_accesses::3 26842 # number of demand (read+write) accesses
-system.l2c.demand_accesses::4 26607 # number of demand (read+write) accesses
-system.l2c.demand_accesses::5 26630 # number of demand (read+write) accesses
-system.l2c.demand_accesses::6 26517 # number of demand (read+write) accesses
-system.l2c.demand_accesses::7 26747 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 213094 # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency::0 398760.755929 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 398006.709116 # average overall miss latency
-system.l2c.demand_avg_miss_latency::2 401224.669099 # average overall miss latency
-system.l2c.demand_avg_miss_latency::3 396429.881860 # average overall miss latency
-system.l2c.demand_avg_miss_latency::4 396404.136316 # average overall miss latency
-system.l2c.demand_avg_miss_latency::5 396945.495935 # average overall miss latency
-system.l2c.demand_avg_miss_latency::6 401462.173836 # average overall miss latency
-system.l2c.demand_avg_miss_latency::7 397488.336220 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 3186722.158311 # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency 40000.457119 # average overall mshr miss latency
-system.l2c.demand_hits::0 11293 # number of demand (read+write) hits
-system.l2c.demand_hits::1 11282 # number of demand (read+write) hits
-system.l2c.demand_hits::2 11320 # number of demand (read+write) hits
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-system.l2c.demand_hits::4 11209 # number of demand (read+write) hits
-system.l2c.demand_hits::5 11253 # number of demand (read+write) hits
-system.l2c.demand_hits::6 11313 # number of demand (read+write) hits
-system.l2c.demand_hits::7 11391 # number of demand (read+write) hits
-system.l2c.demand_hits::total 90506 # number of demand (read+write) hits
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-system.l2c.demand_miss_rate::7 0.574120 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 4.602220 # miss rate for demand accesses
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-system.l2c.demand_misses::1 15336 # number of demand (read+write) misses
-system.l2c.demand_misses::2 15213 # number of demand (read+write) misses
-system.l2c.demand_misses::3 15397 # number of demand (read+write) misses
-system.l2c.demand_misses::4 15398 # number of demand (read+write) misses
-system.l2c.demand_misses::5 15377 # number of demand (read+write) misses
-system.l2c.demand_misses::6 15204 # number of demand (read+write) misses
-system.l2c.demand_misses::7 15356 # number of demand (read+write) misses
-system.l2c.demand_misses::total 122588 # number of demand (read+write) misses
-system.l2c.demand_mshr_hits 1626 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency 4838535294 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate::0 4.547444 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 4.544368 # mshr miss rate for demand accesses
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system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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projects / gem5.git / commitdiff